Re: [RFC PATCH v3 22/28] tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI

On 1/13/23 06:04, Fabiano Rosas wrote: We will soon enable the build without TCG, which does not support many machines, so only run the bcm2835-dma-test when the corresponding machine is present. Signed-off-by: Fabiano Rosas --- tests/qtest/meson.build | 4 ++-- 1 file changed, 2 insertions(+

Re: [RFC PATCH v3 25/28] tests/avocado: Tag TCG tests with accel:tcg

On 1/13/23 06:04, Fabiano Rosas wrote: This allows the test to be skipped when TCG is not present in the QEMU binary. Signed-off-by: Fabiano Rosas --- tests/avocado/boot_linux_console.py | 1 + tests/avocado/reverse_debugging.py | 8 2 files changed, 9 insertions(+) Reviewed-by:

Re: [RFC PATCH v3 24/28] tests/avocado: Skip tests that require a missing accelerator

On 1/13/23 06:04, Fabiano Rosas wrote: If a test was tagged with the "accel" tag and the specified accelerator it not present in the qemu binary, cancel the test. We can now write tests without explicit calls to require_accelerator, just the tag is enough. Signed-off-by: Fabiano Rosas --- tes

Re: [PATCH v10 3/9] KVM: Extend the memslot to support fd-based private memory

On Tue, Jan 10, 2023, Chao Peng wrote: > On Mon, Jan 09, 2023 at 07:32:05PM +, Sean Christopherson wrote: > > On Fri, Jan 06, 2023, Chao Peng wrote: > > > On Thu, Jan 05, 2023 at 11:23:01AM +, Jarkko Sakkinen wrote: > > > > On Fri, Dec 02, 2022 at 02:13:41PM +0800, Chao Peng wrote: > > > >

Re: [RFC PATCH v3 27/28] arm/Kconfig: Always select SEMIHOSTING when TCG is present

On 1/13/23 06:04, Fabiano Rosas wrote: We are about to enable the build without TCG, so CONFIG_SEMIHOSTING and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in default.mak anymore. So reflect the change in a Kconfig. Instead of using semihosting/Kconfig, use a target-specific f

Re: [RFC PATCH v3 28/28] arm/Kconfig: Do not build TCG-only boards on a KVM-only build

On 1/13/23 06:04, Fabiano Rosas wrote: config CHEETAH bool +default y if TCG && (ARM || AARCH64) Shouldn't need both ARM and AARCH64? r`

Re: [PATCH v10 6/9] KVM: Unmap existing mappings when change the memory attributes

On Fri, Dec 02, 2022, Chao Peng wrote: > @@ -785,11 +786,12 @@ struct kvm { > > #if defined(CONFIG_MMU_NOTIFIER) && defined(KVM_ARCH_WANT_MMU_NOTIFIER) > struct mmu_notifier mmu_notifier; > +#endif > unsigned long mmu_invalidate_seq; > long mmu_invalidate_in_progress; > g

Re: [PATCH v10 7/9] KVM: Update lpage info when private/shared memory are mixed

On Fri, Dec 02, 2022, Chao Peng wrote: > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 283cbb83d6ae..7772ab37ac89 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -38,6 +38,7 @@ > #include > > #define __KVM_HAV

Re: [PATCH v10 4/9] KVM: Add KVM_EXIT_MEMORY_FAULT exit

On Fri, Dec 02, 2022, Chao Peng wrote: > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index 99352170c130..d9edb14ce30b 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -6634,6 +6634,28 @@ array field represents return values

Re: [PATCH v10 7/9] KVM: Update lpage info when private/shared memory are mixed

On Fri, Dec 02, 2022, Chao Peng wrote: > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 9a07380f8d3c..5aefcff614d2 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -12362,6 +12362,8 @@ static int kvm_alloc_memslot_metadata(struct kvm *kvm, > if ((slot->b

Re: [PATCH v10 8/9] KVM: Handle page fault for private memory

On Fri, Dec 02, 2022, Chao Peng wrote: > @@ -5599,6 +5652,9 @@ int noinline kvm_mmu_page_fault(struct kvm_vcpu *vcpu, > gpa_t cr2_or_gpa, u64 err > return -EIO; > } > > + if (r == RET_PF_USER) > + return 0; > + > if (r < 0) > return

Re: [PATCH v10 9/9] KVM: Enable and expose KVM_MEM_PRIVATE

On Fri, Dec 02, 2022, Chao Peng wrote: > @@ -10357,6 +10364,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) > > if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) > static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); > + > + if

Re: [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM

On Fri, Dec 02, 2022, Chao Peng wrote: > This patch series implements KVM guest private memory for confidential > computing scenarios like Intel TDX[1]. If a TDX host accesses > TDX-protected guest memory, machine check can happen which can further > crash the running host system, this is terrible

[RFC PATCH 1/5] i386/xen: Implement HYPERVISOR_physdev_op

From: David Woodhouse Just hook up the basic hypercalls to stubs in xen_evtchn.c for now. Signed-off-by: David Woodhouse --- hw/i386/kvm/xen_evtchn.c | 25 hw/i386/kvm/xen_evtchn.h | 11 target/i386/kvm/xen-compat.h | 19 ++ target/i386/kvm/xen-emu.c| 118 +

[RFC PATCH 0/5] Xen PIRQ support

This continues to build on the basic Xen on KVM platform support from https://lore.kernel.org/qemu-devel/20230110122042.1562155-1-dw...@infradead.org/ We're working on hooking up the PV backend devices, and the biggest remaining noticeably missing part was PIRQ support. This allows a Xen guest

[RFC PATCH 2/5] hw/xen: Implement emulated PIRQ hypercall support

From: David Woodhouse This wires up the basic infrastructure but the actual interrupts aren't there yet, so don't advertise it to the guest. Signed-off-by: David Woodhouse --- hw/i386/kvm/trace-events | 4 + hw/i386/kvm/trace.h | 1 + hw/i386/kvm/xen_evtchn.c | 265

[RFC PATCH 3/5] hw/xen: Support GSI mapping to PIRQ

From: David Woodhouse If I advertise XENFEAT_hvm_pirqs then a guest now boots successfully as long as I tell it 'pci=nomsi'. [root@localhost ~]# cat /proc/interrupts CPU0 0: 52 IO-APIC 2-edge timer 1: 16 xen-pirq 1-ioapic-edge i8042 4: 1534 xe

[RFC PATCH 5/5] hw/xen: Support MSI mapping to PIRQ

From: David Woodhouse The way that Xen handles MSI PIRQs is kind of awful. There is a special MSI message which targets a PIRQ. The vector in the low bits of data must be zero. The low 8 bits of the PIRQ# are in the destination ID field, the extended destination ID field is unused, and instead t

[RFC PATCH 4/5] hw/xen: [FIXME] Avoid deadlock in xen_evtchn_set_gsi()

From: David Woodhouse Signed-off-by: David Woodhouse --- hw/i386/kvm/xen_evtchn.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index 18c88229ab..c4103ee98b 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@

Re: [PATCH v4 0/3] tcg: add perfmap and jitdump

On 1/12/23 07:20, Ilya Leoshkevich wrote: v3 -> v4: * s/unsigned long long/uint64_t/g (Richard). * Fix address resolution with TARGET_TB_PCREL again. * Open question: do we need something like get_pc_from_opc()? See FIXME in patch 3. Looks good. I'll queue this to tcg-next. Ideally, w

[PATCH] tcg: Avoid recursion in tcg_gen_mulu2_i32

We have a test for one of TCG_TARGET_HAS_mulu2_i32 or TCG_TARGET_HAS_muluh_i32 being defined, but the test became non-functional when we changed to always define all of these macros. Replace this with a build-time test in tcg_gen_mulu2_i32. Fixes: 25c4d9cc845 ("tcg: Always define all of the TCGOp

Re: [RFC PATCH] testing: probe gdb for supported architectures ahead of time

On 1/5/23 10:15, Alex Bennée wrote: Currently when we encounter a gdb that is old or not built with multiarch in mind we fail rather messily. Try and improve the situation by probing ahead of time and setting HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip and give a more m

Re: Display update issue on M1 Macs

On 2023/01/13 22:43, BALATON Zoltan wrote: On Thu, 5 Jan 2023, BALATON Zoltan wrote: Hello, I got reports from several users trying to run AmigaOS4 on sam460ex on Apple silicon Macs that they get missing graphics that I can't reproduce on x86_64. With help from the users who get the problem

[PATCH v2] net: Strip virtio-net header when dumping

filter-dump specifiees Ethernet as PCAP LinkType, which does not expect virtio-net header. Having virtio-net header in such PCAP file breaks PCAP unconsumable. Unfortunately currently there is no LinkType for virtio-net so for now strip virtio-net header to convert the output to Ethernet. Signed-o

Re: [PATCH v8] xen/pt: reserve PCI slot 2 for Intel igd-passthru

On 1/10/23 3:16 AM, Michael S. Tsirkin wrote: > On Tue, Jan 10, 2023 at 02:08:34AM -0500, Chuck Zmudzinski wrote: >> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, >> as noted in docs/igd-assign.txt in the Qemu source code. >> >> Currently, when the xl toolstack is used to c

Re: [PATCH] net: Strip virtio-net header when dumping

On 2023/01/13 22:40, Philippe Mathieu-Daudé wrote: On 13/1/23 14:08, Akihiko Odaki wrote: filter-dump specifiees Ethernet as PCAP LinkType, which does not expect virtio-net header. Having virtio-net header in such PCAP file breaks PCAP unconsumable. Unfortunately currently there is no LinkType f

[PATCH] target/arm: Fix physical address resolution for MTE

Conversion to probe_access_full missed applying the page offset. Fixes: b8967ddf ("target/arm: Use probe_access_full for MTE") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1416 Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 02/19] hw/net: Add more MII definitions

The definitions will be used by igb. Signed-off-by: Akihiko Odaki --- include/hw/net/mii.h | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index 4ae4dcce7e..c6a767a49a 100644 --- a/include/hw/net/mii.h +++ b/include/hw

[PATCH 03/19] fsl_etsec: Use hw/net/mii.h

hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 11 ++- hw/net/fsl_etsec/etsec.h | 17 - hw/net/fsl_etsec/miim.c | 5 +++-- include/hw/net/mii.h | 1 + 4 files change

[PATCH 04/19] e1000: Use hw/net/mii.h

hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 86 ++-- hw/net/e1000_regs.h| 46 hw/net/e1000e.c| 1 + hw/net/e1000e_core.c | 99 +

[PATCH 01/19] e1000e: Fix the code style

igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 41 hw/net/e1000e.c| 72 ++-- hw/net/e1000e_core.c |

[PATCH 05/19] e1000: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 84 +++--

[PATCH 10/19] e1000e: Use memcpy to intialize registers

Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000

[PATCH 17/19] e1000e: Remove extra pointer indirection

e1000e_write_packet_to_guest() passes the reference of variable ba as a pointer to an array, and that pointer indirection is just unnecessary; all functions which uses the passed reference performs no pointer operation on the pointer and they simply dereference the passed pointer. Remove the extra

[PATCH 00/19] e1000x cleanups (preliminary for IGB)

We are adding a new device named igb, yet another Intel NIC. As the new implementation derives from e1000e, overhaul e1000e implementation first. e1000 has many commonalities with e1000e so we also apply the corresponding changes to the device if possible. This was spun off from: https://patchew.o

[PATCH 08/19] e1000e: Use more constant definitions

The definitions of SW Semaphore Register were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374 Signed-off-by: Akihiko Odaki --- hw/net/e1000_regs.h | 7 +++ hw/net/e1000e_core.c | 49 +++

[PATCH 06/19] e1000e: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 94 +++

[PATCH 09/19] e1000: Use memcpy to intialize registers

Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index d9d

[PATCH 19/19] tests/qtest/libqos/e1000e: Remove duplicate register definitions

The register definitions in tests/qtest/libqos/e1000e.h had names different from hw/net/e1000_regs.h, which made it hard to understand what test codes corresponds to the implementation. Use hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove these duplications. Signed-off-by: Akihiko Od

[PATCH 18/19] tests/qtest/e1000e-test: Fix the code style

igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/e1000e-test.c | 2 +- tests/qtest/libqos/e1000e.c | 6 -- 2 files changed, 5 insertions(+), 3 deletions(-) diff

[PATCH 13/19] e1000: Configure ResettableClass

This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 13 --

[PATCH v2 06/13] igb: Build igb

Currently igb functions identically with e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/Kconfig | 5 + hw/net/meson.build | 2 ++ 2 files changed, 7 insertions(+) diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 1cc1c5775e..

[PATCH v2 13/13] docs/system/devices/igb: Add igb documentation

Signed-off-by: Akihiko Odaki --- MAINTAINERS | 1 + docs/system/device-emulation.rst | 1 + docs/system/devices/igb.rst | 70 3 files changed, 72 insertions(+) create mode 100644 docs/system/devices/igb.rst diff --git a/MAINTAINERS b/

[PATCH v2 01/13] hw/net/net_tx_pkt: Introduce net_tx_pkt_get_eth_hdr

Expose the ethernet header so that igb can utilize it to perform the internal routing among its SR-IOV functions. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/net_tx_pkt.c | 6 ++ hw/net/net_tx_pkt.h | 8 2 files changed, 14 ins

[PATCH v2 02/13] pcie: Introduce pcie_sriov_num_vfs

igb can use this function to change its behavior depending on the number of virtual functions currently enabled. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/pci/pcie_sriov.c | 5 + include/hw/pci

[PATCH 12/19] e1000e: Improve software reset

This change makes e1000e reset more things when software reset was triggered. Some registers are exempted from software reset in the datasheet and this change also implements the behavior accordingly. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 24 +++- 1 file cha

[PATCH v2 04/13] igb: Copy e1000e code

Start off igb implementation by copying e1000e code first as igb resembles e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- MAINTAINERS |5 + hw/net/igb.c| 727 + hw/net/igb_common.h | 102 ++ hw/net/igb_core.c |

[PATCH v2 05/13] igb: Rename identifiers

Rename identifiers of definitions which will be modified later for igb. This will also allow to build igb along with e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/igb.c| 368 +- hw/net/igb_common.h |6 +- hw/net/i

[PATCH v2 00/13] Introduce igb

Based-on: <20230114035919.35251-1-akihiko.od...@daynix.com> ([PATCH 00/19] e1000x cleanups (preliminary for IGB)) igb is a family of Intel's gigabit ethernet controllers. This series implements 82576 emulation in particular. You can see the last patch for the documentation. Note that there is ano

[PATCH 15/19] e1000e: Introduce e1000_rx_desc_union

Before this change, e1000e_write_packet_to_guest() allocated the receive descriptor buffer as an array of uint8_t. This does not ensure the buffer is sufficiently aligned. Introduce e1000_rx_desc_union type, a union type of all receive descriptor types to correct this. Signed-off-by: Akihiko Odak

[PATCH 16/19] e1000e: Set MII_ANER_NWAY

This keeps Windows driver 12.18.9.23 from generating an event with ID 30. The description of the event is as follows: > Intel(R) 82574L Gigabit Network Connection > PROBLEM: The network adapter is configured for auto-negotiation but > the link partner is not. This may result in a duplex mismatch.

[PATCH v2 10/13] tests/qtest/libqos/igb: Copy e1000e code

Start off igb test implementation by copying e1000e code first as igb resembles e1000e. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 + tests/qtest/igb-test.c | 242 +++ tests/qtest/libqos/igb.c | 226

[PATCH v2 12/13] tests/avocado: Add igb test

This automates ethtool tests for igb registers, interrupts, etc. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 1 + .../org.centos/stream/8/x86_64/test-avocado | 1 + tests/avocado/igb.py | 38 +++ 3 files changed, 4

[PATCH v2 08/13] tests/qtest/e1000e-test: Fabricate ethernet header

e1000e understands ethernet header so fabricate something convincing. Signed-off-by: Akihiko Odaki --- tests/qtest/e1000e-test.c | 17 +++-- tests/qtest/libqos/e1000e.h | 2 ++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/

[PATCH v2 09/13] tests/qtest/libqos/e1000e: Export macreg functions

They will be useful for igb testing. Signed-off-by: Akihiko Odaki --- tests/qtest/libqos/e1000e.c | 12 tests/qtest/libqos/e1000e.h | 12 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index 28f

[PATCH 14/19] e1000e: Configure ResettableClass

This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000e.c | 10 +

[PATCH v2 11/13] tests/qtest/libqos/igb: Transform to igb tests

Signed-off-by: Akihiko Odaki --- tests/qtest/fuzz/generic_fuzz_configs.h | 5 + tests/qtest/igb-test.c | 67 ++-- tests/qtest/libqos/igb.c| 139 +--- tests/qtest/libqos/meson.build | 1 + tests/qtest/meson.build

[PATCH 07/19] e1000: Use more constant definitions

The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306 The definitions for E1000_NUM_UNICAST, E1000_MC_T

[PATCH 11/19] e1000e: Remove pending interrupt flags

They are duplicate of running throttling timer flags and incomplete as the flags are not cleared when the interrupts are fired or the device is reset. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 5 ++--- hw/net/e1000e_core.c | 19 +++ hw/net/e1000e_core.h | 2 -- hw

[PATCH v2 03/13] e1000: Split header files

Some definitions in the header files are invalid for igb so extract them to new header files to keep igb from referring to them. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 1 + hw/ne

Re: [PATCH] accel/kvm: Specify default IPA size for arm64

On 1/8/23 22:22, Akihiko Odaki wrote: libvirt uses "none" machine type to test KVM availability. Before this change, QEMU used to pass 0 as machine type when calling KVM_CREATE_VM. The kernel documentation says: On arm64, the physical address size for a VM (IPA Size limit) is limited to 40bits

[PATCH v9] xen/pt: reserve PCI slot 2 for Intel igd-passthru

Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, as noted in docs/igd-assign.txt in the Qemu source code. Currently, when the xl toolstack is used to configure a Xen HVM guest with Intel IGD passthrough to the guest with the Qemu upstream device model, a Qemu emulated PCI devi

[PATCH] target/arm: Fix in_debug path in S1_ptw_translate

During the conversion, the test against get_phys_addr_lpae got inverted, meaning that successful translations went to the 'failed' label. Cc: qemu-sta...@nongnu.org Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table walking") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/14

Re: [PATCH] accel/kvm: Specify default IPA size for arm64

On 2023/01/14 14:23, Richard Henderson wrote: On 1/8/23 22:22, Akihiko Odaki wrote: libvirt uses "none" machine type to test KVM availability. Before this change, QEMU used to pass 0 as machine type when calling KVM_CREATE_VM. The kernel documentation says: On arm64, the physical address size

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