On 09/01/23 7:37 pm, Daniel P. Berrangé wrote:
On Mon, Dec 26, 2022 at 05:33:25AM +, Het Gala wrote:
From: Author Het Gala
Existing 'migrate' QAPI design enforces transport mechanism, ip address
of destination interface and corresponding port number in the form
of a unified string 'uri'
On 5/1/23 14:07, Philippe Mathieu-Daudé wrote:
Minor housekeeping while reviewing PCI host bridge models.
Philippe Mathieu-Daudé (8):
hw/pci-host/bonito: Convert to 3-phase reset
hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code
hw/pci-host/bonito: Use 'bonito_pci' for PC
Hi Peter,
On 20/12/22 12:11, Philippe Mathieu-Daudé wrote:
Since commit a0e61807a3 ("qapi: Remove QMP events and commands from
user-mode builds") we don't generate the "qapi-commands-machine.h"
header in a user-emulation-only build.
Move the QMP functions from helper.c (which is always compiled
When sending mail to Kamil's address, it's bouncing with a message
that the mailbox is full. This already happens since summer 2022,
and the last message that Kamil sent to the qemu-devel mailing list
is from November 2021 (as far as I can see), so we unfortunately
have to assume that this e-mail a
On Fri, Jan 13, 2023 at 5:36 AM Jason Wang wrote:
>
> On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote:
> >
> > To restore the device at the destination of a live migration we send the
> > commands through control virtqueue. For a device to read CVQ it must
> > have received the DRIVER_OK stat
On 1/12/23 12:05, Peter Maydell wrote:
On Wed, 11 Jan 2023 at 09:14, Paolo Bonzini wrote:
On 1/10/23 11:53, Peter Maydell wrote:
On Tue, 10 Jan 2023 at 09:33, Paolo Bonzini wrote:
A handful of header files in QEMU are wrapped with extern "C" blocks.
These are not necessary: there are C++ sou
On 1/10/23 18:39, Alex Bennée wrote:
From: Marc-André Lureau
Let's try to reduce our Perl usage during config/build-time.
Note: this patch might be dropped if "configure: remove
backwards-compatibility code" is merged earlier.
It can be dropped now.
Paolo
Signed-off-by: Marc-André Lureau
On 4/1/23 14:39, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (6):
hw/pci/pci_host: Trace config accesses on unexisting functions
hw/mips/malta: Split FPGA LEDs/ASCII display updates
hw/mips/malta: Trace FPGA LEDs/ASCII display updates
hw/mips/gt64xxx_pci: Accumulate address
Hi Kevin,
Thank you for your patience and explanations. I learned a lot from our
discussions and thank you again for your help.
Regards
Zhiyong
On 1/12/23 7:47 PM, Kevin Wolf wrote:
Am 11.01.2023 um 17:21 hat Zhiyong Ye geschrieben:
Hi Kevin,
Can I ask again how base.img + diff.qcow2 can
On 16/12/22 23:55, Philippe Mathieu-Daudé wrote:
If we get custom to see MAINTAINERS changes first,
we might catch missing MAINTAINERS updates easier.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/git.orderfile | 2 ++
1 file changed, 2 insertions(+)
I'm queuing this patch via mips-nex
On Fri, Jan 13, 2023 at 5:39 AM Jason Wang wrote:
>
> On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote:
> >
> > This is needed for qemu to know it can suspend the device to retrieve
> > its status and enable SVQ with it, so all the process is transparent to
> > the guest.
> >
> > Signed-off-by
On Fri, Jan 13, 2023 at 01:37:26PM +0530, Het Gala wrote:
>
> On 09/01/23 7:37 pm, Daniel P. Berrangé wrote:
> > On Mon, Dec 26, 2022 at 05:33:25AM +, Het Gala wrote:
> > > From: Author Het Gala
> > >
> > > Existing 'migrate' QAPI design enforces transport mechanism, ip address
> > > of dest
Hi Bernhard,
On 9/1/23 18:23, Bernhard Beschow wrote:
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges and is an extended version of [1]. The motivation is to share as much
code as possible and to bring both device models to feature parity such that
perhaps PIIX4
On Thu, Jan 12, 2023 at 11:36:22PM -0800, Christoph Hellwig wrote:
> Hi all,
>
> qemu 7.2.0 fails to boot my usual test setup using -kernel (see
> the actual script below). I've bisected this down to:
>
> commit ffe2d2382e5f1aae1abc4081af407905ef380311
> Author: Jason A. Donenfeld
> Date: Wed
Hi Michael,
On 10/1/23 10:53, Thomas Huth wrote:
The basic idea of this patch set is to change hw/rtc/mc146818rtc.c into
target independent code so that the file only has to be compiled once
instead of multiple times (and that it can be used in a qemu-system-all
binary once we get there).
Tho
+CC qemu pci maintainers
Michael, Marcel,
Do you have any comments on this thread? As you can see one solution is
to simply deassert prior to asserting, the other is to reintroduce a
pci_irq_pulse(). Both seem to solve the issue.
On Jan 12 14:10, Klaus Jensen wrote:
> Hi all (linux-nvme, qemu-de
On Fri, Jan 13, 2023 at 5:55 AM Jason Wang wrote:
>
> On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote:
> >
> > This allows net to restart the device backend to configure SVQ on it.
> >
> > Ideally, these changes should not be net specific. However, the vdpa net
> > backend is the one with eno
On Fri, Jan 13, 2023 at 4:39 AM Jason Wang wrote:
>
> On Fri, Jan 13, 2023 at 11:25 AM Zhu, Lingshan wrote:
> >
> >
> >
> > On 1/13/2023 10:31 AM, Jason Wang wrote:
> > > On Fri, Jan 13, 2023 at 1:27 AM Eugenio Pérez wrote:
> > >> Spuriously kick the destination device's queue so it knows in cas
I'm looking at interrupt remapping (because I need to hook into the
translation somehow to add PIRQ support for Xen which translates guest
MSIs directly to KVM_IRQ_ROUTING_XEN_EVTCHN).
Am I right in understanding that it doesn't report faults on interrupts
which can't be translated? It attempts to
On Thu, 12 Jan 2023 17:46:27 -0500
Gregory Price wrote:
> On Thu, Jan 12, 2023 at 05:21:30PM +, Jonathan Cameron wrote:
> > On Thu, 12 Jan 2023 10:39:17 -0500
> > Gregory Price wrote:
> >
> > > On Wed, Jan 11, 2023 at 02:24:32PM +, Jonathan Cameron via wrote:
> > > > Gregory's patch
On 12/01/2023 17.24, Rot127 wrote:
I currently work on a new updater for architecture modules in Capstone.
The current update process has the problem that it is a lot of manual work.
Syncing the information from LLVM to Capstone requires a one to translate a
lot of C++ to C code and fix a ton o
On Thu, 12 Jan 2023 23:14:26 -0500
Chuck Zmudzinski wrote:
> On 1/12/23 6:03 PM, Michael S. Tsirkin wrote:
> > On Thu, Jan 12, 2023 at 10:55:25PM +, Bernhard Beschow wrote:
> >> I think the change Michael suggests is very minimalistic: Move the if
> >> condition around xen_igd_reserve_slot(
On Fri, 13 Jan 2023 00:27:55 +
Fan Ni wrote:
> For passthrough decoder (a decoder hosted by a cxl component with only
> one downstream port), its cache_mem_registers field COMMITTED
> (see spec 2.0 8.2.5.12 - CXL HDM Decoder Capability Structure) will not
> be set by the current Linux CXL dri
On Fri, Jan 13, 2023 at 09:19:00AM +0100, Eugenio Perez Martin wrote:
On Fri, Jan 13, 2023 at 5:36 AM Jason Wang wrote:
On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote:
>
> To restore the device at the destination of a live migration we send the
> commands through control virtqueue. For a
On Fri, Jan 13, 2023 at 10:51 AM Stefano Garzarella wrote:
>
> On Fri, Jan 13, 2023 at 09:19:00AM +0100, Eugenio Perez Martin wrote:
> >On Fri, Jan 13, 2023 at 5:36 AM Jason Wang wrote:
> >>
> >> On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote:
> >> >
> >> > To restore the device at the dest
On 9/1/23 18:23, Bernhard Beschow wrote:
pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and
pci_map_irq_fn to a PCI bus. This coupling gets in the way when the
pci_map_irq_fn is board-specific while the pci_set_irq_fn is device-
specific.
For example, both of QEMU's PIIX south
Hi Bin!
On 1/12/23 22:28, Bin Meng wrote:
Hi Daniel,
On Wed, Jan 11, 2023 at 1:03 PM Alistair Francis wrote:
On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza
wrote:
Hi,
I found this bug when testing my avocado changes in riscv-to-apply.next.
The sifive_u board, both 32 and 64 bits,
On 1/13/23 04:16, Philippe Mathieu-Daudé wrote:
On 12/1/23 01:34, Alistair Francis wrote:
On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza
wrote:
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
-
On Fri, Jan 13, 2023 at 6:23 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/13/23 04:16, Philippe Mathieu-Daudé wrote:
> > On 12/1/23 01:34, Alistair Francis wrote:
> >> On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza
> >> wrote:
> >>>
> >>> The microchip_icicle_kit, sifive_u, spike and vi
This introduces new properties to allow the user to set the satp mode,
see patch 1 for full syntax.
v5:
- Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
suggested by Andrew
- Split the v4 patch into 2 patches as suggested by Andrew
- Lot of other minor corrections, from Andrew
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
d
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
On Fri, Jan 13, 2023 at 11:03:17AM +0100, Eugenio Perez Martin wrote:
On Fri, Jan 13, 2023 at 10:51 AM Stefano Garzarella wrote:
On Fri, Jan 13, 2023 at 09:19:00AM +0100, Eugenio Perez Martin wrote:
>On Fri, Jan 13, 2023 at 5:36 AM Jason Wang wrote:
>>
>> On Fri, Jan 13, 2023 at 1:25 AM Eugen
Am 13.01.2023 um 08:30 hat Philippe Mathieu-Daudé geschrieben:
> On 12/1/23 20:14, Kevin Wolf wrote:
> > In order to write the bitmap table to the image file, it is converted to
> > big endian. If the write fails, it is passed to clear_bitmap_table() to
> > free all of the clusters it had allocated
On 1/13/23 07:30, Bin Meng wrote:
On Fri, Jan 13, 2023 at 6:23 PM Daniel Henrique Barboza
wrote:
On 1/13/23 04:16, Philippe Mathieu-Daudé wrote:
On 12/1/23 01:34, Alistair Francis wrote:
On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza
wrote:
The microchip_icicle_kit, sifive_u, s
On 14/12/22 11:47, Thomas Huth wrote:
On 16/02/2022 16.42, Alexander von Gluck IV wrote:
---
tests/vm/haiku.x86_64 | 8
1 file changed, 4 insertions(+), 4 deletions(-)
[...]
@@ -48,8 +48,8 @@ class HaikuVM(basevm.BaseVM):
name = "haiku"
arch = "x86_64"
- link =
"htt
On Fri, 2022-12-30 at 08:25 +, scalingtree wrote:
> Hi lists,
>
> (Re-sending as plain text.)
>
> We are in the process of using an external tool (CRIU) to
> checkpoint/restore a KVM-enabled virtual machine. Initially we target
> the hypervisor kvmtool but the extension, if done well, should
Am 13.01.2023 um 08:30 hat Markus Armbruster geschrieben:
> Drive-by comment...
>
> Kevin Wolf writes:
>
> > This series addresses the problem described in these bug reports:
> > https://gitlab.com/qemu-project/qemu/-/issues/1330
> > https://bugzilla.redhat.com/show_bug.cgi?id=2147617
> >
> > qc
On Fri, Jan 13, 2023 at 09:08:38AM +, David Woodhouse wrote:
> I'm looking at interrupt remapping (because I need to hook into the
> translation somehow to add PIRQ support for Xen which translates guest
> MSIs directly to KVM_IRQ_ROUTING_XEN_EVTCHN).
>
> Am I right in understanding that it do
Am 12.01.2023 um 21:28 hat Ilya Dryomov geschrieben:
> On Thu, Dec 9, 2021 at 10:34 AM Or Ozeri wrote:
> >
> > The blk_get_max_hw_transfer API was recently added in 6.1.0.
> > It allows querying an underlying block device its max transfer capability.
> > This commit changes virtio-blk to use this.
On Fri, 13 Jan 2023 at 08:55, Klaus Jensen wrote:
>
> +CC qemu pci maintainers
>
> Michael, Marcel,
>
> Do you have any comments on this thread? As you can see one solution is
> to simply deassert prior to asserting, the other is to reintroduce a
> pci_irq_pulse(). Both seem to solve the issue.
B
On Jan 13 12:32, Peter Maydell wrote:
> On Fri, 13 Jan 2023 at 08:55, Klaus Jensen wrote:
> >
> > +CC qemu pci maintainers
> >
> > Michael, Marcel,
> >
> > Do you have any comments on this thread? As you can see one solution is
> > to simply deassert prior to asserting, the other is to reintroduce
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
---
target/tricore/tran
Hi,
On Mon, Jan 09, 2023 at 10:11:19PM +0100, Eric Auger wrote:
> > Jean, do you have any idea about how to fix that? Do you think we have a
> > trouble in the acpi/viot setup or virtio-iommu probe sequence. It looks
> > like virtio probe and attach commands are called too early, before the
> > bu
On Fri, 13 Jan 2023 at 12:37, Klaus Jensen wrote:
> There are a fair amount of uses of pci_irq_pulse() still left in the
> tree.
Are there? I feel like I'm missing something here:
$ git grep pci_irq_pulse
include/hw/pci/pci.h:static inline void pci_irq_pulse(PCIDevice *pci_dev)
$
...looks at fir
On Jan 13 12:42, Peter Maydell wrote:
> On Fri, 13 Jan 2023 at 12:37, Klaus Jensen wrote:
> > There are a fair amount of uses of pci_irq_pulse() still left in the
> > tree.
>
> Are there? I feel like I'm missing something here:
> $ git grep pci_irq_pulse
> include/hw/pci/pci.h:static inline void
On Thu, 1 Dec 2022 at 14:30, ~axelheider wrote:
>
> From: Axel Heider
>
> The first UART always always exists. If the security extensions are
> enabled, the second UART also always exists. Otherwise, it only exists
> if a backend is configured explicitly via '-serial ', where
> 'null' creates a d
On 12.01.23 19:36, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
On 12.01.23 17:58, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
Let's move more code into vmstate_save(), reducing code duplication and
preparing for reuse of vmstate_s
On 12.01.23 23:06, Peter Xu wrote:
On Thu, Jan 12, 2023 at 06:40:00PM +, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
On 12.01.23 18:43, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
... and store it in the migration state. This
On 13.01.23 14:01, David Hildenbrand wrote:
On 12.01.23 23:06, Peter Xu wrote:
On Thu, Jan 12, 2023 at 06:40:00PM +, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
On 12.01.23 18:43, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType for
virtio-net so for now strip virtio-net header to convert the output to
Ethernet.
Signed-o
On Thu, 5 Jan 2023 at 22:12, Evgeny Iakovlev
wrote:
>
> The architecture does not define any functionality for the CLAIM tag bits.
> So we will just keep the raw bits, as per spec.
>
> Helps Hyper-V boot on aarch64-tcg because it context-switches DBGCLAIM
> on EL2 entry/exit.
>
> Signed-off-by: Ev
On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev
wrote:
>
> Qemu doesn't implement Debug Communication Channel, however when running
> Microsoft Hyper-V in software-emulated ARM64 as a guest, it tries to
> access some of the DCM registers during an EL2 context switch.
I've occasionally thought about
On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev
wrote:
>
> ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
> to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
> uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
> write, an
On 13/1/23 12:05, Philippe Mathieu-Daudé wrote:
On 14/12/22 11:47, Thomas Huth wrote:
On 16/02/2022 16.42, Alexander von Gluck IV wrote:
---
tests/vm/haiku.x86_64 | 8
1 file changed, 4 insertions(+), 4 deletions(-)
[...]
@@ -48,8 +48,8 @@ class HaikuVM(basevm.BaseVM):
name
On Fri, 13 Jan 2023, Howard Spoelstra wrote:
On Fri, Jan 13, 2023 at 12:53 AM BALATON Zoltan wrote:
The names also show what we intend to
emulate even though the emulation may not be complete or have bugs (this
is also true for other machines in QEMU where a lot of them are not fully
emulated,
On Mon, 9 Jan 2023 at 14:19, Philippe Mathieu-Daudé wrote:
>
> On 9/1/23 14:33, BALATON Zoltan wrote:
> > On Mon, 9 Jan 2023, Philippe Mathieu-Daudé wrote:
> >> Use the same property name than the TYPE_PFLASH_CFI01 model.
> >
> > Nothing uses it? Can this break command lines and if so do we need
>
This small series basically fix an outdated hexagon slot rule for
instruction hintjr and makes the decode machinery more resilient against
any possible outdated slot constraints in the future.
Matheus Tavares Bernardino (2):
Hexagon (iclass): update J4_hintjumpr slot constraints
Hexagon (decod
Each slot in a packet can be assigned to at most one instruction.
Although the assembler generally ought to enforce this rule, we better
be safe than sorry and also do some check to properly throw an "invalid
packet" exception on wrong slot assignments.
This should also make it easier to debug pos
The main reason to do this is to document our O_BINARY implementation
decision somewhere. However I've also moved some of the implementation
details out of qemu-options and added links between the two. As a
bonus I've highlighted the scary warnings about host access with the
appropriate RST tags.
The Hexagon PRM says that "The assembler automatically encodes
instructions in the packet in the proper order. In the binary encoding
of a packet, the instructions must be ordered from Slot 3 down to
Slot 0."
Prior to the architecture version v73, the slot constraints from
instruction "hintjr" onl
Make it easier to navigate the documentation.
Signed-off-by: Alex Bennée
---
docs/about/index.rst | 16
docs/system/index.rst | 2 ++
docs/tools/index.rst | 2 ++
docs/user/index.rst | 2 ++
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/docs/about/index.
On Mon, 9 Jan 2023 at 23:43, Bernhard Beschow wrote:
>
>
>
> Am 9. Januar 2023 12:08:16 UTC schrieb "Philippe Mathieu-Daudé"
> :
> >The point of a getter() function is to not expose the structure
> >internal fields. Otherwise callers could simply access the
> >PFlashCFI01::mem field.
"modern" QO
On 13/1/23 14:08, Akihiko Odaki wrote:
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType for
virtio-net so for now strip virtio-net header to
Drop the frankly misleading quickstart section for a more rounded
introduction section. This new section gives an overview of the
accelerators and high level introduction to some of the key features
of the emulator. We also expand on a general form for a QEMU command
line with a hopefully not too s
I've split this off from my bigger branch for hopefully fast review
turnaround. This also includes the new semihsoting documentation and
takes into account feedback from Peter on IRC.
Let me know what you think.
Alex Bennée (4):
docs: add hotlinks to about preface text
docs: add a new section
This affects both system and user mode emulation so we should probably
list it up front.
Signed-off-by: Alex Bennée
---
docs/about/emulation.rst | 103 ++
docs/about/index.rst | 1 +
docs/devel/tcg-plugins.rst| 2 +
docs/system/arm/emulation.
On Thu, 5 Jan 2023, BALATON Zoltan wrote:
Hello,
I got reports from several users trying to run AmigaOS4 on sam460ex on Apple
silicon Macs that they get missing graphics that I can't reproduce on x86_64.
With help from the users who get the problem we've narrowed it down to the
following:
I
[...]
It might be OK if you just change the declaration; I mean '1' is pretty
close to true? (I think...)
Anyway, at least make the new one a bool.
Agreed bool is better. Can we rename it to something like "early_setup"?
"immutable" isn't clear on its most important attribute (on when it'll b
On Mon, 9 Jan 2023 at 12:31, Philippe Mathieu-Daudé wrote:
>
> pflash_cfi02_register() hides an implicit sysbus mapping of
> MMIO region #0. This is not practical in a heterogeneous world
> where multiple cores use different address spaces. In order to
> remove pflash_cfi02_register() from the pfl
On Mon, 9 Jan 2023 at 12:56, Philippe Mathieu-Daudé wrote:
>
> pflash_cfi02_register() hides an implicit sysbus mapping of
> MMIO region #0. This is not practical in a heterogeneous world
> where multiple cores use different address spaces. In order to
> remove pflash_cfi02_register() from the pfl
On Mon, 9 Jan 2023 at 12:20, Philippe Mathieu-Daudé wrote:
>
> pflash_cfi02_register() hides an implicit sysbus mapping of
> MMIO region #0. This is not practical in a heterogeneous world
> where multiple cores use different address spaces. In order to
> remove pflash_cfi02_register() from the pfl
Philippe Mathieu-Daudé writes:
> [resend fixing my last name typography...]
>
> All series reviewed, can patches be picked by corresponding
> maintainers?
>
> The "qapi-commands-machine.h" header is not generated in user-only
> emulation. This series removes its use in user-emu code by moving
> t
On 12.01.23 20:44, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
The bitmap and the size are immutable while migration is active: see
virtio_mem_is_busy(). We can migrate this information early, before
migrating any actual RAM content. Further, all information we ne
On Mon, 9 Jan 2023 at 13:13, Philippe Mathieu-Daudé wrote:
>
> pflash_cfi01_register() hides an implicit sysbus mapping of
> MMIO region #0. This is not practical in a heterogeneous world
> where multiple cores use different address spaces. In order to
> remove pflash_cfi01_register() from the pfl
This series makes the necessary changes to allow the use of
--disable-tcg for arm.
Based on Richard's "target/arm: Introduce aarch64_set_svcr":
https://lore.kernel.org/r/20230112004322.161330-1-richard.hender...@linaro.org
branch here: https://github.com/farosas/qemu/tree/arm-disable-tcg
Since v
This is in preparation for moving debug_helper.c into a TCG-specific
directory.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 6 --
target/arm/machine.c | 7 +--
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5f63316dbf.
The hflags are used only for TCG code, so introduce a new file
hflags.c to keep that code.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
If I move assert_hflags_rebuild_correctly along with
cpu_get_tb_cpu_state, rebuild_hflags_internal would have to be
exposed. This used to wor
Signed-off-by: Fabiano Rosas
---
tests/qtest/arm-cpu-features.c | 24
1 file changed, 24 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4be1415823..9a052e41fc 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line. Most other architectures define a default value in QEMU for
these options, but arm does not.
Add these options to the test class in case the test is being ex
We will soon enable the build without TCG, which does not support many
machines, so only run the bcm2835-dma-test when the corresponding
machine is present.
Signed-off-by: Fabiano Rosas
---
tests/qtest/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qtes
The tests under tests/tcg depend on the TCG accelerator. Do not build
them if --disable-tcg was given in the configure line.
Test against CONFIG_TCG='' instead of CONFIG_TCG=y to account for
CONFIG_TCG=m.
sample output:
$ make check-tcg
GIT ui/keycodemapdb meson dtc
SKIPPED x86_64-softmm
From: Philippe Mathieu-Daudé
NPCM7XX models have been commited after the conversion from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Manually convert them.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-11-phi...@li
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect ot
From: Philippe Mathieu-Daudé
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:
hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a
definition
DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/helper.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 562da41e73..aa94db9917 1006
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Add definitions for RAM / Flash / Flash blocksize.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-4-phi...@linaro.org
Signed-off-by: Peter Maydell
--
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Add the FLASH_SECTOR_SIZE definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-12-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/z2
From: Philippe Mathieu-Daudé
The structure is named SECUREECState. Rename the type accordingly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-12-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/misc/sbsa_ec.c | 13 +++--
1
From: Philippe Mathieu-Daudé
Add a comment describing the Connex uses a Numonyx RC28F128J3F75
flash, and the Verdex uses a Micron RC28F256P30TFA.
Correct the Verdex machine description (we model the 'Pro' board).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id:
From: Philippe Mathieu-Daudé
The typedef and definitions are generated by the OBJECT_DECLARE_TYPE
macro in "hw/arm/bcm2836.h":
20#define TYPE_BCM283X "bcm283x"
21OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when
From: Philippe Mathieu-Daudé
To avoid forward-declaring PXA2xxI2CState, declare
PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-2-phi...@linaro.org
Signed-off-by: Peter Maydell
---
This allows the test to be skipped when TCG is not present in the QEMU
binary.
Signed-off-by: Fabiano Rosas
---
tests/avocado/boot_linux_console.py | 1 +
tests/avocado/reverse_debugging.py | 8
2 files changed, 9 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests
From: Felipe Balbi
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
Memory) at a different base address. Correctly describe the memory
layout to give existing FW images a chance to run unmodified.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: F
From: Philippe Mathieu-Daudé
Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x:
QOMified") the pflash_cfi01_register() function does not fail.
This call was later converted with a script to use &error_fatal,
still unable to fail. Remove the unreachable code.
Signed-off-by: Philippe Ma
On 13/01/2023 15.04, Fabiano Rosas wrote:
Signed-off-by: Fabiano Rosas
---
tests/qtest/arm-cpu-features.c | 24
1 file changed, 24 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4be1415823..9a052e41fc 100644
--- a/tes
From: Philippe Mathieu-Daudé
Upon introduction in commit b8433303fb ("Set proper device-width
for vexpress flash"), ve_pflash_cfi01_register() was calling
qdev_init_nofail() which can not fail. This call was later
converted with a script to use &error_fatal, still unable to
fail. Remove the unrea
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-4-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/omap1.c| 115 ++
hw/arm/omap2.c| 40 +
When TCG is disabled this part of the code should not be reachable, so
wrap it with an ifdef for now.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/ptw.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4bda0590c7..2a
The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the
cortex-a57 as default cpu for KVM.
Signed-off-by: Fabiano Rosas
---
hw/arm/virt.c | 6 ++
tests/qtest/arm-cpu-features.c | 3 +--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c
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