On 5/1/23 16:44, Bernhard Beschow wrote:
Bernhard Beschow (2):
hw/pci-host/bonito: Inline pci_register_root_bus()
hw/pci-host/bonito: Map PCI IRQs in board code
include/hw/pci-host/bonito.h | 2 ++
hw/mips/fuloong2e.c | 22 ++
hw/pci-host/bonito.c
On 5/1/23 17:02, BALATON Zoltan wrote:
On Thu, 5 Jan 2023, Philippe Mathieu-Daudé wrote:
No need to document magic values when the definition names
from "standard-headers/linux/pci_regs.h" are self-explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/grackle.c | 2 +-
hw/pci-host/r
On Thu, Jan 05, 2023 at 05:29:54PM +0100, Philippe Mathieu-Daudé wrote:
> On 5/1/23 17:01, Laszlo Ersek wrote:
> > On 1/5/23 10:56, Michael S. Tsirkin wrote:
> > > On Thu, Jan 05, 2023 at 04:17:06AM -0500, Michael S. Tsirkin wrote:
> > > > From: Laszlo Ersek
> > >
> > > I noticed v2 is forthcomin
Am 5. Januar 2023 16:02:48 UTC schrieb BALATON Zoltan :
>On Thu, 5 Jan 2023, Philippe Mathieu-Daudé wrote:
>> No need to document magic values when the definition names
>> from "standard-headers/linux/pci_regs.h" are self-explicit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/pci-h
On Thu, Jan 05, 2023 at 03:40:44PM +0100, Philippe Mathieu-Daudé wrote:
> This argument was added 9 years ago in commit 83d08f2673
add ("commit subject")
> and has never been used since, so remote it.
remote -> remove
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/pc.c | 2
On Thu, Jan 05, 2023 at 03:31:57PM +0100, Bernhard Beschow wrote:
> This series consolidates the implementations of the PIIX3 and PIIX4 south
> bridges and is an extended version of [1]. The motivation is to share as much
> code as possible and to bring both device models to feature parity such tha
I was motivated to sort this out while working on my register API
which is target agnostic but ran into the weeds when trying to link up
with the gdbstub. This was due to us building gdbstub for every single
target we support due to a few ABI sensitive bits that require CPU
specific information. Th
This aids subsystems (like gdbstub) that want to trigger a flush
without pulling target specific headers.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- actually include the header and rename to tb-flush.h
- better kerneldoc style comment for the function
---
include/ex
From: Philippe Mathieu-Daudé
Prototypes using gdb_syscall_complete_cb() or gdb_?et_reg_cb()
don't depend on "cpu.h", thus are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221214143659.62133-1-phi...@linaro.org>
Signed-off-by: Alex Ben
In preparation for moving user/softmmu specific bits from the main
gdbstub file we need to separate the connection details into a
user/softmmu state. These will eventually be defined in their own
files.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 91 +++
From: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/timer/imx_epit.h | 2 ++
hw/timer/imx_epit.c | 12 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
index e2cb9
This is mostly code motion but a number of things needed to be done
for this minimal patch set:
- move shared structures to internals.h
- splitting some functions into user and softmmu versions
- fixing a few casting issues to keep softmmu common
More CONFIG_USER_ONLY stuff will be handled
These will be needed from multiple places in the code. They are
declared as inline so move to the header and fix up to modern coding
style.
The only other place that messes with hex stuff at the moment is the
URI handling in utils but that would be more code churn so leave for
now.
Signed-off-by:
From: Philippe Mathieu-Daudé
The pointed MouseTransformInfo structure is accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221220142520.24094-2-phi...@linaro.org
Signed-off-by: Peter Maydell
---
include/hw/input/tsc2xxx.h | 4 ++--
hw/inpu
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 15 +++
gdbstub/gdbstub.c | 10 ++
From: Tobias Röhmel
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-
From: Fabiano Rosas
Fix this:
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Message-id: 20221213190537.511-4-faro...@suse.de
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 67 +++
From: Axel Heider
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.
Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.
Signed-off-
From: Philippe Mathieu-Daudé
This function is not used anywhere outside this file,
so we can make the function "static void".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Message-id: 20221216214924.4711-2-phi...@linaro.org
Signed-off-by: Peter M
In both user and softmmu cases we are just replying with a constant.
If the linker is paying attention it may even be able to sort optimise
the call.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 4 +++-
gdbstub/gdbstub.c | 15 ++-
gdbstub/softmmu.c | 5 +
gdbstub/us
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub
When I started splitting gdbstub apart I was a little too boilerplate
with my file headers. Fix up to carry over Fabrice's copyright and the
LGPL license header.
Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops)
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 13 ++---
gdbstub/softmmu.c | 5 +
gdbstub/user.c | 5 +
4 files changed, 13 insertions(+), 11 dele
This is a hangover from the original code. addr is misleading as it is
only a really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 17 ++---
1 file changed, 10 insertion
In get_phys_addr_twostage() we set the lg_page_size of the result to
the maximum of the stage 1 and stage 2 page sizes. This works for
the case where we do want to create a TLB entry, because we know the
common TLB code only creates entries of the TARGET_PAGE_SIZE and
asking for a size larger than
On Thu, 5 Jan 2023 at 16:46, Cédric Le Goater wrote:
>
> On 1/5/23 16:33, Peter Maydell wrote:
> > On Wed, 21 Dec 2022 at 18:32, Stephen Longfield
> > wrote:
> >>
> >> Size is used at lines 1088/1188 for the loop, which reads the last 4
> >> bytes from the crc_ptr so it does need to get increase
From: Tobias Röhmel
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Message-id: 20221206102504.165775-3-to
From: Philippe Mathieu-Daudé
Silent when compiling with -Wextra:
../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer
[-Wmissing-field-initializers]
{ NULL }
^
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20221220142520.24094-4-phi...@linaro.org
Rev
Now we have removed any target specific bits from the core gdbstub
code we only need to build it twice. We have to jump a few meson hoops
to manually define the CONFIG_USER_ONLY symbol but it seems to work.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 3 +--
gdbstub/user-target.c | 2
From: Fabiano Rosas
Fix these:
WARNING: Block comments use a leading /* on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Messa
The process was pretty similar to the softmmu move except we take the
time to split stuff between user.c and user-target.c to avoid as much
target specific compilation as possible. We also start to make use of
our shiny new header scheme so the user-only helpers can be included
without the rest of
Use something more specific to avoid name clashes.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gdbstub/internals.h b/gdbstub/internals.h
index eabb0341d1..b444f24ef5 100644
--- a/gdbs
From: Axel Heider
Fix typos, add background information
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/timer/imx_epit.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit
The two implementations are different enough to encourage having a
specialisation and we can move some of the softmmu only stuff out of
gdbstub.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 19
gdbstub/gdbstub.c | 73 +++--
gdbstub/s
This is needed for handling vcont packets as the way of calculating
max cpus vhanges between user and softmmu mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 11 +--
gdbstub/softmmu.c | 9 +
gdbstub/user.c | 17 +
4 f
From: Jean-Christophe Dubois
IRQs were not associated to the various GPIO devices inside i.MX7D.
This patch brings the i.MX7D on par with i.MX6.
Signed-off-by: Jean-Christophe Dubois
Message-id: 20221226101418.415170-1-...@tribudubois.net
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221220142520.24094-3-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/nseries.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/ar
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Message-id: 20221206102504.165775-8-tobias.roeh...@rwth-aachen.de
Signed-off-by: Peter Maydell
---
target/arm/cpu_tcg.c | 42 ++
On Mon, 2 Jan 2023 at 11:31, David Hildenbrand wrote:
>
> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
>
> Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into
> staging (2022-12-21 18:08:09 +)
>
> are available in the Git repository at:
>
>
Our GDB syscall support is the last chunk of code that needs target
specific support so move it to a new file. We take the opportunity to
move the syscall state into its own singleton instance and add in a
few helpers for the main gdbstub to interact with the module.
I also moved the gdb_exit() de
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
Signed-off-by: Alex Bennée
---
target
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
Reviewed-by: P
From: Fabiano Rosas
Fix the following:
ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('
(the last two still have some occ
From: Zhuojia Shen
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.
Specifically, the following new ID registers/fields are exposed to
u
From: Tobias Röhmel
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Message-id: 20221206102504.165775-7-tobias.roeh...@rwth-aachen.de
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 126 ++-
1 file changed, 104
From: Jean-Christophe Dubois
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/timer/imx_gpt.h | 1 +
hw/arm/fsl-imx6ul.c| 2 +-
hw/misc/imx6ul_ccm.c
From: Claudio Fontana
Remove some unused headers.
Signed-off-by: Claudio Fontana
Acked-by: Richard Henderson
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Signed-off-by: Fabiano Rosas
Message-id: 20221213190537.511-7-faro...@suse.de
[added back some includes that are still needed
From: Axel Heider
- fix #1263 for CR writes
- rework compare time handling
- The compare timer has to run even if CR.OCIEN is not set,
as SR.OCIF must be updated.
- The compare timer fires exactly once when the
compare value is less than the current value, but the
reload values is
(2023-01-04 18:58:33 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230105
for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33
On 5/1/23 17:43, Alex Bennée wrote:
When I started splitting gdbstub apart I was a little too boilerplate
with my file headers. Fix up to carry over Fabrice's copyright and the
LGPL license header.
Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops)
Reviewed-by: Richard Henderson
Si
From: Stephen Longfield
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC computation,
or the crc32 function will access uninitialized memory.
This was
On 5/1/23 17:43, Alex Bennée wrote:
Use something more specific to avoid name clashes.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Message-id: 20221213190537.511-6-faro...@suse.de
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/arm/helper.c b/targe
We will be needing to use these helpers between the user and softmmu
files so declare them in the headers, add a system prefix and remove
static from the implementations.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 25
gdbstub/gdbstub.c | 271 ++--
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect before.
Signed-off-by: Alex Bennée
---
From: Axel Heider
The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/timer/imx_epit.c | 16
1 file changed, 12 insertions(+), 4 d
From: Jean-Christophe Dubois
So far the GPT timers were unable to raise IRQs to the processor.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/fsl-imx7.h | 5 +
hw/arm/fsl-imx7.c | 10 ++
2 files changed, 1
> -Original Message-
> From: Brian Cain
> Sent: Thursday, January 5, 2023 11:10 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org;
> alex.ben...@linaro.org
> Cc: Taylor Simpson ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; Matheus Bernardino (QUIC)
>
> Subjec
[ .. ]
The problem is that QEMU doesn't know about the S390_FEAT_EXTENDED_LENGTH_SCCB
feature when the PV object link is first checked. So #248 CPUs is considered
valid, but when DIAG308_PV_START is called, it fails.
Drat. Is there any chance that the check could be done somewhere later?
s39
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, January 5, 2023 10:24 AM
> To: qemu-devel@nongnu.org; alex.ben...@linaro.org
> Cc: Taylor Simpson ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subje
Am 4. Januar 2023 21:59:37 UTC schrieb BALATON Zoltan :
>We already have machine in a local variable so no need to use
>qdev_get_machine(), also remove now unneded line break.
>
>Signed-off-by: BALATON Zoltan
>---
> hw/ppc/mac_newworld.c | 3 +--
> hw/ppc/mac_oldworld.c | 3 +--
> 2 files changed
From: Axel Heider
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/timer/imx_epit.c | 215
1 file changed, 117 insertions(+), 98 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 39f
> -Original Message-
> From: Alex Bennée
> Sent: Thursday, January 5, 2023 10:43 AM
> To: qemu-devel@nongnu.org; alex.ben...@gmail.com
> Cc: David Hildenbrand ; Sunil Muthuswamy
> ; Aurelien Jarno ;
> Michael Rolnik ; Aleksandar Rikalo
> ; Greg Kurz ; Ilya
> Leoshkevich ; Thomas Huth ;
>
From: Jean-Christophe Dubois
CCM derived clocks will have to be added later.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/imx7_ccm.c | 49 +-
1 file changed, 40 insertions(+), 9 deletions
From: Alex Bennée
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Cc: qemu-sta...@nongnu.org
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config usersp
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
Message-id: 20221206102504.165775-6-tobias.roeh...@rwth-aachen.de
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 6 +
target/arm/cpu.c | 28 +++-
target/arm/helper.c | 302 +++
target/arm/
On 5/1/23 17:43, Alex Bennée wrote:
We will be needing to use these helpers between the user and softmmu
files so declare them in the headers, add a system prefix and remove
"system prefix" -> "'gdb_' prefix"
static from the implementations.
Signed-off-by: Alex Bennée
---
gdbstub/internal
On 5/1/23 17:43, Alex Bennée wrote:
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Yay \o/
From: Axel Heider
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/timer/imx_epit.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7af3a8b10e8..39f47222d05 10064
From: Tobias Röhmel
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 des
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Message-id: 20221213190537.511-5-faro...@suse.de
Signed-off-by: Peter Maydell
---
target/arm/m_helper.c | 16
1 file changed, 16 deletions(-)
diff --git a/target/arm/m_h
From: Philippe Mathieu-Daudé
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:
hw/arm/smmu-common.c:173:33: warning: static function
'smmu_hash_remove_by_asid_iova' is used in an inline function with external
linkage [-Wstatic-in-inline]
On Thu, Jan 05, 2023 at 09:35:54AM +0100, David Hildenbrand wrote:
> On 04.01.23 18:23, Peter Xu wrote:
> > On Thu, Dec 22, 2022 at 12:02:10PM +0100, David Hildenbrand wrote:
> > > Migrating device state before we start iterating is currently impossible.
> > > Introduce and use qemu_savevm_state_st
On Thu, Dec 22, 2022 at 12:02:12PM +0100, David Hildenbrand wrote:
> +bool migration_incoming_postcopy_listening(void)
> +{
> +PostcopyState ps = postcopy_state_get();
> +
> +return ps >= POSTCOPY_INCOMING_LISTENING && ps < POSTCOPY_INCOMING_END;
> +}
This name is misleading, IMHO.
The co
Am 5. Januar 2023 16:39:01 UTC schrieb "Michael S. Tsirkin" :
>On Thu, Jan 05, 2023 at 03:31:57PM +0100, Bernhard Beschow wrote:
>> This series consolidates the implementations of the PIIX3 and PIIX4 south
>> bridges and is an extended version of [1]. The motivation is to share as much
>> code a
On Thu, 5 Jan 2023 at 11:00, Alex Bennée wrote:
>
> Hi Peter,
>
> I discovered that semihosting syscall support got broken and while
> preparing to bisect I ran into a few warts.
>
> Alex Bennée (4):
>semihosting-tests: add timeout support
>Makefile: drop microbit.lds from the sou
On 5/1/23 17:43, Alex Bennée wrote:
This is a hangover from the original code. addr is misleading as it is
only a really a register id. While len will never exceed
"a really"?
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub
On 5/1/23 17:43, Alex Bennée wrote:
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 15 +++
Hi Jean,
Thanks for taking the time to look into this.
On Wed, Jan 04, 2023 at 12:29:10PM +, Jean-Philippe Brucker wrote:
> Hi Mostafa,
>
> On Mon, Dec 19, 2022 at 12:57:20PM +, Mostafa Saleh wrote:
> > GBPA register can be used to globally abort all
> > transactions.
> >
> > Only UPDAT
On 5/1/23 17:43, Alex Bennée wrote:
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect befo
On 1/5/23 17:50, Peter Maydell wrote:
On Thu, 5 Jan 2023 at 16:46, Cédric Le Goater wrote:
On 1/5/23 16:33, Peter Maydell wrote:
On Wed, 21 Dec 2022 at 18:32, Stephen Longfield wrote:
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does nee
On Mon, 2 Jan 2023 at 15:46, Rebecca Cran wrote:
>
> For the SBSA-REF machine start all APs in the powered-off state.
> This reduces host CPU usage until PSCI_CPU_ON is called when the APs
> are needed.
>
> Signed-off-by: Rebecca Cran
> ---
> hw/arm/sbsa-ref.c | 6 ++
> 1 file changed, 6 ins
On 5/1/23 17:43, Alex Bennée wrote:
In both user and softmmu cases we are just replying with a constant.
If the linker is paying attention it may even be able to sort optimise
the call.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 4 +++-
gdbstub/gdbstub.c | 15 ++-
g
No need to document magic values when the definition names
from "standard-headers/linux/pci_regs.h" are self-explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/grackle.c | 2 +-
hw/pci-host/raven.c| 6 +++---
hw/pci-host/uninorth.c | 33 +++--
3 fi
From: Axel Heider
remove unused defines, add needed defines
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/timer/imx_epit.h | 4 ++--
hw/timer/imx_epit.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/includ
We are about to split softmmu and user mode helpers into different
files. To facilitate this we will need to share access to the GDBState
between those files.
To keep building we have to temporarily define CONFIG_USER_ONLY just
before we include internals.h for the user-mode side of things. This
w
The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2
jobs (2023-01-04 18:58:33 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230105
for you to
On 1/5/23 16:33, Peter Maydell wrote:
On Wed, 21 Dec 2022 at 18:32, Stephen Longfield wrote:
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC comput
From: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Reviewed-by: Alessandro Di Federico
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
---
target/hexagon/idef-parser/README.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
* David Hildenbrand (da...@redhat.com) wrote:
> We'll make use of both next in the context of virtio-mem.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Dr. David Alan Gilbert
> ---
> include/migration/vmstate.h | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> dif
This argument was added 9 years ago in commit 83d08f2673
("pc: map PCI address space as catchall region for not mapped
addresses") and has never been used since, so remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/pci-host/i440fx.c | 3 +--
hw/pci-host/q35.c
From: Mukilan Thiyagarajan
This patch fixes the issue originally reported in
this thread:
https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html
The root cause of the issue is a bug in the hexagon specific
logic for saving & restoring context during signal delivery.
The CPU state h
On 5/1/23 17:43, Alex Bennée wrote:
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 13 ++---
gdbstub/softmmu.c | 5 +
gdbstub/user.c | 5 +
From: Mukilan Thiyagarajan
There are two test cases where the inline asm doesn't
have the correct constraints causing them to fail.
In misc.c, the 'result' output needs the early clobber
modifier since the rest of the inputs are read after
assignment to the output register.
In mem_noshuf.c, the
From: Alessandro Di Federico
This patch manually suppresses a warning for an unused variable
(yynerrs) emitted by bison.
This warning has been triggered for the first time by clang 15.
This patch also disables `-Wextra`, which is not usually adopted in
QEMU. However, clang 15 triggers the warni
From: Alessandro Di Federico
Note: `Makefile` relies on modification dates in the source tree to
detect changes to `meson_options.txt`. However, git does not track
those. Therefore, the following was necessary to regenerate
`meson-buildoptions.sh`:
touch meson_options.txt
cd "$BUILD_DIR"
From: Mukilan Thiyagarajan
The patch renames the identifier of the 32bit register
HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED.
This change is to intended to provide some warning that
HEX_REG_P3_0 is an aliased register which has multiple
representations in CPU state and therefore might require
special
From: Marco Liebel
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Marco Liebel
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <20230105102349.2181856-1-quic_mlie...@quicinc.com>
---
target/hexagon/genptr.c
On Wed 04 Jan 2023 12:46:01 PM +01, Thomas Huth wrote:
> "quorum" is required by iotest 312 - if it is not compiled into the
> QEMU binary, the test fails. Thus list "quorum" as required driver
> so that the test gets skipped in case it is not available.
>
> Signed-off-by: Thomas Huth
Reviewed-by
Currently when we encounter a gdb that is old or not built with
multiarch in mind we fail rather messily. Try and improve the
situation by probing ahead of time and setting
HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip
and give a more meaningful message if we don't run the
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