The following changes since commit 5204b499a6cae4dfd9fe762d5e6e82224892383b:
mailmap: Fix Stefan Weil author email (2022-12-13 15:56:57 -0500)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221215
for you to fetch changes up to
From: Xiaojuan Yang
Add cfi01 pflash device for LoongArch virt machine
Signed-off-by: Xiaojuan Yang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221130100647.398565-1-yangxiaoj...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig| 1 +
hw/loongarch/acpi-build.c |
在 2022/12/15 下午3:29, Philippe Mathieu-Daudé 写道:
Hi,
On 2/12/22 11:25, Song Gao wrote:
The following changes since commit
c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500)
are available in the Git repository at:
https://gitlab.com/gao
On 12/15/22 08:58, Philippe Mathieu-Daudé wrote:
On 15/12/22 08:27, Helge Deller wrote:
msync() uses the flags MS_ASYNC, MS_INVALIDATE and MS_SYNC, which differ
between platforms, specifcally on alpha and hppa.
Add a target to host translation for those and wire up a nicer strace
output.
This
在 2022年12月15日 15:40, Philippe Mathieu-Daudé 写道:
On 15/12/22 07:50, Tianrui Zhao wrote:
This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.
Signed-off-by: Tianrui Zhao
---
hw/intc/loongarch_pch_msi.c | 22
Signed-off-by: Juan Quintela
Reviewed-by: Leonardo Bras
---
migration/ram.h | 1 +
migration/ram.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/migration/ram.h b/migration/ram.h
index e844966f69..038d52f49f 100644
--- a/migration/ram.h
+++ b/migration/ram.h
@@ -66,6 +66,
We were recalculating it left and right. We plan to change that
values on next patches.
Signed-off-by: Juan Quintela
Reviewed-by: Leonardo Bras
---
migration/multifd.h | 4
migration/multifd.c | 7 ---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/migration/multifd.h
From: Peter Xu
Any call to ram_find_and_save_block() needs to take the bitmap mutex. We
used to not take it for most of ram_save_complete() because we thought
we're the only one left using the bitmap, but it's not true after the
preempt full patchset applied, since the return path can be taking
From: Peter Xu
The 2nd check on RAM_SAVE_FLAG_CONTINUE is a bit redundant. Use a boolean
to be clearer.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
migration/ram.c | 5 +++--
1 file changed, 3 insertions(+), 2 dele
From: Peter Xu
Removing referencing to RAMState.f in compress_page_with_multi_thread() and
flush_compressed_data().
Compression code by default isn't compatible with having >1 channels (or it
won't currently know which channel to flush the compressed data), so to
make it simple we always flush o
The following changes since commit 5204b499a6cae4dfd9fe762d5e6e82224892383b:
mailmap: Fix Stefan Weil author email (2022-12-13 15:56:57 -0500)
are available in the Git repository at:
https://gitlab.com/juan.quintela/qemu.git tags/next-8.0-pull-request
for you to fetch changes up to 7f401b80
From: Peter Xu
Introduce pss_channel for PageSearchStatus, define it as "the migration
channel to be used to transfer this host page".
We used to have rs->f, which is a mirror to MigrationState.to_dst_file.
After postcopy preempt initial version, rs->f can be dynamically changed
depending on wh
From: Peter Xu
The major change is to replace "!save_page_use_compression()" with
"xbzrle_enabled" to make it clear.
Reasonings:
(1) When compression enabled, "!save_page_use_compression()" is exactly the
same as checking "xbzrle_enabled".
(2) When compression disabled, "!save_page_use_com
From: Peter Xu
To prepare for thread-safety on page accountings, at least below counters
need to be accessed only atomically, they are:
ram_counters.transferred
ram_counters.duplicate
ram_counters.normal
ram_counters.postcopy_bytes
There are a lot of other counte
From: Peter Xu
Now with rs->pss we can already cache channels in pss->pss_channels. That
pss_channel contains more infromation than rs->f because it's per-channel.
So rs->f could be replaced by rss->pss[RAM_CHANNEL_PRECOPY].pss_channel,
while rs->f itself is a bit vague now.
Note that vanilla p
From: Peter Xu
Migration code has a lot to do with host pages. Teaching PSS core about
the idea of host page helps a lot and makes the code clean. Meanwhile,
this prepares for the future changes that can leverage the new PSS helpers
that this patch introduces to send host page in another thread
From: Peter Xu
With the new code to send pages in rp-return thread, there's little help to
keep lots of the old code on maintaining the preempt state in migration
thread, because the new way should always be faster..
Then if we'll always send pages in the rp-return thread anyway, we don't
need t
From: Peter Xu
We used to allocate PSS structure on the stack for precopy when sending
pages. Make it static, so as to describe per-channel ram migration status.
Here we declared RAM_CHANNEL_MAX instances, preparing for postcopy to use
it, even though this patch has not yet to start using the 2
We were calling qemu_target_page_size() left and right.
Signed-off-by: Juan Quintela
Reviewed-by: Leonardo Bras
---
migration/multifd.h | 4
migration/multifd-zlib.c | 14 ++
migration/multifd-zstd.c | 12 +---
migration/multifd.c | 18 --
4 f
Am 14.12.2022 um 23:35 hat Peter Maydell geschrieben:
> On Wed, 14 Dec 2022 at 13:45, Kevin Wolf wrote:
> >
> > The following changes since commit 5204b499a6cae4dfd9fe762d5e6e82224892383b:
> >
> > mailmap: Fix Stefan Weil author email (2022-12-13 15:56:57 -0500)
> >
> > are available in the Git
From: Peter Xu
Helper to init PSS structures.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
migration/ram.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/migration/ram.c b/migration/
From: Peter Xu
Don't take the bitmap mutex when sending pages, or when being throttled by
migration_rate_limit() (which is a bit tricky to call it here in ram code,
but seems still helpful).
It prepares for the possibility of concurrently sending pages in >1 threads
using the function ram_save_h
From: Peter Xu
Since we use PageSearchStatus to represent a channel, it makes perfect
sense to keep last_sent_block (aka, leverage RAM_SAVE_FLAG_CONTINUE) to be
per-channel rather than global because each channel can be sending
different pages on ramblocks.
Hence move it from RAMState into PageS
On Wed, Dec 14, 2022 at 04:30:48PM -0500, Peter Xu wrote:
> On Wed, Dec 14, 2022 at 09:14:09AM +, Daniel P. Berrangé wrote:
> > On Tue, Dec 13, 2022 at 04:38:46PM -0500, Peter Xu wrote:
> > > From: "manish.mishra"
> > >
> > > MSG_PEEK reads from the peek of channel, The data is treated as
> >
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: David Edmondson
Reviewed-by: Leonardo Bras
---
migration/ram.h | 2 ++
migration/ram.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/migration/ram.h b/migration/ram.h
index c7af65ac74..e844966
From: Peter Xu
Add the helper to show that postcopy preempt enabled, meanwhile active.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
migration/ram.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff
Hi, Thomas,
Thanks for your reply. I have attempted to follow you suggestions but it always
failed on tagging a GPG-signed tag before submitting the pull request. I have
used GPG 2.2.4 to generate a RSA4096 GPG secret key and pasted the public key
on GitHub successfully.
$ git tag -s pull-requ
From: Peter Xu
With all the facilities ready, send the requested page directly in the
rp-return thread rather than queuing it in the request queue, if and only
if postcopy preempt is enabled. It can achieve so because it uses separate
channel for sending urgent pages. The only shared data is bi
If a memory-backend is configured with mode
HOST_MEM_POLICY_PREFERRED then
host_memory_backend_memory_complete() calls mbind() as:
mbind(..., MPOL_PREFERRED, nodemask, ...);
Here, 'nodemask' is a bitmap of host NUMA nodes and corresponds
to the .host-nodes attribute. Therefore, there can be mul
LLVM 15.0.0 has improved diagnostics for the
'nounused-but-set-variable' warning and now warns when
a variable is modified using pre/post increment/decrement
operators but is otherwise never read.
linux-tests.c has such an unused variable 'wcount' and since
TCG tests are compiled with -Wall -Werro
On 09/12/2022 17.47, Philippe Mathieu-Daudé wrote:
On non-x86_64 host, if KVM is not available we get:
Traceback (most recent call last):
File "tests/vm/basevm.py", line 634, in main
vm = vmcls(args, config=config)
File "tests/vm/basevm.py", line 104, in __init__
mem =
On Wed, 14 Dec 2022 at 19:20, Markus Armbruster wrote:
>
> The following changes since commit ea3a008d2d9ced9c4f93871c823baee237047f93:
>
> Update VERSION for v7.2.0-rc4 (2022-12-06 19:53:34 -0500)
>
> are available in the Git repository at:
>
> https://repo.or.cz/qemu/armbru.git tags/pull-qap
On Thu, 15 Dec 2022 at 09:45, Wang, Wenchao wrote:
>
> Hi, Thomas,
>
> Thanks for your reply. I have attempted to follow you suggestions but it
> always failed on tagging a GPG-signed tag before submitting the pull request.
> I have used GPG 2.2.4 to generate a RSA4096 GPG secret key and pasted
Hi; I see this migration qtest failure on my x86 macos box:
▶ 32/591
ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed:
assertion fail
ed: (!g_str_equal(status, "failed")) ERROR
32/591 qemu:qtest+qtest-aarch64 / qtest-aarch64/migration-test
ERROR 152.
Control VQ is the way net devices use to send changes to the device state, like
the number of active queues or its mac address.
QEMU needs to intercept this queue so it can track these changes and is able to
migrate the device. It can do it from 1576dbb5bbc4 ("vdpa: Add x-svq to
NetdevVhostVDPAOpt
Since we don't know if we will use SVQ at qemu initialization, let's
allocate iova_tree only if needed. To do so, accept it at SVQ start, not
at initialization.
This will avoid to create it if the device does not support SVQ.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio/vhos
The next patches will start control SVQ if possible. However, we don't
know if that will be possible at qemu boot anymore.
Since the moved checks will be already evaluated at net/ to know if it
is ok to shadow CVQ, move them.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio/vhos
Currently iova range is requested once per queue pair in the case of
net. Reduce the number of ioctls asking it once at initialization and
reusing that value for each vhost_vdpa.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 15 ---
net/vhost-vdpa.c | 27 +++
SVQ may run or not in a device depending on runtime conditions (for
example, if the device can move CVQ to its own group or not).
Allocate the SVQ array unconditionally at startup, since its hard to
move this allocation elsewhere.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio
This function used to trust in v->shadow_vqs != NULL to know if it must
start svq or not.
This is not going to be valid anymore, as qemu is going to allocate svq
array unconditionally (but it will only start them conditionally).
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio/v
Isolate control virtqueue in its own group, allowing to intercept control
commands but letting dataplane run totally passthrough to the guest.
Signed-off-by: Eugenio Pérez
---
v9:
* Reuse iova_range fetched from the device at initialization, instead of
fetch it again at vhost_vdpa_net_cvq_start
The next patches will start control SVQ if possible. However, we don't
know if that will be possible at qemu boot anymore.
Delay device file descriptors until we know it at device start. This
will avoid to create them if the device does not support SVQ.
Signed-off-by: Eugenio Pérez
Acked-by: Jas
It will be reused at vdpa device start so let's extract in its own
function.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 260e47486
CVQ can be shadowed two ways:
- Device has x-svq=on parameter (current way)
- The device can isolate CVQ in its own vq group
QEMU needs to check for the second condition dynamically, because CVQ
index is not known before the driver ack the features. Since this is
dynamic, the CVQ isolation could v
The memory listener that thells the device how to convert GPA to qemu's
va is registered against CVQ vhost_vdpa. memory listener translations
are always ASID 0, CVQ ones are ASID 1 if supported.
Let's tell the listener if it needs to register them on iova tree or
not.
Signed-off-by: Eugenio Pérez
So the caller can choose which ASID is destined.
No need to update the batch functions as they will always be called from
memory listener updates at the moment. Memory listener updates will
always update ASID 0, as it's the passthrough ASID.
All vhost devices's ASID are 0 at this moment.
Signed-
By the end of this series CVQ is shadowed as long as the features
support it.
Since we don't know at the beginning of qemu running if this is
supported, move the event notifier handler setting to the start of the
SVQ, instead of the start of qemu run. This will avoid to create them if
the device d
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> Hi; I see this migration qtest failure on my x86 macos box:
>
>
> ▶ 32/591
> ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed:
> assertion fail
> ed: (!g_str_equal(status, "failed")) ERROR
> 32/591 qemu:qtest+qtest-aar
On Thu, 15 Dec 2022 at 11:40, Dr. David Alan Gilbert
wrote:
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > Hi; I see this migration qtest failure on my x86 macos box:
> >
> >
> > ▶ 32/591
> > ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed:
> > assertion fail
The following changes since commit 5204b499a6cae4dfd9fe762d5e6e82224892383b:
mailmap: Fix Stefan Weil author email (2022-12-13 15:56:57 -0500)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to fetch changes up to 347fe9e156a3e00c40ae18029
Introduced by: aba578bdace5303a441f8a37aad781b5cb06f38c
Signed-off-by: Michael Tokarev
---
hw/cxl/cxl-cdat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-cdat.c b/hw/cxl/cxl-cdat.c
index 3653aa56f0..137abd0992 100644
--- a/hw/cxl/cxl-cdat.c
+++ b/hw/cxl/cxl-cdat
Am 13/12/2022 um 09:53 schrieb Kevin Wolf:
> This series converts some IO_CODE() functions to coroutine_fn because
> they access the graph and will need to hold the graph lock in the
> future. IO_CODE() functions can be called from iothreads, so taking the
> graph lock requires the function to r
On 11/9/22 00:13, John Johnson wrote:
Add ability to do async operations during memory transactions
Signed-off-by: Jagannathan Raman
Signed-off-by: Elena Ufimtseva
Signed-off-by: John G Johnson
---
hw/vfio/common.c | 63 +---
hw/vfio/user-protocol.h | 32 ++
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
use of TLB maintenance instructions that operate on the
outer shareable domain:
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
TLBI RVALE1OS, and TLBI RVAALE1OS.
(There
From: Timofey Kutergin
The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
it supports the Privileged Access Never (PAN) feature. Add
a model of this CPU, so you can use a CPU type on the virt
board that models a specific real hardware CPU, rather than
having to use the QEMU-specific
Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a
simple no-behaviour-change conversion.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221109161444.3397405-4-peter.mayd...@linaro.org
---
hw/intc/arm_gic_common.c
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
and IC IALLUIS cache maintenance instructions.
The HCR_EL2.TOCU bit traps all the other cache maintenance
instructions that operate to the point of unification:
AArch64 IC IVAU, IC IALLU, DC CVAU
AArch32 ICIMVAU, ICIALLU, DCCMV
FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
TICAB, TOCU and TID4. These allow the guest to enable trapping of
various EL1 instructions to EL2. In this commit, add the necessary
code to allow the guest to set these bits if the feature is present;
because the bit is always
From: Mihai Carabas
Use the base_memmap to build the SMBIOS 19 table which provides the address
mapping for a Physical Memory Array (from spec [1] chapter 7.20).
This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
("SMBIOS: Build aggregate smbios tables and entry point"
From: Gavin Shan
This introduces variable 'region_base' for the base address of the
specific high memory region. It's the preparatory work to optimize
high memory region address assignment.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia
Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221109161444.3397405-10-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_its_kvm.c | 14 +-
1 file changed, 9 insertions
From: Gavin Shan
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled or enabled when the optimization is applied or not, with
the following
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
TLB maintenance instructions that operate on the inner shareable
domain:
AArch64:
TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
TLBI RVALE1IS, and TLBI RVAALE
From: Thomas Huth
The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
poisoned in common code, so the files that include this header have to
be added to specific_ss and recompiled for each, qemu-system-arm and
qemu-system-aarch64. However, since the kvm headers are only option
From: Gavin Shan
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia H
From: Schspa Shi
We use 32bit value for linux,initrd-[start/end], when we have
loader_start > 4GB, there will be a wrong initrd_start passed
to the kernel, and the kernel will report the following warning.
[0.00] [ cut here ]
[0.00] initrd not fully access
From: Gavin Shan
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
Its counterpart ('region_base') will be introduced in next patch.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia Huck
Reviewed-by: Marc Zyngier
T
Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221109161444.3397405-7-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_kvm.c | 14 +-
1 file changed, 9 insertions(+)
From: Gavin Shan
The 3 high memory regions are usually enabled by default, but they may
be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
This leads to waste in the PA space.
Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
allow users selectively disabl
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
their AArch32 equivalents). This is a subset of the registers
trapped by HCR_EL2.TID2, which includes all of these and also the
CTR_EL0 register.
Our implementation
From: Gavin Shan
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is likely to be disabled b
Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
TYPE_ARM_GIC_KVM subclass to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221109161444.3397405-5-peter.mayd...@linaro.org
---
hw/intc/arm_gic_kvm.c | 14
From: Philippe Mathieu-Daudé
When building with --disable-tcg on Darwin we get:
target/arm/cpu.c:725:16: error: incomplete definition of type 'struct
TCGCPUOps'
cc->tcg_ops->do_interrupt(cs);
~~~^
Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
handler to sysemu
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 15 Dec 2022 at 11:40, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > Hi; I see this migration qtest failure on my x86 macos box:
> > >
> > >
> > > ▶ 32/591
> > > ERROR:../../tests/qtest/m
On 15/12/22 13:37, Michael Tokarev wrote:
Introduced by: aba578bdace5303a441f8a37aad781b5cb06f38c
Signed-off-by: Michael Tokarev
---
hw/cxl/cxl-cdat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method
doesn't do anything that's invalid in the hold phase, so the
conversion is simple and not a behaviour change.
Note that we must convert this base class before we can convert the
TYPE_ARM_SMMUV3 subclass -- transitional support i
On Sun, Dec 11, 2022 at 1:29 PM Vysakh P Pillai
wrote:
>
> Add support to optionally specify a memory region container
> to be used to override the default system memory used
> by the the RISCV harts when they are realized. Additional
> memory regions can be added as sub-regions of this container
From: Gavin Shan
This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.
No functional change intended.
Signed-off-by: Gavin S
Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy
reset method doesn't do anything that's invalid in the hold phase, so
the conversion only requires changing it to a hold phase method, and
using the 3-phase versions of the "save the parent reset method and
chain to it" code.
Signed-
Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221109161444.3397405-8-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_its_common.c | 7 ---
1 file changed, 4 i
linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20221215
for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af:
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15
11:1
Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221109161444.3397405-6-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_common.c | 7 ---
1 file changed, 4 insertion
From: Luke Starrett
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:
"indicates the maximum SPI INTID that the GIC implementation supports"
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
for the internal 16x SGI's and 16x PPI's. However,
On 11/9/22 00:13, John Johnson wrote:
Signed-off-by: John G Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
---
hw/vfio/pci.c | 4
hw/vfio/pci.h | 1 +
hw/vfio/user.c | 7 +--
hw/vfio/user.h | 1 +
4 files changed, 11 insertions(+), 2 deletions(-)>
diff
It has only one caller---inline it and remove the function.
Signed-off-by: Paolo Bonzini
---
block.c | 6 --
block/block-backend.c| 2 +-
include/block/block-io.h | 5 -
3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/block.c b/block.c
index 9c2ac757e4
From: Zhuojia Shen
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.
Specifically, the following new ID registers/fields are exposed to
u
Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221109161444.3397405-9-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_its.c | 14 +-
1 file changed, 9 insertions(+)
On Wed, 14 Dec 2022 at 16:46, Markus Armbruster wrote:
>
> The following changes since commit ea3a008d2d9ced9c4f93871c823baee237047f93:
>
> Update VERSION for v7.2.0-rc4 (2022-12-06 19:53:34 -0500)
>
> are available in the Git repository at:
>
> https://repo.or.cz/qemu/armbru.git tags/pull-mis
On Thu, 15 Dec 2022 at 13:06, Peter Maydell wrote:
>
> On Wed, 14 Dec 2022 at 16:46, Markus Armbruster wrote:
> >
> > The following changes since commit ea3a008d2d9ced9c4f93871c823baee237047f93:
> >
> > Update VERSION for v7.2.0-rc4 (2022-12-06 19:53:34 -0500)
> >
> > are available in the Git r
Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
3 files chang
On Thu, 15 Dec 2022 at 12:52, Dr. David Alan Gilbert
wrote:
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > It doesn't seem to repro running manually, my guess is that
> > it happens because the machine is heavily loaded doing the
> > whole build-and-test cycle.
>
> Yeh; I think we'll st
blkdebug events can be called from either non-coroutine or coroutine
contexts. However, suspend actions only make sense from within
a coroutine. Currently, using those action would lead to an abort() in
qemu_coroutine_yield() ("Co-routine is yielding to no one"). Catch them
and print an error in
On Thu, Dec 8, 2022 at 10:54 PM Mayuresh Chitale
wrote:
>
> Sync headers with kernel commit 76dcd734eca2
>
> Signed-off-by: Mayuresh Chitale
> Reviewed-by: Andrew Jones
> ---
> include/standard-headers/drm/drm_fourcc.h | 34 -
> include/standard-headers/linux/ethtool.h | 63 +
On 11/9/22 00:13, John Johnson wrote:
Signed-off-by: John G Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
---
hw/vfio/trace-events | 15 +++
hw/vfio/user.c | 26 ++
2 files changed, 41 insertions(+)
I would introduce th
qemu-io's do_co_pwrite_zeroes is reinventing the coroutine wrapper
blk_pwrite_zeroes. Just use the real thing directly.
Signed-off-by: Paolo Bonzini
---
qemu-io-cmds.c | 55 +-
1 file changed, 9 insertions(+), 46 deletions(-)
diff --git a/qemu-io
Hi,
I came across this post where Ralf-Philipp is looking for a freelancer
to implement PPC VLE support in QEMU:
https://chaos.social/@rpw/109516326028642262
It mentions upstreaming the code and I've included QEMU PPC
maintainers in this email so they can discuss the project with
Ralf-Philipp. Tha
On Wed, 14 Dec 2022 at 10:16, Thomas Huth wrote:
>
> Hi!
>
> The following changes since commit 5204b499a6cae4dfd9fe762d5e6e82224892383b:
>
> mailmap: Fix Stefan Weil author email (2022-12-13 15:56:57 -0500)
>
> are available in the Git repository at:
>
> https://gitlab.com/thuth/qemu.git tag
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 15 Dec 2022 at 12:52, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > It doesn't seem to repro running manually, my guess is that
> > > it happens because the machine is heavily loaded doing
Am 15.12.2022 um 14:02 hat Paolo Bonzini geschrieben:
> blkdebug events can be called from either non-coroutine or coroutine
> contexts. However, suspend actions only make sense from within
> a coroutine. Currently, using those action would lead to an abort() in
> qemu_coroutine_yield() ("Co-rout
From: Longpeng
Supports vdpa-dev, we can use the deivce directly:
-M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \
vhost-vdpa-device,vhostdev=/dev/vhost-vdpa-x
Reviewed-by: Stefano Garzarella
Acked-by: Jason Wang
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5 +
h
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