Re: [PATCH 0/6] Enable Cubieboard A10 boot SPL from SD card

Hi Strahinja, On Thu, Dec 8, 2022 at 8:24 PM Strahinja Jankovic < strahinjapjanko...@gmail.com> wrote: > Hi Niek, > > On Wed, Dec 7, 2022 at 9:25 PM Niek Linnenbank > wrote: > > > > Hello Strahinja, > > > > Thanks for contribution these patches, and also taking the H3 into > account :-) > > Than

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

When the request times out, the kernel should be printing the command ID. What does that say? The driver thinks the 0 is invalid, so I'm just curious what value it's expecting. On Thu, Dec 8, 2022, 8:13 PM Guenter Roeck wrote: > On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote: > >

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

On Thu, Dec 08, 2022 at 12:13:55PM -0800, Guenter Roeck wrote: > On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote: > > > > > > A cq head doorbell mmio is skipped... And it is not the fault of the > > > kernel. The kernel is in it's good right to skip the mmio since the cq > > > eventi

Re: [PATCH] mailmap: Fix Stefan Weil author email

Am 08.12.22 um 16:55 schrieb Philippe Mathieu-Daudé: Fix authorship of commits 266aaedc37~..ac14949821. See commit 3bd2608db7 ("maint: Add .mailmap entries for patches claiming list authorship") for rationale. Signed-off-by: Philippe Mathieu-Daudé --- .mailmap | 1 + 1 file changed, 1 inser

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

On 12/8/22 12:28, Keith Busch wrote: When the request times out, the kernel should be printing the command ID. What does that say? The driver thinks the 0 is invalid, so I'm just curious what value it's expecting. After some time I see the following. ... [ 88.071197] nvme nvme0: invalid i

Re: CVMSEG Emulation

Hi, This address range is located in KSEG3… Doesn’t seems to be a good location for userspace program. I think you have two options to make target_mmap work, the first would be rising TARGET_VIRT_ADDR_SPACE_BITS to 64 bit. That may break some user space applications storing pointer tags on high

Re: [PATCH 1/2] target/riscv: Simplify helper_sret() a little bit

On Wed, 2022-12-07 at 17:00 +0800, Bin Meng wrote: > There are 2 paths in helper_sret() and the same mstatus update codes > are replicated. Extract the common parts to simplify it a little bit. > > Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Wilfred > --- > >  target/riscv/op_helper.c

Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order

On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote: > SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa Wilfred > --- > > (no changes since v1) > >  hw/riscv/Kconfig | 16 +---

Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote: > hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt > controllers regardless of how MSI is implemented. msi_nonbroken is > initialized to true in sifive_plic_realize(). > > Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selectio

Re: [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0

On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote: > At present the SiFive PLIC model "priority-base" expects interrupt > priority register base starting from source 1 instead source 0, > that's why on most platforms "priority-base" is set to 0x04 except > 'opentitan' machine. 'opentitan' should ha

Re: [RFC v4 3/3] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)

On Thu, Dec 08, 2022 at 10:55:58PM +, Fan Ni wrote: > On Mon, Nov 28, 2022 at 10:01:57AM -0500, Gregory Price wrote: > > > > -if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) { > > +if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || > > +(cxl_dstate->pmem_size < CXL_

[PATCH v4 09/27] tcg/s390x: Remove FAST_BCR_SER facility check

The fast-bcr-serialization facility is bundled into facility 45, along with load-on-condition. We are checking this at startup. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 1 - tcg/s390x/tcg-target.c.inc | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v4 05/27] tcg/s390x: Check for long-displacement facility at startup

We are already assuming the existance of long-displacement, but were not being explicit about it. This has been present since z990. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 6 -- tcg/s390x/tcg-target.c.inc | 15 +++ 2 files changed, 19 insertions(+), 2

[PATCH v4 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz

Reuse code from movcond to conditionally copy a2 to dest, based on the condition codes produced by FLOGR. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.c.inc | 20 +++- 2 files changed, 12 inser

[PATCH v4 06/27] tcg/s390x: Check for extended-immediate facility at startup

The extended-immediate facility was introduced in z9-109, which itself was end-of-life in 2017. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 4 +- tcg/s390x/tcg-target.c.inc | 231 +++-- 2 files changed, 72 insertions(+), 163 deletions(-) d

[PATCH v4 22/27] tcg/s390x: Support SELGR instruction in movcond

The new select instruction provides two separate register inputs, whereas the old load-on-condition instruction overlaps one of the register inputs with the destination. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 15 +++ 1 file ch

[PATCH v4 08/27] tcg/s390x: Check for load-on-condition facility at startup

The general-instruction-extension facility was introduced in z196, which itself was end-of-life in 2021. In addition, z196 is the minimum CPU supported by our set of supported operating systems: RHEL 7 (z196), SLES 12 (z196) and Ubuntu 16.04 (zEC12). Check for facility number 45, which will be th

[PATCH v4 00/27] tcg/s390x: misc patches

Based-on: 20221202053958.223890-1-richard.hender...@linaro.org ("[PATCH for-8.0 v3 00/34] tcg misc patches") Changes from v3: * Require z196 as minimum cpu -- 6 new patches removing checks. * Tighten constraints on AND, OR, XOR, CMP, trying get the register allocator to hoist things that c

[PATCH v4 19/27] tcg/s390x: Support MIE3 logical operations

This is andc, orc, nand, nor, eqv. We can use nor for implementing not. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 3 + tcg/s390x/tcg-target.h | 25 tcg/s390x/tcg-target.c.inc | 102

[PATCH v4 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64

Drop support for sequential OR and XOR, as the serial dependency is slower than loading the constant first. Let the register allocator handle such immediates by matching only what one insn can achieve. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-ta

[PATCH v4 21/27] tcg/s390x: Generalize movcond implementation

Generalize movcond to support pre-computed conditions, and the same set of arguments at all times. This will be assumed by a following patch, which needs to reuse tgen_movcond_int. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 3 +- tcg/s3

[PATCH v4 07/27] tcg/s390x: Check for general-instruction-extension facility at startup

The general-instruction-extension facility was introduced in z10, which itself was end-of-life in 2019. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 10 ++-- tcg/s390x/tcg-target.c.inc | 100 - 2 files changed, 49 insertions(+), 61 deleti

[PATCH v4 25/27] tcg/s390x: Tighten constraints for 64-bit compare

Give 64-bit comparison second operand a signed 33-bit immediate. This is the smallest superset of uint32_t and int32_t, as used by CLGFI and CGFI respectively. The rest of the 33-bit space can be loaded into TCG_TMP0. Drop use of the constant pool. Signed-off-by: Richard Henderson --- tcg/s390

[PATCH v4 01/27] tcg/s390x: Use register pair allocation for div and mulu2

Previously we hard-coded R2 and R3. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 ++-- tcg/s390x/tcg-target-con-str.h | 8 +-- tcg/s390x/tcg-target.c.inc | 43 +- 3 files changed, 35 insertions(+)

[PATCH v4 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond

Return both regular and inverted condition codes from tgen_cmp2. This lets us choose after the fact which comparision we want. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-)

[PATCH v4 26/27] tcg/s390x: Cleanup tcg_out_movi

Merge maybe_out_small_movi, as it no longer has additional users. Use is_const_p{16,32}. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 52 -- 1 file changed, 16 insertions(+), 36 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s

[PATCH v4 18/27] tcg/s390x: Tighten constraints for and_i64

Let the register allocator handle such immediates by matching only what one insn can achieve. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target-con-str.h | 2 + tcg/s390x/tcg-target.c.inc | 114 + 3 files chang

[PATCH v4 10/27] tcg/s390x: Remove DISTINCT_OPERANDS facility check

The distinct-operands facility is bundled into facility 45, along with load-on-condition. We are checking this at startup. Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there is no space savings for avoiding the distinct-operands insn. Signed-off-by: Richard Henderson --- tcg/s390

[PATCH v4 02/27] tcg/s390x: Remove TCG_REG_TB

This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and several follow-up patches. The primary motivation is to reduce the less-tested code paths, pre-z10. Secondarily, this allows the unconditional use of TCG_TARGET_HAS_direct_jump, which might be more important for performance than an

[PATCH v4 16/27] tcg/s390x: Issue XILF directly for xor_i32

There is only one instruction that is applicable to a 32-bit immediate xor. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 871fcb7683..fc304327fc 100

[PATCH v4 04/27] tcg/s390x: Remove USE_LONG_BRANCHES

The size of a compiled TB is limited by the uint16_t used by gen_insn_end_off[] -- there is no need for a 32-bit branch. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 9 - 1 file changed, 9 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c

[PATCH v4 24/27] tcg/s390x: Implement ctpop operation

There is an older form that produces per-byte results, and a newer form that produces per-register results. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 4 ++-- tcg/s390x/tcg-target.c.inc | 36 2 files chan

[PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction

The MIE2 facility adds a 3-operand signed 64x64->128 multiply. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 8 3 files changed, 10 insertions(+), 1 deleti

[PATCH v4 14/27] tcg/s390x: Support MIE2 multiply single instructions

The MIE2 facility adds 3-operand versions of multiply. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 1 + tcg/s390x/tcg-target.c.inc | 34 -- 3 files changed, 26 ins

[PATCH v4 11/27] tcg/s390x: Use LARL+AGHI for odd addresses

Add one instead of dropping odd addresses to the constant pool. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.i

[PATCH v4 27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi

Load constants in no more than two insns, which turns out to be faster than using the constant pool. Suggested-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 23 +-- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/tcg/s3

[PATCH v4 03/27] tcg/s390x: Always set TCG_TARGET_HAS_direct_jump

Since USE_REG_TB is removed, there is no need to load the target TB address into a register. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 48 +++--- 2 files changed, 10 insertions(+), 40 deletions(-) diff -

[PATCH v4 13/27] tcg/s390x: Distinguish RIE formats

There are multiple variations, with different fields. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 47 +- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x

[PATCH v4 12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats

One has 3 register arguments; the other has 2 plus an m3 field. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 57 +- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b

Re: [PATCH] blockdev: add 'media=cdrom' argument to support usb cdrom emulated as cdrom

Thanks. -device usb-bot,id=bot0 -device scsi-{cd,hd},bus=bot0.0,drive=drive0 Qemu implements virtio scsi to emulate scsi controller, but if the virtual machine(for example windows guest os) don't install the virtio scsi driver, it don't work i need the function: emulate cdrom in guest, suppo

Re: [RFC v4 3/3] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)

On Mon, Nov 28, 2022 at 10:01:57AM -0500, Gregory Price wrote: > From: Gregory Price > > This commit enables each CXL Type-3 device to contain one volatile > memory region and one persistent region. > > Two new properties have been added to cxl-type3 device initialization: > [volatile-memde

Re: [RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR

On 2022/12/8 23:11, Christoph Muellner wrote: From: Christoph Müllner Setting flags using OR might work, but is not optimal for a couple of reasons: * No way grep for stores to the field MEM_IDX. * The return value of cpu_mmu_index() is not masked (not a real problem as long as cpu_mmu_ind

Re: [PATCH RESEND v3 00/10] migration: introduce dirtylimit capability

Ping ？ 在 2022/12/4 1:09, huang...@chinatelecom.cn 写道: From: Hyman Huang(黄勇) v3(resend): - fix the syntax error of the topic. v3: This version make some modifications inspired by Peter and Markus as following: 1. Do the code clean up in [PATCH v2 02/11] suggested by Markus 2. Replace the [PATC

Target-dependent include path, why?

I stumbled over this: ../include/ui/qemu-pixman.h:12:10: fatal error: pixman.h: No such file or directory 12 | #include | ^~ Works when included into target-dependent code. Running make -V=1 shows we're passing a number of -I only when compiling target-dep

[PATCH v3 8/8] accel/tcg: Move remainder of page locking to tb-maint.c

The only thing that still touches PageDesc in translate-all.c are some locking routines related to tb-maint.c which have not yet been moved. Do so now. Move some code up in tb-maint.c as well, to untangle the maze of ifdefs, and allow a sensible final ordering. Move some declarations from exec/t

[PATCH v3 5/8] accel/tcg: Move page_{get,set}_flags to user-exec.c

This page tracking implementation is specific to user-only, since the system softmmu version is in cputlb.c. Move it out of translate-all.c to user-exec.c. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 17 ++ accel/tcg/translate-all.c | 350

[PATCH v3 3/8] accel/tcg: Use interval tree for TBs in user-only mode

Begin weaning user-only away from PageDesc. Since, for user-only, all TB (and page) manipulation is done with a single mutex, and there is no virtual/physical discontinuity to split a TB across discontinuous pages, place all of the TBs into a single IntervalTree. This makes it trivial to find all

[PATCH v3 7/8] accel/tcg: Move PageDesc tree into tb-maint.c for system

Now that PageDesc is not used for user-only, and for system it is only used for tb maintenance, move the implementation into tb-main.c appropriately ifdefed. We have not yet eliminated all references to PageDesc for user-only, so retain a typedef to the structure without definition. Signed-off-by

[PATCH v3 1/8] util: Add interval-tree.c

Copy and simplify the Linux kernel's interval_tree_generic.h, instantiating for uint64_t. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/interval-tree.h| 99 tests/unit/test-interval-tree.c | 209 util/interval-tree.c| 882 +

[PATCH v3 6/8] accel/tcg: Use interval tree for user-only page tracking

Finish weaning user-only away from PageDesc. Using an interval tree to track page permissions means that we can represent very large regions efficiently. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/967 Resolves: https://gitla

[PATCH v3 4/8] accel/tcg: Use interval tree for TARGET_PAGE_DATA_SIZE

Continue weaning user-only away from PageDesc. Use an interval tree to record target data. Chunk the data, to minimize allocation overhead. Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 1 - accel/tcg/user-exec.c | 99 --- 2 files changed,

[PATCH v3 2/8] accel/tcg: Rename page_flush_tb

Rename to tb_remove_all, to remove the PageDesc "page" from the name, and to avoid suggesting a "flush" in the icache sense. Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/t

[PATCH v3 0/8] accel/tcg: Rewrite user-only vma tracking

The primary motivator here are the numerous bug reports (e.g. #290) about not being able to handle very large memory allocations. I presume all or most of these are due to guest use of the clang address sanitizer, which allocates a massive shadow vma. This patch set copies the linux kernel code fo

Re: Target-dependent include path, why?

On 12/8/22 23:12, Markus Armbruster wrote: I stumbled over this: ../include/ui/qemu-pixman.h:12:10: fatal error: pixman.h: No such file or directory 12 | #include | ^~ Works when included into target-dependent code. Running make -V=1 shows we're passi

Re: [PATCH v10 6/9] KVM: Unmap existing mappings when change the memory attributes

On Thu, Dec 08, 2022 at 07:20:43PM +0800, Chao Peng wrote: > On Wed, Dec 07, 2022 at 04:13:14PM +0800, Yuan Yao wrote: > > On Fri, Dec 02, 2022 at 02:13:44PM +0800, Chao Peng wrote: > > > Unmap the existing guest mappings when memory attribute is changed > > > between shared and private. This is ne

Re: [PATCH v10 8/9] KVM: Handle page fault for private memory

On Thu, Dec 08, 2022 at 07:23:46PM +0800, Chao Peng wrote: > On Thu, Dec 08, 2022 at 10:29:18AM +0800, Yuan Yao wrote: > > On Fri, Dec 02, 2022 at 02:13:46PM +0800, Chao Peng wrote: > > > A KVM_MEM_PRIVATE memslot can include both fd-based private memory and > > > hva-based shared memory. Architect

[PATCH v2 2/2] target/ppc: Check DEXCR on hash{st, chk} instructions

Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently the only implementation which has the DEXCR. Reviewed-by: Daniel Henrique Barboza Signed-off-by:

[PATCH v2 0/2] target/ppc: Implement Dynamic Execution Control Registers

Implements the Dynamic Execution Control Register (DEXCR) and the Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction enable) and 6 (Privileged hash instruction enable) have architectural effects. Other aspects

[PATCH v2 1/2] target/ppc: Implement the DEXCR and HDEXCR

Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the

Re: [PATCH v10 5/9] KVM: Use gfn instead of hva for mmu_notifier_retry

On Tue, Dec 06, 2022 at 03:48:50PM +, Fuad Tabba wrote: ... > > > > > > */ > > > > - if (unlikely(kvm->mmu_invalidate_in_progress) && > > > > - hva >= kvm->mmu_invalidate_range_start && > > > > - hva < kvm->mmu_invalidate_range_end) > > > > - re

Re: [PATCH v3 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM

On 12/8/2022 2:25 PM, Xiaoyao Li wrote: > Bit[2:0] of CPUID.14H_01H:EAX stands as a whole for the number of INTEL > PT ADDR RANGES. For unsupported value that exceeds what KVM reports, > report it as a whole in mark_unavailable_features() as well. > Maybe this patch can be put before 3/8. > S

Re: [PATCH v3 6/8] target/i386/intel-pt: Enable host pass through of Intel PT

On 12/8/2022 2:25 PM, Xiaoyao Li wrote: > commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") > added the support of Intel PT by making CPUID[14] of PT as fixed feature > set (from ICX) for any CPU model on any host. This truly breaks the PT > exposure on Intel SPR platform b

Re: Target-dependent include path, why?

On 9/12/22 06:24, Richard Henderson wrote: On 12/8/22 23:12, Markus Armbruster wrote: I stumbled over this: ../include/ui/qemu-pixman.h:12:10: fatal error: pixman.h: No such file or directory     12 | #include    |  ^~ Works when included into target-depende

Re: [PATCH v3 2/8] accel/tcg: Rename page_flush_tb

On 9/12/22 06:19, Richard Henderson wrote: Rename to tb_remove_all, to remove the PageDesc "page" from the name, and to avoid suggesting a "flush" in the icache sense. Signed-off-by: Richard Henderson --- accel/tcg/tb-maint.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-)

Re: [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge

On 12/8/2022 2:25 PM, Xiaoyao Li wrote: > For IceLake-server, it's just the same as using the default PT > feature set since the default one is exact taken from ICX. > > For Snowridge, define it according to real SNR silicon capabilities. > > Signed-off-by: Xiaoyao Li > --- > target/i386/cpu

Re: [PATCH v3 5/8] accel/tcg: Move page_{get,set}_flags to user-exec.c

On 9/12/22 06:19, Richard Henderson wrote: This page tracking implementation is specific to user-only, since the system softmmu version is in cputlb.c. Move it out of translate-all.c to user-exec.c. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 1

Re: [PATCH v3 6/8] accel/tcg: Use interval tree for user-only page tracking

On 9/12/22 06:19, Richard Henderson wrote: Finish weaning user-only away from PageDesc. Using an interval tree to track page permissions means that we can represent very large regions efficiently. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290 Resolves: https://gitlab.com/qemu-proj

Re: [PATCH v3 7/8] accel/tcg: Move PageDesc tree into tb-maint.c for system

On 9/12/22 06:19, Richard Henderson wrote: Now that PageDesc is not used for user-only, and for system it is only used for tb maintenance, move the implementation into tb-main.c appropriately ifdefed. We have not yet eliminated all references to PageDesc for user-only, so retain a typedef to the

Re: [RFC PATCH] migration: reduce time of loading non-iterable vmstate

On 2022/12/9 上午12:00, Peter Xu wrote: On Thu, Dec 08, 2022 at 10:39:11PM +0800, Chuang Xu wrote: On 2022/12/8 上午6:08, Peter Xu wrote: On Thu, Dec 08, 2022 at 12:07:03AM +0800, Chuang Xu wrote: On 2022/12/6 上午12:28, Peter Xu wrote: Chuang, No worry on the delay; you're faster than when I read

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