Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

On Dec 8 08:16, Klaus Jensen wrote: > On Dec 7 09:49, Guenter Roeck wrote: > > Hi, > > > > On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote: > > > Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3) > > > and Shadow Doorbel buffer & EventIdx buffer handling logic (Se

Re: [PATCH v11 1/2] vhost-vdpa: Skip the range check while MR is IOMMU

On Thu, 8 Dec 2022 at 15:42, Jason Wang wrote: > > On Wed, Nov 30, 2022 at 1:33 PM Cindy Lu wrote: > > > > Skip the check in vhost_vdpa_listener_skipped_section() while > > MR is IOMMU, Move this check to vhost_vdpa_iommu_map_notify() > > > > Signed-off-by: Cindy Lu > > --- > > hw/virtio/vhost

RE: [PATCH] target/i386/hax: Add XCR0 support

Hi, Paolo, As HAXM v7.8.0 is released and it added XCR0 support, could you help to merge this patch to add corresponding support into HAX user space of QEMU? The patch has been attached below. Thanks. Best Regards, Wenchao - From b1789f2523d06798b8883664bfa9a9

[PATCH 1/1] hw/nvme: fix missing cq eventidx update

From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq eventidx fixes the issue. Fixes: 3f7fe8de3d4

[PATCH 0/1] hw/nvme: shadow doorbells broken on riscv64

From: Klaus Jensen Guenter reports[1] that hw/nvme is broken on riscv64. This is a regression since 7.1, so this does not warrent an rc5 for 7.2. I'm sure Guenter can carry this patch in his tree, and maybe we can get this out in a stable release. I really wonder why this issue only shows up on

Re: [PATCH v10 3/9] KVM: Extend the memslot to support fd-based private memory

On 12/2/2022 2:13 PM, Chao Peng wrote: .. Together with the change, a new config HAVE_KVM_RESTRICTED_MEM is added and right now it is selected on X86_64 only. From the patch implementation, I have no idea why HAVE_KVM_RESTRICTED_MEM is needed.

Re: [PATCH-for-8.0 1/4] cputlb: Restrict SavedIOTLB to system emulation

Philippe Mathieu-Daudé writes: > Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in > case of reset") added the SavedIOTLB structure -- which is > system emulation specific -- in the generic CPUState structure. > > Signed-off-by: Philippe Mathieu-Daudé > --- > accel/tcg/cputlb.c

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > should call riscv_timer_write_timecmp() whenever htimedelta changes. > > > > Fixes: 3ec0fe18a31f ("target/risc

[PATCH v13 2/7] s390x/cpu topology: reporting the CPU topology to the guest

The guest uses the STSI instruction to get information on the CPU topology. Let us implement the STSI instruction for the basis CPU topology level, level 2. Signed-off-by: Pierre Morel --- target/s390x/cpu.h | 76 + target/s390x/kvm/cpu_topology.c | 186 +++

[PATCH v13 4/7] s390x/cpu_topology: CPU topology migration

The migration can only take place if both source and destination of the migration both use or both do not use the CPU topology facility. We indicate a change in topology during migration postload for the case the topology changed between source and destination. Signed-off-by: Pierre Morel --- t

[PATCH v13 0/7] s390x: CPU Topology

Hi, Implementation discussions == CPU models -- Since the S390_FEAT_CONFIGURATION_TOPOLOGY is already in the CPU model for old QEMU we could not activate it as usual from KVM but needed a KVM capability: KVM_CAP_S390_CPU_TOPOLOGY. Checking and enabling this capabi

[PATCH v13 3/7] s390x/cpu_topology: resetting the Topology-Change-Report

During a subsystem reset the Topology-Change-Report is cleared by the machine. Let's ask KVM to clear the Modified Topology Change Report (MTCR) bit of the SCA in the case of a subsystem reset. Signed-off-by: Pierre Morel Reviewed-by: Nico Boehr Reviewed-by: Janis Schoetterl-Glausch --- target

[PATCH v13 5/7] s390x/cpu_topology: interception of PTF instruction

When the host supports the CPU topology facility, the PTF instruction with function code 2 is interpreted by the SIE, provided that the userland hypervizor activates the interpretation by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension. The PTF instructions with function code 0 and 1 are interce

[PATCH v13 1/7] s390x/cpu topology: Creating CPU topology device

We will need a Topology device to transfer the topology during migration and to implement machine reset. The device creation is fenced by s390_has_topology(). Signed-off-by: Pierre Morel --- include/hw/s390x/cpu-topology.h | 44 ++ hw/s390x/cpu-topology.c | 149

[PATCH v13 6/7] s390x/cpu_topology: activating CPU topology

The KVM capability, KVM_CAP_S390_CPU_TOPOLOGY is used to activate the S390_FEAT_CONFIGURATION_TOPOLOGY feature and the topology facility for the guest in the case the topology is available in QEMU and in KVM. The feature is disabled by default and fenced for SE (secure execution). Signed-off-by:

[PATCH v13 7/7] docs/s390x: document s390x cpu topology

Add some basic examples for the definition of cpu topology in s390x. Signed-off-by: Pierre Morel --- docs/system/s390x/cpu-topology.rst | 87 ++ docs/system/target-s390x.rst | 1 + 2 files changed, 88 insertions(+) create mode 100644 docs/system/s390x/cpu-topo

Re: [PATCH-for-8.0 2/4] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API

On 7/12/22 21:15, Peter Maydell wrote: On Wed, 7 Dec 2022 at 18:27, Philippe Mathieu-Daudé wrote: On 7/12/22 19:23, Peter Maydell wrote: On Wed, 7 Dec 2022 at 17:42, Philippe Mathieu-Daudé wrote: Both insert/remove_breakpoint() handlers are used in system and user emulation. We can not use

Re: [PATCH-for-8.0 1/4] cputlb: Restrict SavedIOTLB to system emulation

On 8/12/22 09:40, Alex Bennée wrote: Philippe Mathieu-Daudé writes: Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Signed-off-by: Philippe Mathieu-Daudé -

[PATCH] gitlab-ci: Check building ppc64 without TCG

Building QEMU for ppc64 hosts with --disable-tcg used to break a couple of times in the past, see e.g. commit a01b64cee7 ("target/ppc: Put do_rfi under a TCG-only block") or commit 049b4ad669 ("target/ppc: Fix build warnings when building with 'disable-tcg'"), so we should test this in our CI to av

Re: [PATCH 1/1] hw/nvme: fix missing cq eventidx update

On 8/12/22 09:29, Klaus Jensen wrote: From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq event

Re: [PATCH] gitlab-ci: Check building ppc64 without TCG

On 8/12/22 11:15, Thomas Huth wrote: Building QEMU for ppc64 hosts with --disable-tcg used to break a couple of times in the past, see e.g. commit a01b64cee7 ("target/ppc: Put do_rfi under a TCG-only block") or commit 049b4ad669 ("target/ppc: Fix build warnings when building with 'disable-tcg'"),

Re: [PATCH] gitlab-ci: Check building ppc64 without TCG

On 08/12/2022 11.17, Philippe Mathieu-Daudé wrote: On 8/12/22 11:15, Thomas Huth wrote: Building QEMU for ppc64 hosts with --disable-tcg used to break a couple of times in the past, see e.g. commit a01b64cee7 ("target/ppc: Put do_rfi under a TCG-only block") or commit 049b4ad669 ("target/ppc: Fi

Re: [PATCH 1/1] hw/nvme: fix missing cq eventidx update

On Dec 8 11:14, Philippe Mathieu-Daudé wrote: > On 8/12/22 09:29, Klaus Jensen wrote: > > From: Klaus Jensen > > > > Prior to reading the shadow doorbell cq head, we have to update the > > eventidx. Otherwise, we risk that the driver will skip an mmio doorbell > > write. This happens on riscv64,

Re: [PATCH 0/1] hw/nvme: shadow doorbells broken on riscv64

On 8/12/22 09:29, Klaus Jensen wrote: From: Klaus Jensen Guenter reports[1] that hw/nvme is broken on riscv64. This is a regression since 7.1, so this does not warrent an rc5 for 7.2. I'm sure Guenter can carry this patch in his tree, and maybe we can get this out in a stable release. Delayi

Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

On 7/12/22 11:03, Bin Meng wrote: hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in sifive_plic_realize(). Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from RISC-V machines.

Re: [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

On 7/12/22 11:03, Bin Meng wrote: hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in both riscv_aplic_realize() and riscv_imsic_realize(). Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.

Re: [PULL 11/21] docs: Build and install all the docs in a single manual

On Thu, 8 Dec 2022 at 06:55, Stefan Weil wrote: > > Am 12.01.21 um 17:57 schrieb Peter Maydell: > [...] > > diff --git a/docs/meson.build b/docs/meson.build > > + sphinxdocs += this_manual > > + install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: > > true) > > This line cause

Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order

On 7/12/22 11:03, Bin Meng wrote: SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/Kconfig | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) Reviewed-by: Philip

Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()

On 7/12/22 11:03, Bin Meng wrote: The realize() callback has an errp for us to propagate the error up. While we are here, corret the wrong multi-line comment format. Typo "correct" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Bin Meng --- Changes in v2: - new patch: "hw/intc: sifiv

Re: [PATCH v10 6/9] KVM: Unmap existing mappings when change the memory attributes

On Wed, Dec 07, 2022 at 05:16:34PM +, Fuad Tabba wrote: > Hi, > > On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote: > > > > Unmap the existing guest mappings when memory attribute is changed > > between shared and private. This is needed because shared pages and > > private pages are from diffe

Re: [PATCH v10 7/9] KVM: Update lpage info when private/shared memory are mixed

On Tue, Dec 06, 2022 at 10:42:24PM -0800, Isaku Yamahata wrote: > On Tue, Dec 06, 2022 at 08:02:24PM +0800, > Chao Peng wrote: > > > On Mon, Dec 05, 2022 at 02:49:59PM -0800, Isaku Yamahata wrote: > > > On Fri, Dec 02, 2022 at 02:13:45PM +0800, > > > Chao Peng wrote: > > > > > > > A large page

Re: [PATCH v10 6/9] KVM: Unmap existing mappings when change the memory attributes

On Wed, Dec 07, 2022 at 04:13:14PM +0800, Yuan Yao wrote: > On Fri, Dec 02, 2022 at 02:13:44PM +0800, Chao Peng wrote: > > Unmap the existing guest mappings when memory attribute is changed > > between shared and private. This is needed because shared pages and > > private pages are from different

Re: [PATCH v10 8/9] KVM: Handle page fault for private memory

On Thu, Dec 08, 2022 at 10:29:18AM +0800, Yuan Yao wrote: > On Fri, Dec 02, 2022 at 02:13:46PM +0800, Chao Peng wrote: > > A KVM_MEM_PRIVATE memslot can include both fd-based private memory and > > hva-based shared memory. Architecture code (like TDX code) can tell > > whether the on-going fault is

Re: [PATCH v10 3/9] KVM: Extend the memslot to support fd-based private memory

On Thu, Dec 08, 2022 at 04:37:03PM +0800, Xiaoyao Li wrote: > On 12/2/2022 2:13 PM, Chao Peng wrote: > > .. > > > Together with the change, a new config HAVE_KVM_RESTRICTED_MEM is added > > and right now it is selected on X86_64 only. > > > > From the patch implementation, I have no idea why HA

Re: [PATCH v2 00/12] qemu-img info: Show protocol-level information

On 20.06.22 18:26, Hanna Reitz wrote: Hi, This series is a v2 to: https://lists.nongnu.org/archive/html/qemu-block/2022-05/msg00042.html Ping, it looks like this still applies (to the master branch and kevin’s block-next branch at least). Hanna So the final state is that despite the QAPI

[PATCH v2 3/3] hw/nvme: fix missing cq eventidx update

From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq eventidx fixes the issue. Fixes: 3f7fe8de3d4

[PATCH v2 0/3] hw/nvme: shadow doorbells broken on riscv64

From: Klaus Jensen Guenter reports[1] that hw/nvme is broken on riscv64. This is a regression since 7.1, so this does not warrent an rc5 for 7.2. I'm sure Guenter can carry this patch in his tree, and maybe we can get this out in a stable release. I really wonder why this issue only shows up on

[PATCH v2 2/3] hw/nvme: rename shadow doorbell related trace events

From: Klaus Jensen Rename the trace events related to writing the event index and reading the doorbell value to make it more clear that the event is associated with an actual update (write or read respectively). Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 11 +++ hw/nvme/tra

[PATCH v2 1/3] hw/nvme: use QOM accessors

From: Klaus Jensen Replace various ->parent_obj use with the equivalent QOM accessors. Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 89 +++--- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index e

[PATCH] target/i386/gdbstub: Fix a bug about order of FPU stack in 'g' packets.

Before this commit, when GDB attached an OS working on QEMU, order of FPU stack registers printed by GDB command 'info float' was wrong. There was a bug causing the problem in 'g' packets sent by QEMU to GDB. The packets have values of registers of machine emulated by QEMU containing FPU stack regi

Re: [PATCH v2 1/3] hw/nvme: use QOM accessors

On 8/12/22 13:26, Klaus Jensen wrote: From: Klaus Jensen Replace various ->parent_obj use with the equivalent QOM accessors. Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 89 +++--- 1 file changed, 48 insertions(+), 41 deletions(-) Reviewed-

Re: [PATCH v2 2/3] hw/nvme: rename shadow doorbell related trace events

On 8/12/22 13:26, Klaus Jensen wrote: From: Klaus Jensen Rename the trace events related to writing the event index and reading the doorbell value to make it more clear that the event is associated with an actual update (write or read respectively). Signed-off-by: Klaus Jensen --- hw/nvme/c

[PATCH] target/i386: Fix wrong XSAVE feature names

The previous patch changes the name from FEAT_XSAVE_COMP_{LO|HI} to FEAT_XSAVE_XCR0_{LO|HI}, the changes for CPUID.0x12.0x1 should be FEAT_XSAVE_XCR0_{LO|HI}, the SGX can't work in VM if these are not right Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") Signed-off-b

[PATCH] util/oslib-win32: Remove obsolete reference to g_poll code

The comment about g_poll is not required here anymore since the corresponding code has been removed a while ago already. Fixes: b4c6036faa ("configure: bump min required glib version to 2.56") Signed-off-by: Thomas Huth --- util/oslib-win32.c | 4 1 file changed, 4 deletions(-) diff --git

WHPX CPUID-0x40000000

Hi, all May I know why the Hypervisor vendor signature value is cleared to 0 in whpx-all.c? https://gitlab.com/qemu-project/qemu/-/blob/master/target/i386/whpx/whpx-all.c#L1963 switch (cpuid_fn) { case 0x4000: /* Expose the vmware cpufrequency cpuid leaf */ rax = 0x4010; rbx

[PATCH] gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobs

These jobs use their own "script:" section and thus do not profit from the global "--disable-docs" from the template. While we're at it, disable also some GUI front ends here since we do not gain any additional test coverage by compiling those here again. Signed-off-by: Thomas Huth --- .gitlab-c

Re: [PATCH v3 02/13] tcg/s390x: Remove TCG_REG_TB

On Tue, 2022-12-06 at 18:42 -0600, Richard Henderson wrote: > On 12/6/22 16:22, Richard Henderson wrote: > > > Wouldn't it be worth keeping XILF/XIFH here? > > > > I don't know.  It's difficult for me to guess whether a dependency > > chain like > > > > val -> xor -> xor > > > > (3 insns wi

Re: [PATCH] util/oslib-win32: Remove obsolete reference to g_poll code

On 8/12/22 14:32, Thomas Huth wrote: The comment about g_poll is not required here anymore since the corresponding code has been removed a while ago already. Fixes: b4c6036faa ("configure: bump min required glib version to 2.56") Signed-off-by: Thomas Huth --- util/oslib-win32.c | 4 1

[PATCH 1/4] coroutine: Clean up superfluous inclusion of qemu/coroutine.h

Signed-off-by: Markus Armbruster --- crypto/block-luks-priv.h| 1 - include/block/raw-aio.h | 1 - include/scsi/pr-manager.h | 1 - nbd/nbd-internal.h | 1 - blockjob.c | 1 - crypto/block-luks.c | 1 - hw/9pfs/codir.c | 1 - hw/9pfs/cofile.

[PATCH 3/4] coroutine: Clean up superfluous inclusion of qemu/lockable.h

Signed-off-by: Markus Armbruster --- include/qemu/progress_meter.h | 2 +- block/progress_meter.c| 2 ++ tests/unit/test-coroutine.c | 1 - 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/qemu/progress_meter.h b/include/qemu/progress_meter.h index dadf822bbf..0f2c

[PATCH 0/4] coroutine: Clean up includes

Markus Armbruster (4): coroutine: Clean up superfluous inclusion of qemu/coroutine.h coroutine: Move coroutine_fn to qemu/osdep.h, trim includes coroutine: Clean up superfluous inclusion of qemu/lockable.h coroutine: Break inclusion loop crypto/block-luks-priv.h | 1 - include/block

[PATCH 2/4] coroutine: Move coroutine_fn to qemu/osdep.h, trim includes

block/block-hmp-cmds.h and qemu/co-shared-resource.h use coroutine_fn without including qemu/coroutine.h. They compile only if it's already included from elsewhere. I could fix that, but pulling in qemu/coroutine.h and everything it includes just for a macro that expands into nothing feels silly.

[PATCH 4/4] coroutine: Break inclusion loop

qemu/coroutine.h and qemu/lockable.h include each other. Neither header actually needs the other one. Drop #include "qemu/coroutine.h" from qemu/lockable.h to break the loop. All users of lockable.h actually need qemu/coroutine.h, so adjust their #include directives. I'm not dropping the #inclu

Re: [RFC PATCH] migration: reduce time of loading non-iterable vmstate

On 2022/12/8 上午6:08, Peter Xu wrote: On Thu, Dec 08, 2022 at 12:07:03AM +0800, Chuang Xu wrote: On 2022/12/6 上午12:28, Peter Xu wrote: Chuang, No worry on the delay; you're faster than when I read yours. :) On Mon, Dec 05, 2022 at 02:56:15PM +0800, Chuang Xu wrote: As a start, maybe you can

[PATCH 3/3] include/hw/block: Include hw/block/block.h where needed

hw/block/swim.h needs BlockConf. Signed-off-by: Markus Armbruster --- include/hw/block/swim.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h index c1bd5f6555..9b3dcb029d 100644 --- a/include/hw/block/swim.h +++ b/include/hw/block/swim.h @@ -

[PATCH 1/3] include/block: Untangle inclusion loops

We have two inclusion loops: block/block.h -> block/block-global-state.h -> block/block-common.h -> block/blockjob.h -> block/block.h block/block.h -> block/block-io.h -> block/block-common.h -> block/blockjob.h -> block/block.h I believe these go ba

[PATCH 0/3] block: Clean up includes

Based-on: <20221208142306.2642640-1-arm...@redhat.com> Markus Armbruster (3): include/block: Untangle inclusion loops hw/sparc64/niagara: Use blk_name() instead of open-coding it include/hw/block: Include hw/block/block.h where needed include/block/block-common.h | 10 ++

[PATCH 2/3] hw/sparc64/niagara: Use blk_name() instead of open-coding it

Signed-off-by: Markus Armbruster --- hw/sparc64/niagara.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index ab3c4ec346..6725cc61fd 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -23,7 +23,6 @@ */ #incl

Re: [PATCH 2/3] hw/sparc64/niagara: Use blk_name() instead of open-coding it

On 8/12/22 15:39, Markus Armbruster wrote: Signed-off-by: Markus Armbruster --- hw/sparc64/niagara.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 3/3] include/hw/block: Include hw/block/block.h where needed

On 8/12/22 15:39, Markus Armbruster wrote: hw/block/swim.h needs BlockConf. Signed-off-by: Markus Armbruster --- include/hw/block/swim.h | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Philippe Mathieu-Daudé

[PATCH v3 0/3] target/riscv: Apply KVM policy to ISA extensions

Currently the single and multi letter ISA extensions exposed to the guest vcpu don't confirm to the KVM policies. This patchset updates the kvm headers and applies policies set in KVM to the extensions exposed to the guest. These patches can also be found on riscv_kvm_ext_v3 branch at: https://gi

[PATCH v3 1/3] update-linux-headers: Version 6.1-rc8

Sync headers with kernel commit 76dcd734eca2 Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- include/standard-headers/drm/drm_fourcc.h | 34 - include/standard-headers/linux/ethtool.h | 63 +++- include/standard-headers/linux/fuse.h | 6 +- .../linux/i

[PATCH v3 3/3] target/riscv: kvm: Support selecting VCPU extensions

Set the state of each ISA extension on the vcpu depending on what is set in the CPU property and what is allowed by KVM for that extension. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 - target/riscv/kvm.c

[PATCH v3 2/3] target/riscv: Extend isa_ext_data for single letter extensions

Currently the ISA string for a CPU is generated from two different arrays, one for single letter extensions and another for multi letter extensions. Add all the single letter extensions to the isa_ext_data array and use it for generating the ISA string. Also drop 'P' and 'Q' extensions from the lis

Re: [PATCH for 8.0 0/2] virtio-iommu: Fix Replay

On Thu, Dec 08, 2022 at 08:48:09AM +0100, Eric Auger wrote: > Hi Peter, Hi, Eric, > > On 12/8/22 00:49, Peter Xu wrote: > > Hi, Eric, > > > > On Wed, Dec 07, 2022 at 02:36:44PM +0100, Eric Auger wrote: > >> When assigning VFIO devices protected by a virtio-iommu we need to replay > >> the mappin

Re: [PATCH 1/4] coroutine: Clean up superfluous inclusion of qemu/coroutine.h

Probably because block layer, aio.h, and coroutine_int.h header files already include "qemu/coroutine.h"? Reviewed-by: Stefan Hajnoczi

Re: [PATCH 2/4] coroutine: Move coroutine_fn to qemu/osdep.h, trim includes

On Thu, 8 Dec 2022 at 09:25, Markus Armbruster wrote: > > block/block-hmp-cmds.h and qemu/co-shared-resource.h use coroutine_fn > without including qemu/coroutine.h. They compile only if it's already > included from elsewhere. > > I could fix that, but pulling in qemu/coroutine.h and everything i

Re: [PATCH 3/4] coroutine: Clean up superfluous inclusion of qemu/lockable.h

Reviewed-by: Stefan Hajnoczi

Re: [PATCH 4/4] coroutine: Break inclusion loop

Reviewed-by: Stefan Hajnoczi

CVMSEG Emulation

In userspace emulation how do I make a set of addresses always valid and initialized to 0 even though the process does not map it in? In particular I want to map

[RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR

From: Christoph Müllner Setting flags using OR might work, but is not optimal for a couple of reasons: * No way grep for stores to the field MEM_IDX. * The return value of cpu_mmu_index() is not masked (not a real problem as long as cpu_mmu_index() returns only valid values). * If the offset of

[PATCH-for-8.0 v2 0/4] target/cpu: System/User cleanups around hwaddr/vaddr

We are not supposed to use the 'hwaddr' type on user emulation. This series is a preparatory cleanup before few refactors to isolate further System vs User code. Since v1: - only restrict SavedIOTLB in header (Alex) - convert insert/remove_breakpoint implementations (Peter) Philippe Mathieu-Daud

[PATCH-for-8.0 v2 1/4] cputlb: Restrict SavedIOTLB to system emulation

Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 6 -- 1 file changed, 4 insertions(+), 2 d

[PATCH-for-8.0 v2 2/4] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API

Both insert/remove_breakpoint() handlers are used in system and user emulation. We can not use the 'hwaddr' type on user emulation, we have to use 'vaddr' which is defined as "wide enough to contain any #target_ulong virtual address". gdbstub.c doesn't require to include "exec/hwaddr.h" anymore.

[PATCH-for-8.0 v2 3/4] target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu

The 'hwaddr' type is only available / meaningful on system emulation. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.h| 2 +- target/cris/cpu.h | 3 +-- target/hppa/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/nios2/cpu.h| 2 +- target/openrisc/cpu.h | 3 ++- ta

[PATCH-for-8.0 v2 4/4] target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard

Commit caac44a52a ("target/sparc: Make sparc_cpu_tlb_fill sysemu only") restricted mmu_helper.c to system emulation. Checking whether CONFIG_USER_ONLY is defined is now pointless. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/mmu_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --g

Re: [PATCH-for-8.0 v2 0/4] target/cpu: System/User cleanups around hwaddr/vaddr

On 12/8/22 09:35, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (4): cputlb: Restrict SavedIOTLB to system emulation gdbstub: Use vaddr type for generic insert/remove_breakpoint() API target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu target/sparc/sysemu: Remove

[PATCH] mailmap: Fix Stefan Weil author email

Fix authorship of commits 266aaedc37~..ac14949821. See commit 3bd2608db7 ("maint: Add .mailmap entries for patches claiming list authorship") for rationale. Signed-off-by: Philippe Mathieu-Daudé --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 35dddbe27b

Re: [PATCH-for-8.0 v2 2/4] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API

Philippe Mathieu-Daudé writes: > Both insert/remove_breakpoint() handlers are used in system and > user emulation. We can not use the 'hwaddr' type on user emulation, > we have to use 'vaddr' which is defined as "wide enough to contain > any #target_ulong virtual address". > > gdbstub.c doesn't r

Re: [RFC PATCH] migration: reduce time of loading non-iterable vmstate

On Thu, Dec 08, 2022 at 10:39:11PM +0800, Chuang Xu wrote: > > On 2022/12/8 上午6:08, Peter Xu wrote: > > On Thu, Dec 08, 2022 at 12:07:03AM +0800, Chuang Xu wrote: > > > On 2022/12/6 上午12:28, Peter Xu wrote: > > > > Chuang, > > > > > > > > No worry on the delay; you're faster than when I read your

Re: [SeaBIOS] Re: [PATCH 4/4] be less conservative with the 64bit pci io window

On Wed, 23 Nov 2022 11:25:08 +0100 Gerd Hoffmann wrote: > On Tue, Nov 22, 2022 at 01:43:16PM -0500, Kevin O'Connor wrote: > > On Mon, Nov 21, 2022 at 11:32:13AM +0100, Gerd Hoffmann wrote: > > > Current seabios code will only enable and use the 64bit pci io window in > > > case it runs out of s

Re: [PATCH v4 0/2] Add OCP extended log to nvme QEMU

ping. Is the solution to the guid constant ok? Best On Fri, Nov 25, 2022 at 10:48:06AM +0100, Joel Granados wrote: > The motivation and description are contained in the last patch in this set. > Will copy paste it here for convenience: > > In order to evaluate write amplification factor (WA

[RFC PATCH-for-8.0] hw: Avoid using inlined functions with external linkage

When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)") and building with -Wall we get: hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline] hw/arm/smmu-common.h:170:1: not

[PATCH] scripts/archive-source: Use more portable argument with tar command

When using the archive-source.sh script on Darwin we get: tar: Option --concatenate is not supported Usage: List:tar -tf Extract: tar -xf Create: tar -cf [filenames...] Help:tar --help Replace the long argument added by commit 8fc76176f6 ("scripts: use git-archive

Re: [RFC PATCH-for-8.0] hw: Avoid using inlined functions with external linkage

On Thu, 8 Dec 2022 at 16:11, Philippe Mathieu-Daudé wrote: > > When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)") > and building with -Wall we get: > > hw/arm/smmu-common.c:173:33: warning: static function > 'smmu_hash_remove_by_asid_iova' is used in an inline function with e

Re: [PATCH] scripts/archive-source: Use more portable argument with tar command

On Thu, 8 Dec 2022 at 16:21, Philippe Mathieu-Daudé wrote: > > When using the archive-source.sh script on Darwin we get: > > tar: Option --concatenate is not supported > Usage: > List:tar -tf > Extract: tar -xf > Create: tar -cf [filenames...] > Help:tar --help > >

Re: [PATCH qemu.git 0/1] hw/arm/virt: add 2x sp804 timer

Peter, This patch adds timer peripherals to the arm-virt machine.>> Is there a reason you can't use the CPU's built-in generic timer device ? That is what typical guest code does on this system. I'm a bit reluctant to add more devices to the virt board because over time it gradually gets increa

Re: [PATCH qemu.git 0/1] hw/arm/virt: add 2x sp804 timer

On Thu, 8 Dec 2022 at 16:59, Axel Heider wrote: > > Peter, > > >> This patch adds timer peripherals to the arm-virt machine.>> > > Is there a reason you can't use the CPU's built-in generic timer > > device ? That is what typical guest code does on this system. > > I'm a bit reluctant to add more

Re: [PATCH] scripts/archive-source: Use more portable argument with tar command

Philippe Mathieu-Daudé writes: > When using the archive-source.sh script on Darwin we get: > > tar: Option --concatenate is not supported > Usage: > List:tar -tf > Extract: tar -xf > Create: tar -cf [filenames...] > Help:tar --help > > Replace the long argument a

Re: [PATCH] scripts/archive-source: Use more portable argument with tar command

On Thu, Dec 08, 2022 at 05:20:51PM +0100, Philippe Mathieu-Daudé wrote: > When using the archive-source.sh script on Darwin we get: > > tar: Option --concatenate is not supported > Usage: > List:tar -tf > Extract: tar -xf > Create: tar -cf [filenames...] > Help:tar

Re: [PATCH qemu.git 0/1] hw/arm/virt: add 2x sp804 timer

Peter, For the seL4 specific case, this is currently not possible in the standard configuration. It's only exposed for a special debug and benchmarking configuration. It's not clear to me what you mean here -- the generic timer in the CPU exists in all configurations, so there should be no ob

Re: [PATCH 1/4] coroutine: Clean up superfluous inclusion of qemu/coroutine.h

Stefan Hajnoczi writes: > Probably because block layer, aio.h, and coroutine_int.h header files > already include "qemu/coroutine.h"? Mostly, but not always. For instance, crypto/block-luks-priv.h compiles fine without it, and doesn't include it after this patch. > Reviewed-by: Stefan Hajnoczi

Re: [PATCH] scripts/archive-source: Use more portable argument with tar command

On 8/12/22 18:15, Daniel P. Berrangé wrote: On Thu, Dec 08, 2022 at 05:20:51PM +0100, Philippe Mathieu-Daudé wrote: When using the archive-source.sh script on Darwin we get: tar: Option --concatenate is not supported Usage: List:tar -tf Extract: tar -xf Create: tar -

Re: [PATCH v2 3/3] hw/nvme: fix missing cq eventidx update

On Thu, Dec 08, 2022 at 01:26:42PM +0100, Klaus Jensen wrote: > From: Klaus Jensen > > Prior to reading the shadow doorbell cq head, we have to update the > eventidx. Otherwise, we risk that the driver will skip an mmio doorbell > write. This happens on riscv64, as reported by Guenter. > > Addin

Re: [PATCH] FreeBSD: Upgrade to 12.4 release

On Thu, Dec 8, 2022 at 12:47 AM Philippe Mathieu-Daudé wrote: > On 8/12/22 07:52, Brad Smith wrote: > > FreeBSD: Upgrade to 12.4 release > > > > Signed-off-by: Brad Smith > > --- > > .gitlab-ci.d/cirrus.yml | 2 +- > > tests/vm/freebsd| 4 ++-- > > 2 files changed, 3 insertions(+), 3

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

On Thu, Dec 08, 2022 at 09:08:12AM +0100, Klaus Jensen wrote: > On Dec 8 08:16, Klaus Jensen wrote: > > On Dec 7 09:49, Guenter Roeck wrote: > > > Hi, > > > > > > On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote: > > > > Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec

Re: [PATCH 3/6] hw/i2c: Allwinner TWI/I2C Emulation

Hi Niek, On Wed, Dec 7, 2022 at 11:06 PM Niek Linnenbank wrote: > > Hi Strahinja, > > On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic > wrote: >> >> This patch implements Allwinner TWI/I2C controller emulation. Only >> master-mode functionality is implemented. >> >> The SPL boot for Cubieboa

Re: [PATCH 6/6] hw/arm: Allwinner A10 enable SPL load from MMC

On Wed, Dec 7, 2022 at 11:39 PM Niek Linnenbank wrote: > > Hi Strahinja, > > > On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic > wrote: >> >> This patch enables copying of SPL from MMC if `-kernel` parameter is not >> passed when starting QEMU. SPL is copied to SRAM_A. >> >> The approach is r

Re: [PATCH 0/6] Enable Cubieboard A10 boot SPL from SD card

Hi Niek, On Wed, Dec 7, 2022 at 9:25 PM Niek Linnenbank wrote: > > Hello Strahinja, > > Thanks for contribution these patches, and also taking the H3 into account :-) Thank you for looking into these patches and all of the comments. I will try to submit V2 of this patch set in the following days

Re: [PATCH v3 1/2] hw/nvme: Implement shadow doorbell buffer support

On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote: > > > > A cq head doorbell mmio is skipped... And it is not the fault of the > > kernel. The kernel is in it's good right to skip the mmio since the cq > > eventidx is not properly updated. > > > > Adding that and it boots properly on

  1   2   >