Am 7. Dezember 2022 15:29:00 UTC schrieb Mark Cave-Ayland
:
>On 06/12/2022 20:06, Thomas Huth wrote:
>
>> The only code that is really, really target dependent is the apic-related
>> code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
>> folder (renamed to rtc_apic_poli
On 7/12/22 15:33, Eric Auger wrote:
On 12/7/22 15:09, Stefan Hajnoczi wrote:
On Wed, 7 Dec 2022 at 08:31, Eric Auger wrote:
On 12/7/22 14:24, Eric Auger wrote:
Initialize r0-3 to avoid compilation errors when
-Werror=maybe-uninitialized is used
../target/i386/ops_sse.h: In function ‘helper_v
Hi,
On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote:
>
> Unmap the existing guest mappings when memory attribute is changed
> between shared and private. This is needed because shared pages and
> private pages are from different backends, unmapping existing ones
> gives a chance for page fault han
Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in
case of reset") added the SavedIOTLB structure -- which is
system emulation specific -- in the generic CPUState structure.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cputlb.c| 4 ++--
include/hw/core/cpu.h | 6 --
2 fi
Commit caac44a52a ("target/sparc: Make sparc_cpu_tlb_fill sysemu
only") restricted mmu_helper.c to system emulation. Checking
whether CONFIG_USER_ONLY is defined is now pointless.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/mmu_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --g
We are not supposed to use hwaddr on user emulation.
This series is a - trivial - preparatory cleanup before
few refactors to isolate further System vs User code.
Philippe Mathieu-Daudé (4):
cputlb: Restrict SavedIOTLB to system emulation
gdbstub: Use vaddr type for generic insert/remove_brea
cpu_get_phys_page_debug() is a system-emulation specific handler.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.h| 2 +-
target/cris/cpu.h | 3 +--
target/hppa/cpu.h | 2 +-
target/m68k/cpu.h | 2 +-
target/nios2/cpu.h| 2 +-
target/openrisc/cpu.h | 3 ++-
target
Both insert/remove_breakpoint() handlers are used in system and
user emulation. We can not use the 'hwaddr' type on user emulation,
we have to use 'vaddr' which is defined as "wide enough to contain
any #target_ulong virtual address".
Signed-off-by: Philippe Mathieu-Daudé
---
gdbstub/internals.h
On 07/12/2022 16:20, Bernhard Beschow wrote:
Am 7. Dezember 2022 15:29:00 UTC schrieb Mark Cave-Ayland
:
On 06/12/2022 20:06, Thomas Huth wrote:
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i3
Hi,
On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote:
> Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3)
> and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13
> in NVMe Spec 1.3). For queues created before the Doorbell Buffer Config
> command, t
Philippe Mathieu-Daudé writes:
> Both insert/remove_breakpoint() handlers are used in system and
> user emulation. We can not use the 'hwaddr' type on user emulation,
> we have to use 'vaddr' which is defined as "wide enough to contain
> any #target_ulong virtual address".
>
> Signed-off-by: Phil
On 7/12/22 19:08, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
Both insert/remove_breakpoint() handlers are used in system and
user emulation. We can not use the 'hwaddr' type on user emulation,
we have to use 'vaddr' which is defined as "wide enough to contain
any #target_ulong virtual
On 12/7/22 17:55, Philippe Mathieu-Daudé wrote:
> On 7/12/22 15:33, Eric Auger wrote:
>> On 12/7/22 15:09, Stefan Hajnoczi wrote:
>>> On Wed, 7 Dec 2022 at 08:31, Eric Auger wrote:
On 12/7/22 14:24, Eric Auger wrote:
> Initialize r0-3 to avoid compilation errors when
> -Werror=mayb
On 12/7/22 10:08, Eric Auger wrote:
On 12/7/22 16:55, Stefan Hajnoczi wrote:
I am using this configure cmd line:
./configure --prefix=/usr --sysconfdir=/etc --libexecdir=/usr/lib/qemu
--target-list=x86_64-softmmu --docdir=/usr/share/doc/qemu --enable-kvm
--extra-cflags=-O --enable-trace-backend
On Wed, 7 Dec 2022 at 17:42, Philippe Mathieu-Daudé wrote:
>
> Both insert/remove_breakpoint() handlers are used in system and
> user emulation. We can not use the 'hwaddr' type on user emulation,
> we have to use 'vaddr' which is defined as "wide enough to contain
> any #target_ulong virtual addr
On 7/12/22 19:23, Peter Maydell wrote:
On Wed, 7 Dec 2022 at 17:42, Philippe Mathieu-Daudé wrote:
Both insert/remove_breakpoint() handlers are used in system and
user emulation. We can not use the 'hwaddr' type on user emulation,
we have to use 'vaddr' which is defined as "wide enough to conta
Current 256KB is not enough for some real cases. As a possible solution
limit can be chosen to be the same as libvirt (10MB)
Signed-off-by: Maksim Davydov
---
python/qemu/qmp/qmp_client.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/python/qemu/qmp/qmp_client.py b/pyt
To control that creating new machine type doesn't affect the previous
types (their compat_props) and to check complex compat_props inheritance
we need qmp command to print machine type compatible properties.
This patch adds the ability to get list of all the compat_props of the
corresponding suppor
This script is necessary to choose the best machine type in the
appropriate cases. Also we have to check compat_props of the old MT
after changes to be sure that they haven't broken old the MT. For
example, pc_compat_3_1 of pc-q35-3.1 has Icelake-Client which was
removed in March.
v4 -> v3:
* incr
This script run QEMU to obtain compat_props of machines and default
values of different types and produce appropriate table. This table
can be used to compare machine types to choose the most suitable
machine. Also this table in json or csv format should be used to check that
new machine doesn't af
qmp_qom_list_properties can print default values if they are available
as qmp_device_list_properties does, because both of them use the
ObjectPropertyInfo structure with default_value field. This can be useful
when working with "not device" types.
Signed-off-by: Maksim Davydov
Reviewed-by: Vladim
Hi,
On 12/7/22 19:23, Richard Henderson wrote:
> On 12/7/22 10:08, Eric Auger wrote:
>> On 12/7/22 16:55, Stefan Hajnoczi wrote:
I am using this configure cmd line:
./configure --prefix=/usr --sysconfdir=/etc --libexecdir=/usr/lib/qemu
--target-list=x86_64-softmmu --docdir=/usr
Am 07.12.22 um 19:22 schrieb Eric Auger:
On 12/7/22 17:55, Philippe Mathieu-Daudé wrote:
On 7/12/22 15:33, Eric Auger wrote:
On 12/7/22 15:09, Stefan Hajnoczi wrote:
On Wed, 7 Dec 2022 at 08:31, Eric Auger wrote:
On 12/7/22 14:24, Eric Auger wrote:
Initialize r0-3 to avoid compilation erro
On Wed, 7 Dec 2022 at 14:11, Stefan Weil wrote:
>
> Am 07.12.22 um 19:22 schrieb Eric Auger:
> >
> > On 12/7/22 17:55, Philippe Mathieu-Daudé wrote:
> >> On 7/12/22 15:33, Eric Auger wrote:
> >>> On 12/7/22 15:09, Stefan Hajnoczi wrote:
> On Wed, 7 Dec 2022 at 08:31, Eric Auger wrote:
>
once, but there remain 193313 unique
warnings for the QEMU code (see
https://qemu.weilnetz.de/test/warnings-20221207.txt). Here is a list of
all kinds of warnings sorted by frequency:
1 -Wkeyword-macro
1 -Wundeclared-selector
1 -Wunreachable-code-loop-increment
1 -Wunused-but-set-para
Hi Stefan,
On 12/7/22 20:59, Stefan Hajnoczi wrote:
> On Wed, 7 Dec 2022 at 14:11, Stefan Weil wrote:
>> Am 07.12.22 um 19:22 schrieb Eric Auger:
>>> On 12/7/22 17:55, Philippe Mathieu-Daudé wrote:
On 7/12/22 15:33, Eric Auger wrote:
> On 12/7/22 15:09, Stefan Hajnoczi wrote:
>> On W
On Wed, 7 Dec 2022 at 18:27, Philippe Mathieu-Daudé wrote:
>
> On 7/12/22 19:23, Peter Maydell wrote:
> > On Wed, 7 Dec 2022 at 17:42, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Both insert/remove_breakpoint() handlers are used in system and
> >> user emulation. We can not use the 'hwaddr' type
Hi Stefan,
On 12/7/22 20:11, Stefan Weil via wrote:
> Am 07.12.22 um 19:22 schrieb Eric Auger:
>>
>> On 12/7/22 17:55, Philippe Mathieu-Daudé wrote:
>>> On 7/12/22 15:33, Eric Auger wrote:
On 12/7/22 15:09, Stefan Hajnoczi wrote:
> On Wed, 7 Dec 2022 at 08:31, Eric Auger
> wrote:
>>>
Hello Strahinja,
Thanks for contribution these patches, and also taking the H3 into account
:-)
I've ran the avocado based acceptance tests for both boards and got these
results:
$ ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes
./build/tests/venv/bin/avocado --show=app,console run
On Wed, 7 Dec 2022 at 18:44, Eric Auger wrote:
> On 12/7/22 19:23, Richard Henderson wrote:
> > Adding -Wall is not standard, nor all the other -W that you are
> > adding. I think you should not be surprised that you run into problems.
> OK that's a useful indication. I used to have this configur
Hi Peter,
On 12/7/22 21:28, Peter Maydell wrote:
> On Wed, 7 Dec 2022 at 18:44, Eric Auger wrote:
>> On 12/7/22 19:23, Richard Henderson wrote:
>>> Adding -Wall is not standard, nor all the other -W that you are
>>> adding. I think you should not be surprised that you run into problems.
>> OK th
On Wed, 2022-12-07 at 08:55 -0600, Richard Henderson wrote:
> On 12/7/22 01:45, Thomas Huth wrote:
> > On 06/12/2022 23.22, Richard Henderson wrote:
> > > On 12/6/22 13:29, Ilya Leoshkevich wrote:
> > > > This change doesn't seem to affect that, but what is the
> > > > minimum
> > > > supported s39
Am 07.12.22 um 21:40 schrieb Ilya Leoshkevich:
On Wed, 2022-12-07 at 08:55 -0600, Richard Henderson wrote:
On 12/7/22 01:45, Thomas Huth wrote:
On 06/12/2022 23.22, Richard Henderson wrote:
On 12/6/22 13:29, Ilya Leoshkevich wrote:
This change doesn't seem to affect that, but what is the
m
On Thu, Sep 01, 2022 at 08:23:52PM +0200, Paolo Bonzini wrote:
> From: John Millikin
>
> When a SCSI command is received from the guest, the CDB length implied
> by the first byte might exceed the number of bytes the guest sent. In
> this case scsi_req_new() will read uninitialized data, causing
Hi Strahinja,
On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch implements Allwinner TWI/I2C controller emulation. Only
> master-mode functionality is implemented.
>
> The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this
>
On Thu, Dec 08, 2022 at 12:07:03AM +0800, Chuang Xu wrote:
>
> On 2022/12/6 上午12:28, Peter Xu wrote:
> > Chuang,
> >
> > No worry on the delay; you're faster than when I read yours. :)
> >
> > On Mon, Dec 05, 2022 at 02:56:15PM +0800, Chuang Xu wrote:
> > > > As a start, maybe you can try with p
On Tue, 2022-12-06 at 16:22 -0600, Richard Henderson wrote:
> On 12/6/22 13:29, Ilya Leoshkevich wrote:
> > On Thu, Dec 01, 2022 at 10:51:49PM -0800, Richard Henderson wrote:
> > > This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
> > > several follow-up patches. The primary motiva
Hi Strahinja,
On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> During SPL boot several DRAM Controller registers are used. Most
> important registers are those related to DRAM initialization and
> calibration, where SPL initiates process and waits until
Hi Strahinja,
On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> During SPL boot several Clock Controller Module (CCM) registers are
> read, most important are PLL and Tuning, as well as divisor registers.
>
> This patch adds these registers and initialize
Hi Strahinja,
On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch enables copying of SPL from MMC if `-kernel` parameter is not
> passed when starting QEMU. SPL is copied to SRAM_A.
>
> The approach is reused from Allwinner H3 implementation.
>
Both ACPI_PIIX4 (directly) and ACPI_ICH9 (indirectly) require ACPI to be
selected. Require it for VT82C686's ACPI controller too for consistency.
Signed-off-by: Bernhard Beschow
---
hw/isa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 0a6a04947
ich9_lpc_realize() uses apm_init() and ich9_smbus_realize() uses
pm_smbus_init(), so both APM and ACPI_SMBUS are provided by the device
models managed by ACPI_ICH9.
Signed-off-by: Bernhard Beschow
---
hw/acpi/Kconfig | 2 ++
hw/i386/Kconfig | 1 -
hw/isa/Kconfig | 1 -
3 files changed, 2 insert
Although the ICH9 ACPI controller may currently be tied to x86 it
doesn't have to. Furthermore, the source files this configuration switch
manages contain a '9', so this name fits more.
Signed-off-by: Bernhard Beschow
---
hw/acpi/Kconfig | 2 +-
hw/acpi/meson.build | 2 +-
hw/i2c/meson.build
This small series establishes consistency between ICH9, PIIX4 and VT82C686 ACPI
controllers to 1/ depend on ACPI and 2/ to select ACPI_SMBUS and APM since the
latter are provided by the device models.
Due to the PIIX4 cleanup PEGASOS2's dependency can be reduced to just ACPI,
eliminating 9 compila
Removes the following dependencies from ppc-softmmu:
- CONFIG_ACPI_CPU_HOTPLUG
- CONFIG_ACPI_CXL
- CONFIG_ACPI_HMAT
- CONFIG_ACPI_MEMORY_HOTPLUG
- CONFIG_ACPI_NVDIMM
- CONFIG_ACPI_PCIHP
- CONFIG_ACPI_PIIX4
- CONFIG_ACPI_X86
- CONFIG_MEM_DEVICE
Signed-off-by: Bernhard Beschow
---
hw/ppc/Kconfig |
piix4_pm_realize() uses apm_init() and pm_smbus_init(), so both APM and
ACPI_SMBUS are provided by the device model managed by ACPI_PIIX4.
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 2 --
hw/acpi/Kconfig | 2 ++
hw/i386/Kconfig
Hi, Eric,
On Wed, Dec 07, 2022 at 02:36:44PM +0100, Eric Auger wrote:
> When assigning VFIO devices protected by a virtio-iommu we need to replay
> the mappings when adding a new IOMMU MR and when attaching a device to
> a domain. While we do a "remap" we currently fail to first unmap the
> existi
On Fri, Dec 02, 2022 at 02:13:46PM +0800, Chao Peng wrote:
> A KVM_MEM_PRIVATE memslot can include both fd-based private memory and
> hva-based shared memory. Architecture code (like TDX code) can tell
> whether the on-going fault is private or not. This patch adds a
> 'is_private' field to kvm_pag
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fifth and final planned release candidate for the QEMU 7.2 release. This
release is meant for testing purposes and should not be used in a
production environment.
http://download.qemu-project.org/qemu-7.2.0-rc4.tar.
On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote:
>
> The htimedelta[h] CSR has impact on the VS timer comparison so we
> should call riscv_timer_write_timecmp() whenever htimedelta changes.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel
> Reviewed-by:
On Wed, Dec 7, 2022 at 7:05 PM Bin Meng wrote:
>
> There are 2 paths in helper_sret() and the same mstatus update codes
> are replicated. Extract the common parts to simplify it a little bit.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> target/riscv/op_helper.
On Wed, Dec 7, 2022 at 7:11 PM Bin Meng wrote:
>
> Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
> leaving M-mode.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> target/riscv/op_helper.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff
On Wed, Dec 7, 2022 at 8:06 PM Bin Meng wrote:
>
> The realize() callback has an errp for us to propagate the error up.
> While we are here, corret the wrong multi-line comment format.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v2:
> - new patch:
On Wed, Dec 7, 2022 at 7:11 PM Bin Meng wrote:
>
> Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
> leaving M-mode.
>
> Signed-off-by: Bin Meng
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> ---
>
> target/riscv/op_helper.c | 6 ++
> 1 file changed, 6 insertions(+)
Some CPUID leaves have meaningful subleaf index. Print the subleaf info
in feature_word_description for CPUID features.
Signed-off-by: Xiaoyao Li
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/targe
KVM only allows userspace to access legal number of MSR_IA32_RTIT_ADDRn,
which is enumrated by guest's CPUID(0x14,0x1):EAX[2:0], i.e.,
env->features[FEAT_14_1_EAX] & INTEL_PT_ADDR_RANGES_NUM_MASK
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.h | 2 ++
target/i386/kvm/kvm.c | 8
2 fi
Bit[2:0] of CPUID.14H_01H:EAX stands as a whole for the number of INTEL
PT ADDR RANGES. For unsupported value that exceeds what KVM reports,
report it as a whole in mark_unavailable_features() as well.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 9 -
1 file changed, 8 insertions(+)
Historically the Intel PT feature set reported from ICX silicon
was chosen as the fixed feature set for Intel PT. If want to enable
and expose INTEL-PT to guest, the supported Intel PT reported by host
must cover the fixed feature set, which are named with MINIMAL in
INTEL_PT_MINIMAL_EBX and INTEL_
Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of
address ranges for INTEL-PT.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8d95202f6a42..9ae36639d380 100644
---
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
set (from ICX) for any CPU model on any host. This truly breaks the PT
exposure on Intel SPR platform because SPR has less supported bitmap of
CPUID(0x14,
CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and
capability of Intel PT.
Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX,
and complete FEAT_14_0_ECX. Thus all the features of Intel PT can be
expanded when "-cpu host/max" and can be configured in named CPU model.
For IceLake-server, it's just the same as using the default PT
feature set since the default one is exact taken from ICX.
For Snowridge, define it according to real SNR silicon capabilities.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 18 ++
1 file changed, 18 insertions(+
Initial virtualization of Intel PT was added by making it as fixed
feature set of ICX's capabilities. However, it breaks the Intel PT exposure
on SPR machine because SPR has less PT capabilities of
CPUID(0x14,1):EBX[15:0].
This series aims to make Intel PT configurable that named CPU model can
def
On 8/12/22 00:12, Bernhard Beschow wrote:
Although the ICH9 ACPI controller may currently be tied to x86 it
doesn't have to. Furthermore, the source files this configuration switch
manages contain a '9', so this name fits more.
Signed-off-by: Bernhard Beschow
---
hw/acpi/Kconfig | 2 +-
FreeBSD: Upgrade to 12.4 release
Signed-off-by: Brad Smith
---
.gitlab-ci.d/cirrus.yml | 2 +-
tests/vm/freebsd| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml
index 634a73a742..785b163aa6 100644
--- a/.gitlab-ci.d
Am 12.01.21 um 17:57 schrieb Peter Maydell:
[...]
diff --git a/docs/meson.build b/docs/meson.build
index fae9849b79b..bb14eaebd3b 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -46,19 +46,11 @@ if build_docs
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
On Dec 7 09:49, Guenter Roeck wrote:
> Hi,
>
> On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote:
> > Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3)
> > and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13
> > in NVMe Spec 1.3). For queues crea
AVX-NE-CONVERT is a new set of instructions which can convert low
precision floating point like BF16/FP16 to high precision floating point
FP32, as well as convert FP32 elements to BF16. This instruction allows
the platform to have improved AI capabilities and better compatibility.
The bit definit
AVX-IFMA is a new instruction in the latest Intel platform Sierra
Forest. This instruction packed multiplies unsigned 52-bit integers and
adds the low/high 52-bit products to Qword Accumulators.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 23]
Add CPUID definition for AVX-IFMA.
Signed-off-by:
Latest Intel platform Granite Rapids has introduced a new instruction -
PREFETCHIT0/1, which moves code to memory (cache) closer to the
processor depending on specific hints.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 14]
Add CPUID definition for PREFETCHIT0/1.
Signed-off-by: Jiaxi Chen
--
AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform
Sierra Forest, aims for the platform to have superior AI capabilities.
This instruction multiplies the individual bytes of two unsigned or
unsigned source operands, then adds and accumulates the results into the
destination dwo
Latest Intel platform Granite Rapids has introduced a new instruction -
AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
the results into a packed single precision tile. AMX-FP16 adds FP16
capability and allows a FP16 GPU trained model to run faster without
loss of accuracy o
CMPccXADD is a new set of instructions in the latest Intel platform
Sierra Forest. This new instruction set includes a semaphore operation
that can compare and add the operands if condition is met, which can
improve database performance.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 7]
Add CPUI
Latest Intel platform Granite Rapids/Sierra Forest has introduced below
new instructions and CPUIDs:
- CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
- AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
- AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
- AVX-NE-CONVERT
On Wed, Dec 7, 2022 at 5:00 PM Eugenio Perez Martin wrote:
>
> On Tue, Dec 6, 2022 at 8:08 AM Jason Wang wrote:
> >
> > On Tue, Dec 6, 2022 at 1:04 AM Eugenio Pérez wrote:
> > >
> > > The state of the descriptors (avail or used) may not be recoverable just
> > > looking at the guest memory. Out
On Wed, Nov 30, 2022 at 1:33 PM Cindy Lu wrote:
>
> Skip the check in vhost_vdpa_listener_skipped_section() while
> MR is IOMMU, Move this check to vhost_vdpa_iommu_map_notify()
>
> Signed-off-by: Cindy Lu
> ---
> hw/virtio/vhost-vdpa.c | 21 ++---
> 1 file changed, 14 insertion
On 8/12/22 07:52, Brad Smith wrote:
FreeBSD: Upgrade to 12.4 release
Signed-off-by: Brad Smith
---
.gitlab-ci.d/cirrus.yml | 2 +-
tests/vm/freebsd| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml
index 634a73a
Hi Peter,
On 12/8/22 00:49, Peter Xu wrote:
> Hi, Eric,
>
> On Wed, Dec 07, 2022 at 02:36:44PM +0100, Eric Auger wrote:
>> When assigning VFIO devices protected by a virtio-iommu we need to replay
>> the mappings when adding a new IOMMU MR and when attaching a device to
>> a domain. While we do a
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