On Thu, 1 Dec 2022 at 11:50, Klaus Jensen wrote:
>
> From: Klaus Jensen
>
> Hi,
>
> The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
>
> Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500)
>
> are available in the Git repository at:
>
> git://git.infradead.or
On Fri, 2 Dec 2022 at 12:25, Thomas Huth wrote:
>
> On 01/12/2022 12.55, Peter Maydell wrote:
> > On Wed, 30 Nov 2022 at 11:16, Thomas Huth wrote:
> >> #define QEMU_ARM_POWERCTL_RET_SUCCESS QEMU_PSCI_RET_SUCCESS
> >> #define QEMU_ARM_POWERCTL_INVALID_PARAM QEMU_PSCI_RET_INVALID_PARAMS
> >>
On Sun, 4 Dec 2022 at 00:04, Richard Henderson
wrote:
>
> Separately control b_lto without --enable-cfi.
> Also add --disable-lto for completeness.
Before this patch, CFI defaults to false and therefore LTO
also defaults to false. After this patch, LTO defaults to
true even if CFI is false. Inten
This aligns PIIX4 with PIIX3.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-30-shen...@gmail.com>
---
hw/isa/piix4.c | 44
hw/mips/malta.c | 6 --
2 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/hw/isa/piix4.
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-32-shen...@gmail.com>
---
hw/isa/piix4.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
Prefixing with "piix4_" makes the method distinguishable from its
PIIX3 counterpart upon merging and also complies more with QEMU
conventions.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-36-shen...@gmail.com>
---
hw/isa/piix4.c | 5 +++--
1 file changed, 3 insertions(+), 2
Aligns the code with PIIX3 such that PIIXState can be used in PIIX4,
too.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-33-shen...@gmail.com>
---
hw/isa/Kconfig | 2 +-
hw/isa/piix4.c | 30 +++---
hw/mips/Kconfig | 1 +
hw/mips/malta.c | 11 +++
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-21-shen...@gmail.com>
---
hw/isa/piix3.c| 8
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 in
From: Philippe Mathieu-Daudé
The PIIX4 PCI-ISA bridge function is always located at 10:0.
Since we want to re-use its address, add the PIIX4_PCI_DEVFN
definition.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221027204720.33611-2-phi...@linaro.org>
---
hw/mips/malta.c | 4 +++-
1 file c
Use the newly introduced TYPE_PROXY_PIC which allows for wiring
up devices in the southbridge where the virtualization technology used
(KVM, TCG, Xen) is not yet known.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-16-shen...@gmail.com>
---
hw/i386/Kconfig | 1
The additional prefix aligns the function name with both other
piix3-internal functions as well as QEMU conventions. Furthermore, it
will help to distinguish the function from its PIIX4 counterpart once
merged.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2022
Now that PIIX3 contains the new isa-pic, it is possible to instantiate
PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to
the ISA bus in its realize method which requires the interrupt
controller to provide fully populated qemu_irqs. This is the case for
isa-pic even though th
Now that the RTC is created as part of the southbridges it doesn't need
to be an out-parameter any longer.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Message-Id: <20221022150508.26830-12-shen...@gmail.com>
---
hw/i386/pc.c | 12 ++--
hw/i386/pc_piix.c| 2 +-
Speeds up PIIX4 which resolves an old TODO.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-41-shen...@gmail.com>
---
hw/isa/piix.c | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 3d1659e5fd..d0
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-23-shen...@gmail.com>
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index a811a9bdab..e99622699a 100644
--- a/hw/isa/
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-22-shen...@gmail.com>
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 7ee706243a..a811a9bdab 100644
--- a/hw/isa/
Having a common base class allows for substituting PIIX3 with PIIX4
and vice versa. Moreover, it makes PIIX4 implement the
acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-42-shen...@gmail.com>
---
hw/isa/piix.c | 53 +++---
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow
Message-Id: <202210221
Just like in the real hardware (and in PIIX4), create the RTC
controllers in the south bridges.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-11-shen...@gmail.com>
---
hw/i386/pc.c | 12 +++-
hw/i386/pc_piix.c | 8
hw/i386/pc_q35
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-35-shen...@gmail.com>
---
hw/isa/piix4.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/i
The power management controller is an integral part of PIIX3 (function
3). So create it as part of the south bridge.
Note that the ACPI function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow
Message-
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-40-shen...@gmail.com>
---
hw/isa/piix.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
di
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-10-shen...@gmail.com>
---
hw/i386/pc_piix.c | 3 ++-
hw/i386/pc_q35.c | 13 +++--
hw/isa/piix4.c| 2 +-
hw/usb/hcd-uhci.c | 16
hw/usb/hcd-uhci.h | 4
5 files ch
Having a proxy PIC allows for ISA PICs to be created and wired up in
southbridges. This is especially useful for PIIX3 for two reasons:
First, the southbridge doesn't need to care about the virtualization
technology used (KVM, TCG, Xen) due to in-IRQs (where devices get
attached) and out-IRQs (whic
The next patches will need to take advantage of it.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Message-Id: <20221022150508.26830-3-shen...@gmail.com>
---
hw/i386/pc_piix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
Now that the base class is used for both PIIX3 and PIIX4, the "3"
became misleading.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-43-shen...@gmail.com>
---
hw/isa/piix.c | 8
include/hw/southbridge/piix.h | 6 ++
2 files changed, 6 insertions(+),
Now that PIIX4 also uses the "proxy-pic", both implementations
can share the same struct.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-34-shen...@gmail.com>
---
hw/isa/piix4.c | 51 +++---
1 file changed, 15 insertions(+), 36 delet
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges and is an extended version of [1]. The motivation is to share as much
code as possible and to bring both device models to feature parity such that
perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc mac
Resolves duplicate code.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-39-shen...@gmail.com>
---
hw/isa/piix.c | 65 +++
1 file changed, 9 insertions(+), 56 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 035f64b9
There is no need for having different names here. Having the same name
further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-38-shen...@gmail.com>
---
hw/isa/piix.c | 4 ++--
1 file changed
Now that the PIIX3 and PIIX4 device models are sufficiently consolidated,
their implementations can be merged into one file for further
consolidation.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-37-shen...@gmail.com>
---
MAINTAINERS| 6 +-
hw/i386/Kconfig
Now that PIIX3 has the PIC integrated, the ACPI controller can be wired
up internally.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-18-shen...@gmail.com>
---
hw/i386/pc_piix.c | 1 -
hw/isa/piix3.c| 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i
This commit marks the finalization of the PIIX3 preparations
to be merged with PIIX4. In particular, PIIXState is prepared
to be reused in piix4.c.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-25-shen...@gmail.com>
---
hw/isa/piix3.c
From: Philippe Mathieu-Daudé
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included valu
Tracking dependencies via Kconfig seems much cleaner.
Note that PIIX4 already depends on ACPI_PIIX4.
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 2 --
hw/mips/Kconfig | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/c
From: Philippe Mathieu-Daudé
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Sorry, the titles should have contained a "v3"...
Am 4. Dezember 2022 19:05:21 UTC schrieb Bernhard Beschow :
>This series consolidates the implementations of the PIIX3 and PIIX4 south
>
>bridges and is an extended version of [1]. The motivation is to share as much
>
>code as possible and to bring
On Sun, Dec 04, 2022 at 11:06:13AM -0500, Stefan Hajnoczi wrote:
> On Thu, 1 Dec 2022 at 11:50, Klaus Jensen wrote:
> >
> > From: Klaus Jensen
> >
> > Hi,
> >
> > The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
> >
> > Update VERSION for v7.2.0-rc3 (2022-11-29 18:15
Hi Strahinja,
On 4/12/22 00:19, Strahinja Jankovic wrote:
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.
Signed-off-by: Strahin
On 4/12/22 20:05, Bernhard Beschow wrote:
Tracking dependencies via Kconfig seems much cleaner.
Note that PIIX4 already depends on ACPI_PIIX4.
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 2 --
hw/mips/Kconfig | 1 +
2 files changed,
On 4/12/22 20:05, Bernhard Beschow wrote:
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-10-shen...@gmail.com>
---
hw/i386/pc_piix.c | 3 ++-
hw/i386/pc_q35.c | 13 +++--
hw/isa/piix4.c| 2 +-
hw/usb/hcd-uhci.c | 16 -
On Sat, 2022-12-03 at 13:23 +, Ani Sinha wrote:
> Debug specific actions can be enabled in bios bits acpi tests by
> passing
> BITS_DEBUG in the environment variable while running the test.
> Document that.
>
> CC: qemu-triv...@nongnu.org
> Signed-off-by: Ani Sinha
> ---
> docs/devel/acpi-bi
On Fri, Dec 2, 2022 at 12:15 AM Bin Meng wrote:
>
> hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
> controllers regardless of how MSI is implemented. msi_nonbroken is
> initialized to true in sifive_plic_realize().
>
> Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote:
>
> hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
> controllers regardless of how MSI is implemented. msi_nonbroken is
> initialized to true in both riscv_aplic_realize() and
> riscv_imsic_realize().
>
> Select MSI_NONBROKEN in RI
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote:
>
> Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
> the IBEX PLIC model was replaced with the SiFive PLIC model in the
> 'opentitan' machine but we forgot the add the dependency there.
>
> Signed-off-by: Bin Meng
Rev
On Fri, Dec 2, 2022 at 12:14 AM Bin Meng wrote:
>
> SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/Kconfig | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> dif
On Fri, Dec 2, 2022 at 12:14 AM Bin Meng wrote:
>
> PLIC is not included in the 'spike' machine.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/spike.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 1
On Fri, Dec 2, 2022 at 12:15 AM Bin Meng wrote:
>
> H-mode has been removed since priv spec 1.10. Drop it.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> include/hw/intc/sifive_plic.h | 1 -
> hw/intc/sifive_plic.c | 1 -
> 2 files changed, 2 deletions(-
On Fri, 2022-12-02 at 19:52 -0500, John Snow wrote:
> A few tiny touchups needed for cutting edge 'flake8' tooling, a minor
> type touchup in iotests, and extending the python tests to cover the
> recently released Python 3.11.
>
> John Snow (3):
> Python: fix flake8 config
> iotests/check: Fi
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On 12/4/22 11:40, Peter Maydell wrote:
On Sun, 4 Dec 2022 at 00:04, Richard Henderson
wrote:
Separately control b_lto without --enable-cfi.
Also add --disable-lto for completeness.
Before this patch, CFI defaults to false and therefore LTO
also defaults to false. After this patch, LTO defaul
`
On Thu, Dec 1, 2022 at 10:59 PM Peter Xu wrote:
>
> On Thu, Dec 01, 2022 at 04:35:48PM +0800, Jason Wang wrote:
> > On Wed, Nov 30, 2022 at 11:17 PM Peter Xu wrote:
> > >
> > > On Wed, Nov 30, 2022 at 02:33:51PM +0800, Jason Wang wrote:
> > > > On Tue, Nov 29, 2022 at 11:57 PM Peter Xu wrote
On Sat, Dec 3, 2022 at 3:38 PM Cindy Lu wrote:
>
> On Thu, 1 Dec 2022 at 16:49, Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 4:11 PM Cindy Lu wrote:
> > >
> > > Some device does not support vhost_send_device_iotlb_msg()
> > > such as vDPA device, which is as expected. So we should not
> > >
On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
>
> It seems not super clear on when iova_tree is used, and why. Add a rich
> comment above iova_tree to track why we needed the iova_tree, and when we
> need it.
>
> Suggested-by: Jason Wang
> Signed-off-by: Peter Xu
> ---
> include/hw/i386/inte
On Thu, Dec 1, 2022 at 5:50 PM Eugenio Perez Martin wrote:
>
> On Thu, Dec 1, 2022 at 9:45 AM Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 3:40 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, Nov 30, 2022 at 7:43 AM Jason Wang wrote:
> > > >
> > > > On Thu, Nov 24, 2022 at 11:52 PM
On Thu, Dec 1, 2022 at 5:29 PM Eugenio Perez Martin wrote:
>
> On Thu, Dec 1, 2022 at 9:39 AM Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 3:07 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, Nov 30, 2022 at 8:02 AM Jason Wang wrote:
> > > >
> > > > On Fri, Nov 25, 2022 at 1:33 AM E
On Mon, Dec 5, 2022 at 2:23 PM Yangming wrote:
>
> Dear all:
>
>
>
> I found a bug of qemu: hot-pluging a vhost-net may cause virtual machine
> crash in following steps:
> 1. Starting a vm without any net device.
> 2. Hot-pluging 70 memory devices.
> 3. Hot-pluging a vhost-net device.
>
>
>
> Aft
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault exception.
At pres
Peter, I'm sorry I didn't reply to your email in time, because I was busy with
other work last week. Here is my latest progress.
On 2022/11/29 上午1:41, Peter Xu wrote:
On Mon, Nov 28, 2022 at 05:42:43PM +0800, Chuang Xu wrote:
On 2022/11/25 上午12:40, Peter Xu wrote:
On Fri, Nov 18, 2022 at 04:36
On 5/12/22 07:37, Jason Wang wrote:
On Mon, Dec 5, 2022 at 2:23 PM Yangming wrote:
Dear all:
I found a bug of qemu: hot-pluging a vhost-net may cause virtual machine crash
in following steps:
1. Starting a vm without any net device.
2. Hot-pluging 70 memory devices.
3. Hot-pluging a vhost-
On 2/12/22 11:25, Song Gao wrote:
The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221202
for you to fe
Hi
On Fri, Dec 2, 2022 at 1:51 PM Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> The vnc-display-test is failing on Darwin:
>
> tests/qtest/vnc-display-test:45038): ERROR **: 10:42:35.488: vnc-error:
> Unsupported auth type 17973672
It is supposed to pass. Can you share more details? It doesn't look
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