On Wed, Nov 30, 2022 at 04:03:28PM -0500, Stefan Hajnoczi wrote:
On Fri, Nov 25, 2022 at 09:12:43AM +0100, Stefano Garzarella wrote:
On Thu, Nov 24, 2022 at 01:36:29PM -0500, Stefan Hajnoczi wrote:
> On Wed, Nov 23, 2022 at 02:16:30PM +0100, Stefano Garzarella wrote:
> > Commit 02b61f38d3 ("hw/v
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
>
> Hi Ard,
>
>
> 在 2022/11/30 16:18, Ard Biesheuvel 写道:
> > On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
> >> On Wed, 30 Nov 2022 02:52:35 +,
> >> "chenxiang (M)" wrote:
> >>> Hi,
> >>>
> >>> We boot the VM using following commands (wit
On Thu, Dec 01, 2022 at 07:13:04AM +0100, Markus Armbruster wrote:
> Keys are int. HMP sendkey assigns them from the value strtoul(),
> silently truncating values greater than INT_MAX. Fix to reject them.
>
> While there, use qemu_strtoul() instead of strtoul() so checkpatch.pl
> won't complain.
On Thu, Dec 01, 2022 at 07:13:03AM +0100, Markus Armbruster wrote:
> When argument @time isn't 'now' or 'never', we parse it as an integer,
> optionally prefixed with '+'. If parsing fails, we silently assume
> zero. Report an error and fail instead.
>
> While there, use qemu_strtou64() instead
On Thu, Dec 1, 2022 at 12:38 AM Michael S. Tsirkin wrote:
>
> On Tue, Nov 29, 2022 at 04:10:34PM +0800, Jason Wang wrote:
> > Hi All:
> >
> > According to ATS, device should work if ATS is disabled. This is not
> > correctly implemented in the current intel-iommu since it doesn't
> > handle the UN
On Wed, Nov 30, 2022 at 11:17 PM Peter Xu wrote:
>
> On Wed, Nov 30, 2022 at 02:33:51PM +0800, Jason Wang wrote:
> > On Tue, Nov 29, 2022 at 11:57 PM Peter Xu wrote:
> > >
> > > On Tue, Nov 29, 2022 at 04:10:37PM +0800, Jason Wang wrote:
> > > > The IOVA tree is only built during page walk this b
On Wed, Nov 30, 2022 at 3:07 PM Eugenio Perez Martin
wrote:
>
> On Wed, Nov 30, 2022 at 8:02 AM Jason Wang wrote:
> >
> > On Fri, Nov 25, 2022 at 1:33 AM Eugenio Pérez wrote:
> > >
> > > Since this capability is emulated by qemu shadowed CVQ cannot forward it
> > > to the device. Process all tha
On Wed, Nov 30, 2022 at 3:40 PM Eugenio Perez Martin
wrote:
>
> On Wed, Nov 30, 2022 at 7:43 AM Jason Wang wrote:
> >
> > On Thu, Nov 24, 2022 at 11:52 PM Eugenio Pérez wrote:
> > >
> > > It can be allocated either if all virtqueues must be shadowed or if
> > > vdpa-net detects it can shadow onl
Hello Pierre
On 11/29/22 18:41, Pierre Morel wrote:
Hi,
The implementation of the CPU Topology in QEMU has been modified
since the last patch series.
- The two preliminary patches have been accepted and are no longer
part of this series.
- The topology machine property has been abandoned
On Wed, Nov 30, 2022 at 11:06 PM Peter Xu wrote:
>
> On Wed, Nov 30, 2022 at 02:23:06PM +0800, Jason Wang wrote:
> > On Tue, Nov 29, 2022 at 11:35 PM Peter Xu wrote:
> > >
> > > On Tue, Nov 29, 2022 at 04:10:35PM +0800, Jason Wang wrote:
> > > > Without caching mode, MAP notifier won't work corre
On Wed, Nov 30, 2022 at 12:08 AM Eric Auger wrote:
>
> Hi Michael,
>
> On 11/29/22 16:44, Michael S. Tsirkin wrote:
> > On Tue, Nov 29, 2022 at 10:52:29AM +0100, Eric Auger wrote:
> >> Hi Jason,
> >>
> >> On 11/29/22 05:02, Jason Wang wrote:
> >>> When vIOMMU is enabled, the vq->used_phys is actua
On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
> HMP "info spice" has a bit of code to show channel type
> SPICE_CHANNEL_WEBDAV as "webdav", disabled since commit 7c6044a94e
> "hmp: info spice: take out webdav" (v2.3.0), because it compiles only
> with Spice versions 0.12.7 and
On Wed, Nov 30, 2022 at 4:11 PM Cindy Lu wrote:
>
> Some device does not support vhost_send_device_iotlb_msg()
> such as vDPA device, which is as expected. So we should not
> return fail here.
Please explain in which case you may hit the -ENODEV and what's the
side effect of this.
Thanks
>
> Si
On Thu, Dec 01, 2022 at 07:13:06AM +0100, Markus Armbruster wrote:
> Fix a few style violations so that checkpatch.pl won't complain when I
> move this code.
>
> Signed-off-by: Markus Armbruster
> ---
> monitor/hmp-cmds.c | 7 ---
> monitor/qmp-cmds.c | 21 +++--
> 2 files c
On Thu, Dec 01, 2022 at 07:13:07AM +0100, Markus Armbruster wrote:
> This moves these commands from MAINTAINERS section "Human
> Monitor (HMP)" to "Graphics".
>
> Command add-client applies to socket character devices in addition to
> display devices. Move it anyway. Aside: the way @protocol cha
On Thu, Dec 01, 2022 at 07:13:08AM +0100, Markus Armbruster wrote:
> This moves these commands from MAINTAINERS section "Human
> Monitor (HMP)" to "Graphics".
>
> Signed-off-by: Markus Armbruster
> ---
> monitor/hmp-cmds.c | 342 --
> ui/ui-hmp-cmds.c |
Queued, thanks.
Paolo
From: Richard Henderson
In get_physical_address, the canonical address check failed to
set TranslateFault.stage2, which resulted in an uninitialized
read from the struct when reporting the fault in x86_cpu_tlb_fill.
Adjust all error paths to use structure assignment so that the
entire struct is
MMX state is saved/restored by FSAVE/FRSTOR so the instructions are
not illegal opcodes even if CR4.OSFXSR=0. Make sure that validate_vex
takes into account the prefix and only checks HF_OSFXSR_MASK in the
presence of an SSE instruction.
Fixes: 20581aadec5e ("target/i386: validate VEX prefixes vi
On Thu, Dec 01, 2022 at 07:13:09AM +0100, Markus Armbruster wrote:
> Switch from monitor_printf() to error_setg() and hmp_handle_error().
> This makes "this is an error" more obvious both in the source and in
> the monitor, where hmp_handle_error() prefixes the message with
> "Error: ".
>
> Signed
On Thu, Dec 01, 2022 at 07:13:11AM +0100, Markus Armbruster wrote:
> Transform
>
> if (good) {
> do stuff
> } else {
> handle error
> }
>
> to
>
> if (!good) {
> handle error
> return;
> }
> do stuff
>
> Signed-off-by: Markus Armbruster
> -
The following changes since commit 7c09a7f6ae1770d15535980d15dffdb23f4d9786:
Update VERSION for v7.2.0-rc2 (2022-11-22 18:59:56 -0500)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 8218c048be1567db9dfd3cf1e19fbff
On Thu, Dec 01, 2022 at 07:13:10AM +0100, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> include/monitor/hmp.h | 5 +
> monitor/hmp-cmds.c| 28 +---
> ui/ui-hmp-cmds.c | 19 +++
> 3 files changed, 21 insertions(+), 31 dele
On 29/11/2022 18.42, Pierre Morel wrote:
We will need a Topology device to transfer the topology
during migration and to implement machine reset.
The device creation is fenced by s390_has_topology().
Signed-off-by: Pierre Morel
---
...
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-
On Wed, Nov 30, 2022 at 09:03:03AM +, Daniel P. Berrangé wrote:
> On Wed, Nov 30, 2022 at 09:02:56AM +0100, Markus Armbruster wrote:
> > Related: QCryptoSecret objects.
>
> snip
>
> > Currently used by various block backends and the tls-creds-x509 object.
> >
> > Would it make sense with di
On Thu, Dec 1, 2022 at 9:39 AM Jason Wang wrote:
>
> On Wed, Nov 30, 2022 at 3:07 PM Eugenio Perez Martin
> wrote:
> >
> > On Wed, Nov 30, 2022 at 8:02 AM Jason Wang wrote:
> > >
> > > On Fri, Nov 25, 2022 at 1:33 AM Eugenio Pérez wrote:
> > > >
> > > > Since this capability is emulated by qemu
Hi,
Stefan is no longer working with us, but I will be more than happy to take
maintaining the nanoMIPS ISA on me!
Regards,
Milica
Any comments on this?
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
On 12/1/22 10:08, Thomas Huth wrote:
On 29/11/2022 18.42, Pierre Morel wrote:
We will need a Topology device to transfer the topology
during migration and to implement machine reset.
The device creation is fenced by s390_has_topology().
Signed-off-by: Pierre Morel
---
...
diff --git a/hw
German Maglione writes:
> On Mon, Nov 28, 2022 at 10:00 AM Marc Hartmayer
> wrote:
>>
>> German Maglione writes:
>>
>> > On Fri, Nov 25, 2022 at 3:40 PM Marc Hartmayer
>> > wrote:
>> >>
>> >> The virtiofsd currently crashes on s390x. This is because of a
>> >> `sigreturn` system call. See au
On Thu, Dec 1, 2022 at 9:45 AM Jason Wang wrote:
>
> On Wed, Nov 30, 2022 at 3:40 PM Eugenio Perez Martin
> wrote:
> >
> > On Wed, Nov 30, 2022 at 7:43 AM Jason Wang wrote:
> > >
> > > On Thu, Nov 24, 2022 at 11:52 PM Eugenio Pérez
> > > wrote:
> > > >
> > > > It can be allocated either if all
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 13 --
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000e.c | 10 +
On 29/11/2022 18.42, Pierre Morel wrote:
The KVM capability, KVM_CAP_S390_CPU_TOPOLOGY is used to
activate the S390_FEAT_CONFIGURATION_TOPOLOGY feature and
the topology facility for the guest in the case the topology
is available in QEMU and in KVM.
The feature is fenced for SE (secure execution
Stefano Garzarella writes:
> On Wed, Nov 30, 2022 at 04:03:28PM -0500, Stefan Hajnoczi wrote:
>>On Fri, Nov 25, 2022 at 09:12:43AM +0100, Stefano Garzarella wrote:
>>> On Thu, Nov 24, 2022 at 01:36:29PM -0500, Stefan Hajnoczi wrote:
>>> > On Wed, Nov 23, 2022 at 02:16:30PM +0100, Stefano Garzar
The 'password-secret' option was added
commit b189346eb1784df95ed6fed610411dbf23d19e1f
Author: Daniel P. Berrangé
Date: Thu Jan 21 14:19:21 2016 +
iscsi: add support for getting CHAP password via QCryptoSecret API
but was not mentioned in the command line docs
Signed-off-by: Da
This deprecates the -iscsi clear text 'password' option
and deletes the previously deprecated -spice 'password'
option.
Daniel P. Berrangé (3):
block: mention 'password-secret' option for -iscsi
block: deprecate iSCSI 'password' in favour of 'password-secret'
ui: remove deprecated 'password'
This has been replaced by the 'password-secret' option,
which references a 'secret' object instance.
Signed-off-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 8
docs/about/removed-features.rst | 7 +++
qemu-options.hx | 9 +
ui/spice-core.c
Support for referencing secret objects was added in
commit b189346eb1784df95ed6fed610411dbf23d19e1f
Author: Daniel P. Berrangé
Date: Thu Jan 21 14:19:21 2016 +
iscsi: add support for getting CHAP password via QCryptoSecret API
The existing 'password' option is overdue for deprec
Milica Lazarevic writes:
> Hi,
>
> Stefan is no longer working with us, but I will be more than happy to take
> maintaining the nanoMIPS ISA on me!
>
> Regards,
> Milica
> Any comments on this?
Suggest you post a patch to update MAINTAINERS, with a suitable cc:.
Daniel P. Berrangé writes:
> On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
>> HMP "info spice" has a bit of code to show channel type
>> SPICE_CHANNEL_WEBDAV as "webdav", disabled since commit 7c6044a94e
>> "hmp: info spice: take out webdav" (v2.3.0), because it compiles only
Philippe Mathieu-Daudé writes:
> On 1/12/22 07:13, Markus Armbruster wrote:
>> This moves these commands from MAINTAINERS section "Human
>> Monitor (HMP)" to "Graphics".
>> Signed-off-by: Markus Armbruster
>> ---
>> monitor/hmp-cmds.c | 342 --
>> ui/ui
Daniel P. Berrangé writes:
> On Thu, Dec 01, 2022 at 07:13:09AM +0100, Markus Armbruster wrote:
>> Switch from monitor_printf() to error_setg() and hmp_handle_error().
>> This makes "this is an error" more obvious both in the source and in
>> the monitor, where hmp_handle_error() prefixes the mes
A register access error typically means something seriously wrong
happened so that anything bad can happen after that and recovery is
impossible.
Even failing one register access is catastorophic as
architecture-specific code are not written so that it torelates such
failures.
Make sure the VM sto
On Wed, 30 Nov 2022 at 18:56, ~axelheider wrote:
>
> This patch adds timer peripherals to the arm-virt machine. The
> use case is, that this machine is quite useful for testing purposes
> when it comes to non-Linux operating system (seL4 in our case).
> However, is currently lacks a dedicates time
Before this change, write_kvmstate_to_list() and
write_list_to_kvmstate() tolerated even if it failed to access some
register, and returned a bool indicating whether one of the register
accesses failed. However, it does not make sen not to fail early as the
the callers check the returned value and
On Thu, Dec 01, 2022 at 10:14:39AM +, Alex Bennée wrote:
> Do you think rust-vmm's vhost crates have enough of the state
> management to manage vhost and vhost-user backends? Maybe it would be a
> good experiment in replacing a (small well defined) piece of
> functionality with rust?
>
> That
On Thu, 1 Dec 2022 at 10:27, Akihiko Odaki wrote:
>
> A register access error typically means something seriously wrong
> happened so that anything bad can happen after that and recovery is
> impossible.
> Even failing one register access is catastorophic as
> architecture-specific code are not wr
On 30/11/2022 18:52, Fabiano Rosas wrote:
Mark Cave-Ayland writes:
Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate
Representation" page. There are a few minor changes to improve the aesthetic
of the final output which are as follows:
- Rename the title from
On 30/11/2022 22:12, Richard Henderson wrote:
On 11/30/22 02:04, Mark Cave-Ayland wrote:
+ * - eqv_i32/i64 *t0*, *t1*, *t2*
+
+ - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* & ~\ *t2*
t1 ^ ~t2
The only typo I saw, fixed while queuing.
Ooops! Thanks for spotting and fixing
On 2022/12/01 19:40, Peter Maydell wrote:
On Thu, 1 Dec 2022 at 10:27, Akihiko Odaki wrote:
A register access error typically means something seriously wrong
happened so that anything bad can happen after that and recovery is
impossible.
Even failing one register access is catastorophic as
arc
On 25/11/2022 16.58, Christian Schoenebeck wrote:
This test requires environment variable QTEST_QEMU_STORAGE_DAEMON_BINARY
to be defined for running. If not, it would immediately abort all qtests
and prevent other, unrelated tests from running.
To fix that, just skip vhost-user-blk-test instead
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
>
> On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
> >
> > Hi Ard,
> >
> >
> > 在 2022/11/30 16:18, Ard Biesheuvel 写道:
> > > On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
> > >> On Wed, 30 Nov 2022 02:52:35 +,
> > >> "chenxiang (M)" w
On Thu, 1 Dec 2022 at 11:00, Akihiko Odaki wrote:
>
> On 2022/12/01 19:40, Peter Maydell wrote:
> > On Thu, 1 Dec 2022 at 10:27, Akihiko Odaki wrote:
> >>
> >> A register access error typically means something seriously wrong
> >> happened so that anything bad can happen after that and recovery i
Emilio Cota writes:
> On Tue, Oct 04, 2022 at 13:00:47 +0100, Daniel P. Berrangé wrote:
> (snip)
>> Can't say I especially like this but I'm out of other ideas for how
>> to guarantee a solution. Users can't set env vars prior to launching
>> QEMU user emulators when using binfmt.
>
> An altern
On 12/1/22 11:15, Thomas Huth wrote:
On 29/11/2022 18.42, Pierre Morel wrote:
The KVM capability, KVM_CAP_S390_CPU_TOPOLOGY is used to
activate the S390_FEAT_CONFIGURATION_TOPOLOGY feature and
the topology facility for the guest in the case the topology
is available in QEMU and in KVM.
The f
On Wed, 30 Nov 2022 at 11:16, Thomas Huth wrote:
>
> By removing #include "kvm-consts.h" from arm-powerctl.h (seems not to
> be required there) and adjusting the header includes in some files, we
> can move them from specific_ss into softmmu_ss, so that they only need
> to be compiled once and not
在 2022/12/1 19:07, Ard Biesheuvel 写道:
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +,
"chenxiang (M
QMP query-pci and HMP info pci can behave differently when there are
no PCI devices. They can report nothing, like this:
qemu-system-aarch64 -S -M spitz -display none -monitor stdio
QEMU 7.1.91 monitor - type 'help' for more information
(qemu) info pci
Or they can fail, like this:
Fix a few style violations so that checkpatch.pl won't complain when I
move this code.
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pci.c
This is mainly about splitting off monitor-related code. There's also
a few UI fixes to HMP command pcie_aer_inject_error.
v2:
* PATCH 08: Use qemu_strtoui() [David], commit message corrected
* PATCH 13: New
Markus Armbruster (13):
pci: Clean up a few things checkpatch.pl would flag later on
I'd like to use @err for an Error *err. Rename PCIEAERErr err to
aer_err.
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci-hmp-cmds.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
This method is for HMP command "info qtree".
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci-internal.h | 1 +
hw/pci/pci-hmp-cmds.c | 38 ++
hw/pci/pci.c | 38
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Dr. David Alan Gilbert
---
hw/pci/pci-hmp-cmds.c | 41 ++---
1 file changed, 6 insertions(+), 35 deletions(-)
diff --git a/hw/pci/pci-hmp-cmds.c b/hw/pci/pci-hmp-cmds.c
index ae75b
PCI AER error status is 32 bit. The HMP command supports both
symbolic and numeric error status: anything that isn't a known
symbolic value is parsed as number with strtol(). Issues:
* Empty argument yields value zero.
* Range errors from strtol() are ignored, value is UINT32_MAX.
* Values not
This moves these commands from MAINTAINERS section "Human
Monitor (HMP)" to "PCI".
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Dr. David Alan Gilbert
---
hw/pci/pci-hmp-cmds.c | 126 +
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
---
hw/pci/pci-internal.h | 20 +
hw/pci/pci-qmp-cmds.c | 201 ++
hw/pci/pci.c | 188 +--
hw/pci/meson.build| 1 +
4 files changed, 226
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Dr. David Alan Gilbert
---
hw/pci/pci-hmp-cmds.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/pci/pci-hmp-cmds.c b/hw/pci/pci-hmp-cmds.c
index 2dd65ca6ee..7a3
When argument @error_status is symbolic, flag -c is ignored. Reject
it instead.
Signed-off-by: Markus Armbruster
---
hw/pci/pci-hmp-cmds.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pci-hmp-cmds.c b/hw/pci/pci-hmp-cmds.c
index 7a3175ab4b..043b0a601d 100644
--- a/hw/pci/pci-
We compile pci-hmp-cmds.c always, but pci-qmp-cmds.c only when
CONFIG_PCI. hw/pci/pci-stub.c keeps the linker happy when
!CONFIG_PCI. Build pci-hmp-cmds.c that way, too.
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
---
hw/pci/pci-stub.c | 5 +
hw/pci/meson.build | 2 +
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci-internal.h | 4 ++
include/monitor/hmp.h | 1 +
include/sysemu/sysemu.h | 3 --
hw/pci/pci-hmp-cmds.c | 104
hw/pci/pci-stub.c
pcibus_dev_print() contains a copy of get_class_desc(). Call the
function instead.
Signed-off-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
---
hw/pci/pci.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 81ffc74925..6711a7
Daniel P. Berrangé writes:
> This has been replaced by the 'password-secret' option,
> which references a 'secret' object instance.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> docs/about/deprecated.rst | 8
> docs/about/removed-features.rst | 7 +++
> qemu-options.hx
"Michael S. Tsirkin" writes:
> On Thu, Dec 01, 2022 at 10:14:39AM +, Alex Bennée wrote:
>> Do you think rust-vmm's vhost crates have enough of the state
>> management to manage vhost and vhost-user backends? Maybe it would be a
>> good experiment in replacing a (small well defined) piece of
Daniel P. Berrangé writes:
> Support for referencing secret objects was added in
>
> commit b189346eb1784df95ed6fed610411dbf23d19e1f
> Author: Daniel P. Berrangé
> Date: Thu Jan 21 14:19:21 2016 +
>
> iscsi: add support for getting CHAP password via QCryptoSecret API
>
> The exis
On Wed, 2022-11-30 at 17:34 +0100, Philippe Mathieu-Daudé wrote:
> Although TCGv is defined as TCGv_i64 on s390x,
> make it clear tcg_temp_new_i64() returns a TCGv_i64.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/s390x/tcg/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 dele
Daniel P. Berrangé writes:
> On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
>> HMP "info spice" has a bit of code to show channel type
>> SPICE_CHANNEL_WEBDAV as "webdav", disabled since commit 7c6044a94e
>> "hmp: info spice: take out webdav" (v2.3.0), because it compiles only
On 1/12/22 11:24, Markus Armbruster wrote:
Milica Lazarevic writes:
Hi,
Stefan is no longer working with us, but I will be more than happy to take
maintaining the nanoMIPS ISA on me!
Regards,
Milica
Any comments on this?
Suggest you post a patch to update MAINTAINERS, with a suitable cc:.
On Thu, 1 Dec 2022 at 13:07, chenxiang (M) wrote:
>
>
>
> 在 2022/12/1 19:07, Ard Biesheuvel 写道:
> > On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
> >> On Thu, 1 Dec 2022 at 08:15, chenxiang (M)
> >> wrote:
> >>> Hi Ard,
> >>>
> >>>
> >>> 在 2022/11/30 16:18, Ard Biesheuvel 写道:
> On Wed
Daniel P. Berrangé writes:
> The 'password-secret' option was added
>
> commit b189346eb1784df95ed6fed610411dbf23d19e1f
> Author: Daniel P. Berrangé
> Date: Thu Jan 21 14:19:21 2016 +
>
> iscsi: add support for getting CHAP password via QCryptoSecret API
>
> but was not mentioned
On 12/1/22 09:45, Cédric Le Goater wrote:
Hello Pierre
On 11/29/22 18:41, Pierre Morel wrote:
Hi,
The implementation of the CPU Topology in QEMU has been modified
since the last patch series.
- The two preliminary patches have been accepted and are no longer
part of this series.
- The
On Thu, 1 Dec 2022 at 10:55, Timofey Kutergin wrote:
> After submitting a patch for cortex-a55 support and trying
> to run SMP on odroid-c4 I have found concern about mpidr_el1 register.
>
> cortex-a55 (and also a75/76/78) seem to be considered SMT CPUs
> with single SMT thread. As a result, they
Many users forget to remove the suggestions from the bug template
when creating a new issue. So when searching for strings like "s390x"
or "Windows", you get a lot of unrelated issues in the results.
Thus let's move the suggestions into HTML comments - so they will
still show up in the markdown whe
From: zhipeng Lu
The drive interface supports media=cdrom so that the usb cdrom
can be emulated as cdrom in qemu, but libvirt deprived the drive
interface, so media=cdrom is added to the blockdev interface to
support usb cdrom emulated as cdrom
Signed-off-by: zhipeng Lu
---
block.c
More like the opposite - proprietary software which does not yet have
proper support for MT CPUs worked fine on QEMU but failed on hardware - so
discrepancy was found.
This does not block anything right now, the question is more how closely
qemu should follow hardware which it emulates...
BR
Timof
Am 28.11.2022 um 15:23 hat Emanuele Giuseppe Esposito geschrieben:
> This is a dump of all minor coroutine-related fixes found while looking
> around and testing various things in the QEMU block layer.
>
> Patches aim to:
> - add missing coroutine_fn annotation to the functions
> - simplify to avo
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-
"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.
Signed-off-by: Bin Meng
---
hw/riscv/opentitan.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index be7ff1eea0..da73aa51f5 100644
--- a/h
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Fixes: 56f6e31
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its default value
zero make
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should i
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.
We use the value of G002 and G003, so it is 53 (including source 0).
[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa492
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
di
At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().
Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
Signed-off-by: Bin Meng
---
hw/
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().
Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.
Signed-off-by: Bin Meng
---
hw/in
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note the irq number ca
PLIC is not included in the 'spike' machine.
Signed-off-by: Bin Meng
---
hw/riscv/spike.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1e1d752c00..13946acf0d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -8,7 +8,6 @@
*
* 0) HTIF Cons
H-mode has been removed since priv spec 1.10. Drop it.
Signed-off-by: Bin Meng
---
include/hw/intc/sifive_plic.h | 1 -
hw/intc/sifive_plic.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index 134cf39a96..d3f45ec248 1
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 1e4b58024f..4550b3b938 100644
--- a/hw/riscv/Kconfig
+++
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