On Thu, Nov 24, 2022 at 3:41 PM Michael S. Tsirkin wrote:
>
> On Thu, Nov 24, 2022 at 03:31:59PM +0800, Jason Wang wrote:
> > On Thu, Nov 24, 2022 at 3:06 PM Michael S. Tsirkin wrote:
> > >
> > > On Thu, Nov 24, 2022 at 12:12:15PM +0800, Jason Wang wrote:
> > > > On Wed, Nov 23, 2022 at 3:21 PM M
On 23/11/2022 19.13, Philippe Mathieu-Daudé wrote:
On 23/11/22 15:12, Alex Bennée wrote:
Thomas Huth writes:
On 23/11/2022 12.15, Philippe Mathieu-Daudé wrote:
On 18/11/22 12:33, Alex Bennée wrote:
The old URL wasn't stable. I suspect the current URL will only be
stable for a few months so m
On Wed, Nov 23, 2022 at 07:13:09PM +0100, Philippe Mathieu-Daudé wrote:
> On 23/11/22 15:12, Alex Bennée wrote:
> > Thomas Huth writes:
> > > On 23/11/2022 12.15, Philippe Mathieu-Daudé wrote:
> > > > On 18/11/22 12:33, Alex Bennée wrote:
> > > > > The old URL wasn't stable. I suspect the current
"Michael S. Tsirkin" writes:
> On Wed, Nov 23, 2022 at 04:03:49PM +, Alex Bennée wrote:
>>
>> "Michael S. Tsirkin" writes:
>>
>> > On Wed, Nov 23, 2022 at 03:21:32PM +, Alex Bennée wrote:
>> >> Hi,
>> >>
>> >> This hopefully fixes the problems with VirtIO migration caused by the
>>
On Thu, Nov 24, 2022 at 09:20:36AM +0100, Thomas Huth wrote:
> On 23/11/2022 19.13, Philippe Mathieu-Daudé wrote:
> > On 23/11/22 15:12, Alex Bennée wrote:
> > > Thomas Huth writes:
> > > > On 23/11/2022 12.15, Philippe Mathieu-Daudé wrote:
> > > > > On 18/11/22 12:33, Alex Bennée wrote:
> > > > >
Gentle ping.
Did I understand the problem or am I wrong?
On 11/17/22 17:38, Pierre Morel wrote:
On 11/17/22 10:31, Pierre Morel wrote:
On 11/16/22 17:51, Christian Borntraeger wrote:
Am 02.09.22 um 09:55 schrieb Pierre Morel:
Hi,
The implementation of the CPU Topology in QEMU has bee
On Thu, Nov 24, 2022 at 12:06:10AM +0100, Philippe Mathieu-Daudé wrote:
> On 23/11/22 19:49, Cédric Le Goater wrote:
> > On 11/23/22 19:13, Philippe Mathieu-Daudé wrote:
> > > On 23/11/22 15:12, Alex Bennée wrote:
> > > > Thomas Huth writes:
> > > > > On 23/11/2022 12.15, Philippe Mathieu-Daudé wr
On Thu, Nov 24, 2022 at 09:21:15AM +, Alex Bennée wrote:
>
> "Michael S. Tsirkin" writes:
>
> > On Wed, Nov 23, 2022 at 04:03:49PM +, Alex Bennée wrote:
> >>
> >> "Michael S. Tsirkin" writes:
> >>
> >> > On Wed, Nov 23, 2022 at 03:21:32PM +, Alex Bennée wrote:
> >> >> Hi,
> >> >>
Hi Thomas
On Wed, Nov 23, 2022 at 6:19 PM Thomas Huth wrote:
>
> On 23/11/2022 15.13, Marc-André Lureau wrote:
> > Hi Bin
> >
> > On Fri, Oct 28, 2022 at 9:06 AM Bin Meng wrote:
> >>
> >> Now that we have fixed various test case issues as seen when running
> >> on Windows, let's enable the qtest
On 24/11/2022 12.17, Marc-André Lureau wrote:
Hi Thomas
On Wed, Nov 23, 2022 at 6:19 PM Thomas Huth wrote:
On 23/11/2022 15.13, Marc-André Lureau wrote:
Hi Bin
On Fri, Oct 28, 2022 at 9:06 AM Bin Meng wrote:
Now that we have fixed various test case issues as seen when running
on Windows,
This patchset converts the TYPE_CPU base class and most subclasses
to use 3-phase reset. (The exception is s390, which is doing
something a bit odd with its reset, so the conversion there isn't
going to be simple like these others. So I'll do that one
separately.)
The rationale here is that we sho
Convert the microblaze CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/microblaze/cpu-qom.h | 4 ++--
target/microblaze/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
dif
Convert the hexagon CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/hexagon/cpu.h | 2 +-
target/hexagon/cpu.c | 12
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hex
Convert the nios2 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/nios2/cpu.h | 4 ++--
target/nios2/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/nios2/
Convert the i386 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/i386/cpu-qom.h | 4 ++--
target/i386/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/i
Convert the sh4 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/sh4/cpu-qom.h | 4 ++--
target/sh4/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/sh4/
Convert the tricore CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/tricore/cpu-qom.h | 2 +-
target/tricore/cpu.c | 12
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/ta
Convert the sparc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/sparc/cpu-qom.h | 4 ++--
target/sparc/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/targe
Convert the ppc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/ppc/cpu-qom.h | 4 ++--
target/ppc/cpu_init.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/pp
Convert the mips CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/mips/cpu-qom.h | 4 ++--
target/mips/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/m
Convert the xtensa CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/xtensa/cpu-qom.h | 4 ++--
target/xtensa/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/ta
On Wed, 23 Nov 2022 at 21:58, Stefan Hajnoczi wrote:
>
> Applied, thanks.
>
> Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
> user-visible changes.
...that pullreq had for-8.0 patches in it. I dunno if they're
so risky that we ought to revert them, though.
-- PMM
Convert the m68k CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/m68k/cpu-qom.h | 4 ++--
target/m68k/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/m
Convert the Arm CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/arm/cpu-qom.h | 4 ++--
target/arm/cpu.c | 13 +
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm
Convert the cris CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/cris/cpu-qom.h | 4 ++--
target/cris/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/c
Convert the openrisc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/openrisc/cpu.h | 4 ++--
target/openrisc/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/targ
Convert the avr CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/avr/cpu-qom.h | 4 ++--
target/avr/cpu.c | 13 +
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/avr
Convert the loongarch CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/loongarch/cpu.h | 4 ++--
target/loongarch/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/t
Convert the parent class TYPE_CPU to 3-phase reset. This
is a necessary prerequisite to converting the subclasses.
Signed-off-by: Peter Maydell
---
hw/core/cpu-common.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index f9
Convert the riscv CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/riscv/cpu.h | 4 ++--
target/riscv/cpu.c | 12
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/riscv/
Convert the rx CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
---
target/rx/cpu-qom.h | 4 ++--
target/rx/cpu.c | 13 -
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/rx/cpu
Hi
On Thu, Nov 24, 2022 at 3:49 PM Thomas Huth wrote:
>
> On 24/11/2022 12.17, Marc-André Lureau wrote:
> > Hi Thomas
> >
> > On Wed, Nov 23, 2022 at 6:19 PM Thomas Huth wrote:
> >>
> >> On 23/11/2022 15.13, Marc-André Lureau wrote:
> >>> Hi Bin
> >>>
> >>> On Fri, Oct 28, 2022 at 9:06 AM Bin Me
On 23/11/2022 20:23, Dr. David Alan Gilbert wrote:
External email: Use caution opening links or attachments
* Avihai Horon (avih...@nvidia.com) wrote:
On 08/11/2022 19:52, Vladimir Sementsov-Ogievskiy wrote:
External email: Use caution opening links or attachments
On 11/3/22 19:16, Avihai
On 23/11/2022 20:59, Dr. David Alan Gilbert wrote:
External email: Use caution opening links or attachments
* Avihai Horon (avih...@nvidia.com) wrote:
+ret = qemu_file_get_to_fd(f, migration->data_fd, data_size);
+if (!ret) {
+trace_vfio_load_state_device_data(vbasedev->na
在 2022/11/23 1:09, Stefan Hajnoczi 写道:
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
Hi, Where can I register an account?
Thanks.
Song Gao
On 20/11/2022 11:34, Avihai Horon wrote:
On 17/11/2022 19:38, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 17 Nov 2022 19:07:10 +0200
Avihai Horon wrote:
On 16/11/2022 20:29, Alex Williamson wrote:
On Thu, 3 Nov 2022 18:16:15 +0200
Avihai Horon
On Thu, Nov 24, 2022 at 08:30:45PM +0800, gaos...@loongson.cn wrote:
>
> 在 2022/11/23 1:09, Stefan Hajnoczi 写道:
> > Applied, thanks.
> >
> > Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
> > user-visible changes.
> Hi, Where can I register an account?
Due to spam a
在 2022/11/24 20:44, Daniel P. Berrangé 写道:
On Thu, Nov 24, 2022 at 08:30:45PM +0800, gaos...@loongson.cn wrote:
在 2022/11/23 1:09, Stefan Hajnoczi 写道:
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
Hi, Where can I register
"Michael S. Tsirkin" writes:
> On Thu, Nov 24, 2022 at 09:21:15AM +, Alex Bennée wrote:
>>
>> "Michael S. Tsirkin" writes:
>>
>> > On Wed, Nov 23, 2022 at 04:03:49PM +, Alex Bennée wrote:
>> >>
>> >> "Michael S. Tsirkin" writes:
>> >>
>> >> > On Wed, Nov 23, 2022 at 03:21:32PM +00
On Wed, Aug 24, 2022 at 03:17:00PM -0700, Atish Patra wrote:
> Qemu virt machine can support few cache events and cycle/instret counters.
> It also supports counter overflow for these events.
>
> Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
> capabilities. There are some
On Wed, 23 Nov 2022 19:55:14 +,
Alex Williamson wrote:
>
> On Wed, 23 Nov 2022 12:08:05 +
> Marc Zyngier wrote:
>
> > On Wed, 23 Nov 2022 01:42:36 +,
> > chenxiang wrote:
> > >
> > > +static int vfio_pci_verify_msi_entry(struct vfio_pci_core_device *vdev,
> > > + struct ev
On Wed, 23 Nov 2022 at 09:54, Mark Cave-Ayland
wrote:
>
> Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate
> Representation" page. There are a few minor changes to improve the aesthetic
> of the final output which are as follows:
>
> - Rename the title from "Tiny Co
* Avihai Horon (avih...@nvidia.com) wrote:
>
> On 23/11/2022 20:59, Dr. David Alan Gilbert wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > * Avihai Horon (avih...@nvidia.com) wrote:
> >
> >
> >
> > > +ret = qemu_file_get_to_fd(f, migration->data_fd, data_si
On 24/11/22 12:50, Peter Maydell wrote:
This patchset converts the TYPE_CPU base class and most subclasses
to use 3-phase reset. (The exception is s390, which is doing
something a bit odd with its reset, so the conversion there isn't
going to be simple like these others. So I'll do that one
separ
> On Nov 24, 2022, at 2:54 AM, Stefano Garzarella wrote:
>
> On Thu, Nov 24, 2022 at 01:50:19AM -0500, Michael S. Tsirkin wrote:
>> On Thu, Nov 24, 2022 at 12:19:25AM +, Raphael Norwitz wrote:
>>>
>>> > On Nov 23, 2022, at 8:16 AM, Stefano Garzarella
>>> > wrote:
>>> >
>>> > Commit 02b6
Added the SPDX license identifiers for biosbits tests.
Also added a comment on each of the test scripts to indicate that they run
from within the biosbits environment and hence are not subjected to the regular
maintanance acivities for QEMU and is excluded from the dependency management
challenges
> Isn't this '0' flag here accelerator-specific? ...
> ... if so the prototype should be:
>
> int (*update_guest_debug)(CPUState *cpu);
>
> and the '0' value set within kvm-accel-ops.c handler implementation.
>
You're right, we can avoid the additional variable. We'll then have to wrap
On 24/11/2022 15:28, Dr. David Alan Gilbert wrote:
External email: Use caution opening links or attachments
* Avihai Horon (avih...@nvidia.com) wrote:
On 23/11/2022 20:59, Dr. David Alan Gilbert wrote:
External email: Use caution opening links or attachments
* Avihai Horon (avih...@nvidia
On Thu, Nov 24, 2022 at 07:28:34PM +0530, Ani Sinha wrote:
> Added the SPDX license identifiers for biosbits tests.
> Also added a comment on each of the test scripts to indicate that they run
> from within the biosbits environment and hence are not subjected to the
> regular
> maintanance aciviti
* Markus Armbruster (arm...@redhat.com) wrote:
> Tweak the semantic patch to drop redundant parenthesis around the
> return expression.
>
> Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored
> manually.
>
> Coccinelle messes up vmdk_co_create(), not sure why. Change dropped,
> will
On Thu, Nov 24, 2022 at 11:50:12AM +, Peter Maydell wrote:
> Convert the microblaze CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/microblaze/cpu-qom.h |
On Thu, Nov 24, 2022 at 11:50:07AM +, Peter Maydell wrote:
> Convert the cris CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/cris/cpu-qom.h | 4 ++--
>
On Thu, Nov 24, 2022 at 7:47 PM Michael S. Tsirkin wrote:
>
> On Thu, Nov 24, 2022 at 07:28:34PM +0530, Ani Sinha wrote:
> > Added the SPDX license identifiers for biosbits tests.
> > Also added a comment on each of the test scripts to indicate that they run
> > from within the biosbits environmen
On 2022/11/23 19:59, Peter Maydell wrote:
> On Wed, 23 Nov 2022 at 11:38, Changbin Du wrote:
>>
>> Hello, Richard,
>> We just noticed the gdb-stub is broken and probably caused by commit
>> 4a3585568
>> ("target/arm: Plumb debug into S1Translate").
>>
>> (gdb) target remote :1234
>> Remote deb
On 11/24/22 12:50, Peter Maydell wrote:
Convert the ppc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/cpu-qom.h | 4 ++--
target/ppc/cpu_init.c
On Tue, 22 Nov 2022 14:49:16 +0100
Markus Armbruster wrote:
> Tweak the semantic patch to drop redundant parenthesis around the
> return expression.
>
> Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored
> manually.
>
> Coccinelle messes up vmdk_co_create(), not sure why. Change
On 11/24/22 12:50, Peter Maydell wrote:
Convert the Arm CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/arm/cpu-qom.h | 4 ++--
target/arm/cpu.c |
On 24/11/22 14:58, Ani Sinha wrote:
Added the SPDX license identifiers for biosbits tests.
Also added a comment on each of the test scripts to indicate that they run
from within the biosbits environment and hence are not subjected to the regular
maintanance acivities for QEMU and is excluded from
On Thu, 24 Nov 2022 11:50:16 +
Peter Maydell wrote:
> Convert the ppc CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
>
> Signed-off-by: Peter Maydell
> ---
Reviewed-by: Greg Kurz
> target/ppc/cpu-qom.h | 4 ++--
> target/ppc/cpu_i
On Thu, 24 Nov 2022 16:15:11 +0100
Greg Kurz wrote:
> On Tue, 22 Nov 2022 14:49:16 +0100
> Markus Armbruster wrote:
>
> > Tweak the semantic patch to drop redundant parenthesis around the
> > return expression.
> >
> > Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored
> > manual
This function used to trust in v->shadow_vqs != NULL to know if it must
start svq or not.
This is not going to be valid anymore, as qemu is going to allocate svq
array unconditionally (but it will only start them conditionally).
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio/v
It will be reused at vdpa device start so let's extract in its own
function.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 2b4b85d8f
By the end of this series CVQ is shadowed as long as the features
support it.
Since we don't know at the beginning of qemu running if this is
supported, move the event notifier handler setting to the start of the
SVQ, instead of the start of qemu run. This will avoid to create them if
the device d
It can be allocated either if all virtqueues must be shadowed or if
vdpa-net detects it can shadow only cvq.
Extract in its own function so we can reuse it.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
d
Since we don't know if we will use SVQ at qemu initialization, let's
allocate iova_tree only if needed. To do so, accept it at SVQ start, not
at initialization.
This will avoid to create it if the device does not support SVQ.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h |
The next patches will start control SVQ if possible. However, we don't
know if that will be possible at qemu boot anymore.
Since the moved checks will be already evaluated at net/ to know if it
is ok to shadow CVQ, move them.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio/vhos
Control VQ is the way net devices use to send changes to the device state, like
the number of active queues or its mac address.
QEMU needs to intercept this queue so it can track these changes and is able to
migrate the device. It can do it from 1576dbb5bbc4 ("vdpa: Add x-svq to
NetdevVhostVDPAOpt
So the caller can choose which ASID is destined.
No need to update the batch functions as they will always be called from
memory listener updates at the moment. Memory listener updates will
always update ASID 0, as it's the passthrough ASID.
All vhost devices's ASID are 0 at this moment.
Signed-
The memory listener that thells the device how to convert GPA to qemu's
va is registered against CVQ vhost_vdpa. memory listener translations
are always ASID 0, CVQ ones are ASID 1 if supported.
Let's tell the listener if it needs to register them on iova tree or
not.
Signed-off-by: Eugenio Pérez
SVQ may run or not in a device depending on runtime conditions (for
example, if the device can move CVQ to its own group or not).
Allocate the SVQ array unconditionally at startup, since its hard to
move this allocation elsewhere.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
hw/virtio
Isolate control virtqueue in its own group, allowing to intercept control
commands but letting dataplane run totally passthrough to the guest.
Signed-off-by: Eugenio Pérez
---
v8:
* Do not allocate iova_tree on net_init_vhost_vdpa if only CVQ is
shadowed. Move the iova_tree handling in this cas
CVQ can be shadowed two ways:
- Device has x-svq=on parameter (current way)
- The device can isolate CVQ in its own vq group
QEMU needs to check for the second condition dynamically, because CVQ
index is not known before the driver ack the features. Since this is
dynamic, the CVQ isolation could v
The next patches will start control SVQ if possible. However, we don't
know if that will be possible at qemu boot anymore.
Delay device file descriptors until we know it at device start. This
will avoid to create them if the device does not support SVQ.
Signed-off-by: Eugenio Pérez
Acked-by: Jas
The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions
currently return a positive errno value on failure. This causes
checkpatch.pl to spit several errors like the one below:
ERROR: return of an errno should typically be -ve (return -EAGAIN)
#79: FILE: hw/9pfs/9p-synth.c:79:
+
This patch set allows using End-to-End Data Protection in NVMe subsystem
with integrity capable host devices as the NVMe namespaces backend.
The patch series is based on io-uring kernel interface feature not merged
to kernel upstream yet:
https://lore.kernel.org/linux-block/20220920144618.138-1
Describe use of new protection info block-level passthrough nvme feature.
Signed-off-by: Dmitry Tihov
---
docs/system/devices/nvme.rst | 15 +++
1 file changed, 15 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index 30f841ef62..7375379810 100
Allow namespace to enable pass-through of protection information
between guest and integrity capable BlockBackend.
Signed-off-by: Dmitry Tihov
---
hw/nvme/ns.c | 59 +-
hw/nvme/nvme.h | 2 ++
2 files changed, 55 insertions(+), 6 deletions(-)
di
Add protection information block level passthrough support to compare,
dataset management, verify and copy nvme commands.
Signed-off-by: Dmitry Tihov
---
hw/nvme/ctrl.c | 348 +++
hw/nvme/trace-events | 2 +
2 files changed, 325 insertions(+), 25 d
Under linux hosts, T10 protection information can be passed directly
from userspace to integrity capable block devices using io_uring API.
Discover integrity capable block devices and support submitting IO with
integrity payload to such block devices if it is present in request.
Signed-off-by: Dmi
This patch adds ability for read, write and write zeroes commands
to submit single request with data and integrity directly to underlying
device using block-level transfer of protection information. Block
level supports only type1/type3 protection types and for the type1
protection type guard/refta
On Wed, Nov 09, 2022 at 02:56:29AM -0300, Leonardo Bras wrote:
> diff --git a/migration/savevm.c b/migration/savevm.c
> index a0cdb714f7..250caff7f4 100644
> --- a/migration/savevm.c
> +++ b/migration/savevm.c
> @@ -1889,6 +1889,8 @@ static void *postcopy_ram_listen_thread(void *opaque)
>
On Fri, Nov 18, 2022 at 04:36:48PM +0800, Chuang Xu wrote:
> The duration of loading non-iterable vmstate accounts for a significant
> portion of downtime (starting with the timestamp of source qemu stop and
> ending with the timestamp of target qemu start). Most of the time is spent
> committing m
A gratuitous ARP is recommended after a live migration to reduce the amount of
time needed by the network links to be aware of the new location. A hypervisor
may not have the knowledge of the guest network configuration, and this is
especially true on passthrough devices, so its simpler to ask the
Next patches introduce more code on vhost-vdpa branch, with already have
too much indentation.
Signed-off-by: Eugenio Pérez
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
---
hw/net/virtio-net.c | 28 +++-
1 file changed, 15 insertions(+), 13 deleti
Since this capability is emulated by qemu shadowed CVQ cannot forward it
to the device. Process all that command within qemu.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
Status part of the emulated feature. It will follow device model, so we
must copy it as long as NIC device model has it set.
Signed-off-by: Eugenio Pérez
---
hw/net/virtio-net.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index eed629766f..bf71ef
So qemu emulates it even in case the device does not support it.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 8172aa8449..79f022c2bf 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -72,7 +72
On Wed, Nov 23, 2022 at 09:42:36AM +0800, chenxiang via wrote:
> From: Xiang Chen
>
> Currently the number of MSI vectors comes from register PCI_MSI_FLAGS
> which should be power-of-2 in qemu, in some scenaries it is not the same as
> the number that driver requires in guest, for example, a PCI
axel/qemu.git tags/fixes-20221124-pull-request
>
> for you to fetch changes up to 64f1359bd08060ffe7a5689fdcbaeec6d8a59980:
>
> ui/gtk: prevent ui lock up when dpy_gl_update called again before current
> draw event occurs (2022-11-23 12:27:55 +0100)
>
>
On 18.11.22 18:40, Kevin Wolf wrote:
I'm aware that exactly nobody has been looking forward to a series with
this title, but it has to be. The way drain works means that we need to
poll in bdrv_replace_child_noperm() and that makes things rather messy
with Emanuele's multiqueue work because you m
On Wed, Nov 23, 2022 at 02:16:30PM +0100, Stefano Garzarella wrote:
> Commit 02b61f38d3 ("hw/virtio: incorporate backend features in features")
> properly negotiates VHOST_USER_F_PROTOCOL_FEATURES with the vhost-user
> backend, but we forgot to enable vrings as specified in
> docs/interop/vhost-use
Greg Kurz writes:
> On Thu, 24 Nov 2022 16:15:11 +0100
> Greg Kurz wrote:
>
>> On Tue, 22 Nov 2022 14:49:16 +0100
>> Markus Armbruster wrote:
>>
>> > Tweak the semantic patch to drop redundant parenthesis around the
>> > return expression.
>> >
>> > Coccinelle drops a comment in hw/rdma/vmw/p
MIPS Trickbox is a emulated device present in MIPS's proprietary
simulators for decadeds. It's capable for managing simulator status,
signaling interrupts, doing DMA and EJTAG stimulations.
For now we just borrow this device and implement power management
related functions.
Signed-off-by: Jiaxun
hw/sysbus.h is missed in goldfish_pic.h.
Signed-off-by: Jiaxun Yang
---
include/hw/intc/goldfish_pic.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/hw/intc/goldfish_pic.h b/include/hw/intc/goldfish_pic.h
index e9d552f796..3e79580367 100644
--- a/include/hw/intc/goldfish_pic.h
++
Hi there,
This patchset is to add a new machine type for MIPS architecture, which
is purely a VirtIO machine.
It is design to utilize existing VirtIO infrastures but also comptitable
with MIPS's existing internal simulation tools.
It should be able to cooperate with any MIPS core and boot Generi
MIPS VirtIO board is design to utilize existing VirtIO infrastures
but also comptitable with MIPS's existing internal simulation tools.
It includes virtio-mmio, pcie gpex, flash rom, fw_cfg, goldfish-rtc,
and optional goldfish_pic in case MIPS GIC is not present.
It should be able to cooperate wi
"Michael S. Tsirkin" writes:
> On Thu, Nov 24, 2022 at 09:21:15AM +, Alex Bennée wrote:
>>
>> "Michael S. Tsirkin" writes:
>>
>> > On Wed, Nov 23, 2022 at 04:03:49PM +, Alex Bennée wrote:
>> >>
>> >> "Michael S. Tsirkin" writes:
>> >>
>> >> > On Wed, Nov 23, 2022 at 03:21:32PM +00
On Tue, Nov 22, 2022 at 6:07 PM Atish Patra wrote:
>
> The imsic DT binding[1] has changed and no longer require an ipi-id.
> The latest IMSIC driver dynamically allocates ipi id if slow-ipi
> is not defined.
>
> Get rid of the unused dt property which may lead to confusion.
>
> [1]
> https://lor
On Wed, Nov 23, 2022 at 2:07 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Wed, Nov 23, 2022 at 8:03 AM Alistair Francis wrote:
> >
> > On Wed, Nov 23, 2022 at 2:07 AM Bin Meng wrote:
> > >
> > > sstatus register dump is currently missing in riscv_cpu_dump_state().
> > >
> > > Resolves: https://git
Fixes: CVE-2019-14560
GetEfiGlobalVariable2() is used in some instances when looking up the
SecureBoot UEFI variable. The API can fail in certain circumstances,
for example, if AllocatePool() fails or if gRT->GetVariable() fails.
In the case of secure boot checks, it is critical that this return v
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