On 18/11/2022 05.05, Ani Sinha wrote:
On Wed, Nov 16, 2022 at 8:54 AM Ani Sinha wrote:
On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote:
Instead of using a hardcoded timeout, just rely on Avocado's built-in
test case timeout. This helps avoid timeout issues on machines where 60
seconds is no
On 17/11/22 18:25, Alex Bennée wrote:
The boot_linux tests download and run a full cloud image boot and
start a full distro. While the ability to test the full boot chain is
worthwhile it is perhaps a little too heavy weight and causes issues
in CI. Fix this by introducing a new alpine linux ISO
On 17/11/22 18:25, Alex Bennée wrote:
We now have a much lighter weight test in machine_aarch64_virt which
tests the full boot chain in less time. Rename the tests while we are
at it to make it clear it is a Fedora cloud image.
Signed-off-by: Alex Bennée
---
tests/avocado/boot_linux.py | 9 ++
On 17/11/22 18:25, Alex Bennée wrote:
From: Peter Maydell
The two tests
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
take quite a long time to run, and the current timeout of 240s
is not enough for the tests t
The duration of loading non-iterable vmstate accounts for a significant
portion of downtime (starting with the timestamp of source qemu stop and
ending with the timestamp of target qemu start). Most of the time is spent
committing memory region changes repeatedly.
This patch packs all the changes
On Fri, 11 Nov 2022 12:22:08 +0800
Bin Meng wrote:
> These are not used anywhere in the source tree. Drop them.
>
> Signed-off-by: Bin Meng
> ---
>
This one could even go through the trivial tree right
away IMHO.
Reviewed-by: Greg Kurz
> (no changes since v1)
>
> hw/9pfs/9p-util.h | 11 -
Keep the old limit of 288 for machine versions 7.2 and earlier.
Signed-off-by: Dario Faggioli
---
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: "Michael S. Tsirkin"
Cc: Marcel Apfelbaum
---
Changes from v1:
- fix actually keeping the old max value for the 7.2 machine type,
On Fri, Nov 18, 2022 at 09:55:35AM +0100, Dario Faggioli wrote:
> Keep the old limit of 288 for machine versions 7.2 and earlier.
>
> Signed-off-by: Dario Faggioli
> ---
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Habkost
> Cc: "Michael S. Tsirkin"
> Cc: Marcel Apfelbaum
> ---
In addition, use tcg_enabled instead of !kvm_enabled.
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
---
target/ppc/helper_regs.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index c0aee5855b
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Jiaxun Yang
---
hw/mips/mips_int.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 2db5e10fe0..73437cd90f 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mi
Narrow the scope of the lock to the actual read/write,
moving the cpu_transation_failed call outside the lock.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cpu
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
---
hw/ppc/ppc.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index dc86c1c7db..4e816c68c7 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -44,13 +44,9 @@ void ppc_set_irq(Pow
Create a wrapper for locking/unlocking the iothread lock.
Signed-off-by: Richard Henderson
---
Cc: Paolo Bonzini (maintainer:Main loop)
---
include/qemu/main-loop.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/qemu/main-loop.h b/include/qemu/main-lo
Simplify the usage of qemu_mutex_lock_iothread.
Split out for ease of review.
Doesn't actually depend on anything, but patchew only handles a single
dependency, so I need to thread the dependency through the patch sets.
Based-on: 2022074101.2069454-1-richard.hender...@linaro.org
("tcg: Suppor
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
---
target/ppc/excp_helper.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 94adcb766b..8591bb3f73 100644
--- a/target/ppc/excp_helper.c
+++ b/ta
Signed-off-by: Richard Henderson
---
Cc: Alistair Francis
Cc: Bin Meng
Cc: qemu-ri...@nongnu.org
---
target/riscv/cpu_helper.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 278d163803..241d06bab8 100644
On Fri, 11 Nov 2022 12:22:11 +0800
Bin Meng wrote:
> With this new QemuFd_t type, it significantly reduces the number of
I cannot find the definition of this type, nor the definition of
qemu_fd_invalid(). Missing patch ?
Anyway, IIUC this type is an int for linux and a HANDLE for windows,
right
On 11/17/22 19:04, Dario Faggioli wrote:
> Well...
>
> On Thu, 2022-11-17 at 16:27 +0100, Dario Faggioli wrote:
>> Keep the old limit of 288 for machine versions 7.2 and earlier.
>>
> ...At least, this was the idea...
>
>> --- a/hw/i386/pc_q35.c
>> +++ b/hw/i386/pc_q35.c
>> @@ -386,6 +386,7 @@ st
On 11/18/22 10:18, Richard Henderson wrote:
Simplify the usage of qemu_mutex_lock_iothread.
Split out for ease of review.
Doesn't actually depend on anything, but patchew only handles a single
dependency, so I need to thread the dependency through the patch sets.
Based-on: 2022074101.206945
On Fri, Nov 18, 2022 at 09:55:35AM +0100, Dario Faggioli wrote:
> Keep the old limit of 288 for machine versions 7.2 and earlier.
>
> Signed-off-by: Dario Faggioli
> ---
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Habkost
> Cc: "Michael S. Tsirkin"
> Cc: Marcel Apfelbaum
> ---
On 11/11/2022 13.45, Cornelia Huck wrote:
Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
...
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0ad0ed160387..1c0a7b83b545 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -435,7 +435,7
With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert. Unify the pairs of functions.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-ldst.h | 60 --
accel/tcg/cputlb.c | 1
Unify the softmmu and the user-only paths by using the
official memory interface. Avoid double logging of memory
operations to plugins by relying on the ones within the
cpu_*_mmu functions.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 9 +++-
tcg/tci.c| 127
Hosts using Intel and AMD AVX cpus are quite common.
Add fast paths through ldst_atomicity using this.
Signed-off-by: Richard Henderson
---
accel/tcg/ldst_atomicity.c.inc | 76 +++---
1 file changed, 60 insertions(+), 16 deletions(-)
diff --git a/accel/tcg/ldst_atomi
Adding a vector type will make it easier to handle i386
have_atomic16 via AVX.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index f62a46b48c..f29f90e6f4 1006
These bits may be used to describe the precise atomicity
requirements of the guest, which may then be used to
constrain the methods by which it may be emulated by the host.
For instance, the AArch64 LDP (32-bit) instruction changes
semantics with ARMv8.4 LSE2, from
MO_64 | MO_ATMAX_4 | MO_ATOM_
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 177 +
accel/tcg/user-exec.c | 12 +-
accel/tcg/ldst_atomicity.c.inc | 336 +
3 files changed, 480 insertions(+), 45 deletions(-)
diff --git a/accel/tcg/cputlb.c b/acce
Reorg TCG_OPF_64BIT and TCG_OPF_VECTOR into a two-bit field so
that we can add TCG_OPF_128BIT without requiring another bit.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 22 --
tcg/optimize.c | 15 ---
tcg/tcg.c
There is an edge condition prior to gcc13 for which optimization
is required to generate 16-byte atomic sequences. Detect this.
Signed-off-by: Richard Henderson
---
accel/tcg/ldst_atomicity.c.inc | 38 ++---
meson.build| 52 ++-
Use one of the coprocessors to perform 64-bit stores.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 119 +-
1 file changed, 106 insertions(+), 13 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 3f0cb4bc
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h| 3 +
include/tcg/tcg-ldst.h | 4 +
accel/tcg/cputlb.c | 480 +
accel/tcg/user-exec.c | 94 +--
tcg/tcg-op.c | 178 +++-
accel/tcg/l
Prepare for TCG_TYPE_I128 by not using a boolean.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 54 ++-
1 file changed, 36 insertions(+), 18 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index eb93807b5f..e
The main objective here is to support Arm FEAT_LSE2, which says that any
single memory access that does not cross a 16-byte boundary is atomic.
This is the MO_ATOM_WITHIN16 control.
While I'm touching all of this, a secondary objective is to handle the
atomicity of the IBM machines. Both Power an
Instead of using helper_unaligned_{ld,st}, use the full
load/store helpers. This will allow the fast path to
increase alignment to implement atomicity while not
immediately raising an alignment exception.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 332 -
Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 3 +++
tcg/aarch64/tcg-target.c.inc | 10 ++
2 files changed, 13 insertions(+)
diff --git a/tcg/aarch64/tc
While we do not include these in tcg_target_reg_alloc_order,
and therefore they ought never be allocated, it seems safer
to mark them reserved as well.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 13 +
1 file changed, 13 insertions(+)
diff --git a/tcg/i386/tcg-t
Create ldst_atomicity.c.inc.
Not required for user-only code loads, because we've ensured that
the page is read-only before beginning to translate code.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 174 ---
accel/tcg/user-exec.c | 26 +-
accel/tcg/ldst
TCG backends may need to defer to a helper to implement
the atomicity required by a given operation. Mirror the
interface used in system mode.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-ldst.h | 6 +-
accel/tcg/user-exec.c | 392 -
2 files ch
Replace the two uses of asm to expand xgetbv with an inline function.
Since one of the two has been using the mnemonic, assume that the
comment about "older versions of the assember" is obsolete, as even
that is 4 years old.
Signed-off-by: Richard Henderson
---
include/qemu/cpuid.h | 7 +++
Notice when Intel has guaranteed that vmovdqa is atomic.
The new variable will also be used in generated code.
Signed-off-by: Richard Henderson
---
include/qemu/cpuid.h | 18 ++
tcg/i386/tcg-target.h | 1 +
tcg/i386/tcg-target.c.inc | 27 +++
3 f
Instead of playing with offsetof in various places, use
MMUAccessType to index an array. This is easily defined
instead of the previous dummy padding array in the union.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 7 ++-
include/exec/cpu_ldst.h | 26 --
accel/tcg/c
Instead of trying to unify all operations on uint64_t, pull out
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 606 ++---
1 file chan
Add opcodes for backend support for 128-bit memory operations.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8 +
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/i386/tcg-target.h| 2 ++
tcg/loongarch64/tcg-target.h | 2 ++
tcg
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index f277085321..3f0cb4bc66 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c
Create a helper for data movement minding register overlap.
Use the more general xchg instruction, which consumes one
extra byte, but simplifies the more general function.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 27 +--
1 file changed, 21 insertio
We have code in atomic128.h noting that through GCC 8, there
was no support for atomic operations on __uint128. This has
been fixed in GCC 10. But we can still improve over any
basic compare-and-swap loop using the ldxp/stxp instructions.
Add fast paths for FEAT_LSE2, using the detection in tcg.
Am 17/11/2022 um 20:27 schrieb David Hildenbrand:
> On 11.11.22 16:47, Emanuele Giuseppe Esposito wrote:
>> Using the new accel-blocker API, mark where ioctls are being called
>> in KVM. Next, we will implement the critical section that will take
>> care of performing memslots modifications atom
Split out a helper for choosing testb vs testl.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 79568a3981..5ddbbbaf18 1
Like cpu_in_exclusive_context, but also true if
there is no other cpu against which we could race.
Use it in tb_flush as a direct replacement.
Use it in cpu_loop_exit_atomic to ensure that there
is no loop against cpu_exec_step_atomic.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h
Instead of trying to unify all operations on uint64_t, use
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 399 -
1 file changed,
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 3 +-
tcg/i386/tcg-target.c.inc | 325 +++---
2 files changed, 304 insertions(+), 24 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 53d2cb3412..7aafd60d72 100644
---
No change to the ultimate load/store routines yet, so some
atomicity conditions not yet honored, but plumbs the change
to alignment through the adjacent functions.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 128 ++
1 file changed, 101 ins
On 11/17/22 23:17, Weiwei Li wrote:
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn16.decode| 18 +++
target/riscv/insn_trans/trans_rvzce.c.inc | 189 +-
target/riscv/translate
On 11/18/22 06:18, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/excp_helper.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target
On 11/18/22 06:18, Richard Henderson wrote:
In addition, use tcg_enabled instead of !kvm_enabled.
Signed-off-by: Richard Henderson
---
Should we strive for this change (tcg_enabled instead of !kvm_enabled)
everywhere when applicable? There's a lot of places in the ppc code where
this can b
On 11/18/22 06:18, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index dc86c1c7db..4e
On Fri, Nov 18 2022, Thomas Huth wrote:
> On 11/11/2022 13.45, Cornelia Huck wrote:
>> Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr.
>>
>> Signed-off-by: Cornelia Huck
>> ---
> ...
>> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
>> index 0ad0ed160387..1c0a7b83b545 100644
>> -
On 11/17/22 23:17, Weiwei Li wrote:
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index,
+ target_ulong next_pc)
+{
+
+#if !defined(CONFIG_USER_ONLY)
+RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
+if (ret != RISCV_EXCP_NONE) {
On 11/18/22 02:13, Daniel Henrique Barboza wrote:
On 11/18/22 06:18, Richard Henderson wrote:
In addition, use tcg_enabled instead of !kvm_enabled.
Signed-off-by: Richard Henderson
---
Should we strive for this change (tcg_enabled instead of !kvm_enabled)
everywhere when applicable? There'
On 11/16/22 15:07, Emanuele Giuseppe Esposito wrote:
Here we introduce generated_co_wrapper_simple, a simplification of g_c_w that
only considers the case where the caller is not in a coroutine.
This simplifies and clarifies a lot when the caller is a coroutine or not, and
in the future will hope
The old URL wasn't stable. I suspect the current URL will only be
stable for a few months so maybe we need another strategy for hosting
rootfs snapshots?
Signed-off-by: Alex Bennée
---
tests/avocado/boot_linux_console.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tes
On 2022/11/18 18:24, Richard Henderson wrote:
On 11/17/22 23:17, Weiwei Li wrote:
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index,
+ target_ulong next_pc)
+{
+
+#if !defined(CONFIG_USER_ONLY)
+ RISCVException ret = smstateen_acc_ok(env, 0, SM
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode | 8
target/riscv/
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode | 8
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++
2 files changed, 22
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v5
To test Zc* implementation, spe
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 4 ++
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8 ++--
2 files changed, 8 insertions(+), 4 deletions
Add encode and trans* functions support for Zcb instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode| 24 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++
target/riscv/tra
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Cc: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h | 6
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 287 +-
1 file changed, 286 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/d
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1ab04ab246..b9e41df96c 100644
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode| 18 +++
target/riscv/insn_trans/trans_rvzce.c.inc | 189 +-
target/riscv/translate.c
On Wed, 16 Nov 2022 20:39:29 +0100 (CET)
BALATON Zoltan wrote:
> On Wed, 16 Nov 2022, Igor Mammedov wrote:
>
> > Code has not been used practically since its inception (2004)
> > f2aa58c6f4a20 UniNorth PCI bridge support
> > or maybe even earlier, but it was consuming contributors time
> > as Q
On Thu, 17 Nov 2022 22:51:46 +0100
Volker Rümelin wrote:
> > From: Igor Mammedov
> >
> > PCI-ISA bridges that are built in PIIX/Q35 are building its own AML
> > using AcpiDevAmlIf interface. Now build_append_pci_bus_devices()
> > gained AcpiDevAmlIf interface support to get AML of devices atached
On Friday, November 18, 2022 9:42:26 AM CET Greg Kurz wrote:
> On Fri, 11 Nov 2022 12:22:08 +0800
> Bin Meng wrote:
>
> > These are not used anywhere in the source tree. Drop them.
> >
> > Signed-off-by: Bin Meng
> > ---
> >
>
> This one could even go through the trivial tree right
> away IMH
Chao Peng writes:
> On Thu, Nov 17, 2022 at 03:08:17PM +, Alex Bennée wrote:
>>
>> >> >> > +
>> >> >> > +/* KVM_EXIT_MEMORY_FAULT */
>> >> >> > +struct {
>> >> >> > + #define KVM_MEMORY_EXIT_FLAG_PRIVATE (1 << 0)
>> >> >> > +__u32 flags;
>
Richard Henderson writes:
> Create a wrapper for locking/unlocking the iothread lock.
>
> Signed-off-by: Richard Henderson
> ---
> Cc: Paolo Bonzini (maintainer:Main loop)
You might want to review Paolo's comments from:
Subject: [RFC PATCH] main-loop: introduce WITH_QEMU_IOTHREAD_LOCK
D
On Friday, November 18, 2022 10:29:51 AM CET Greg Kurz wrote:
> On Fri, 11 Nov 2022 12:22:11 +0800
> Bin Meng wrote:
>
> > With this new QemuFd_t type, it significantly reduces the number of
>
> I cannot find the definition of this type, nor the definition of
> qemu_fd_invalid(). Missing patch ?
Richard Henderson writes:
> Create a wrapper for locking/unlocking the iothread lock.
>
> Signed-off-by: Richard Henderson
> ---
> Cc: Paolo Bonzini (maintainer:Main loop)
> ---
> include/qemu/main-loop.h | 29 +
> 1 file changed, 29 insertions(+)
>
> diff --git a
On Sun, 23 Oct 2022 at 16:37, wrote:
>
> From: Tobias Röhmel
>
> Signed-off-by: Tobias Röhmel
This patch is basically the right shape, but there's a big
simplification you can make and then a bunch of minor tweaks.
> ---
> target/arm/cpu.c | 26 +++-
> target/arm/cpu.h | 12 ++
> ta
On Sun, 23 Oct 2022 at 16:37, wrote:
>
> From: Tobias Röhmel
>
> All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
>
> Signed-off-by: Tobias Röhmel
> ---
> target/arm/cpu_tcg.c | 42 ++
> 1 file changed, 42 insertions(+)
Review
On 18/11/2022 11.14, Cornelia Huck wrote:
On Fri, Nov 18 2022, Thomas Huth wrote:
On 11/11/2022 13.45, Cornelia Huck wrote:
Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
...
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0ad0ed160387
On 18/11/2022 12.33, Alex Bennée wrote:
The old URL wasn't stable. I suspect the current URL will only be
stable for a few months so maybe we need another strategy for hosting
rootfs snapshots?
Looking at
http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/
there are only i
Hi,
starting from this commit 69e1c14aa2 ("virtio: core: vq reset feature
negotation support"), vhost-user-vsock and vhost-vsock fails while
setting the device features, because VIRTIO_F_RING_RESET is not masked.
I'm not sure vsock is the only one affected.
We could fix in two ways:
1) Masking
On Fri, Nov 18, 2022 at 3:32 PM Stefano Garzarella wrote:
>
> Hi,
> starting from this commit 69e1c14aa2 ("virtio: core: vq reset feature
> negotation support"), vhost-user-vsock and vhost-vsock fails while
> setting the device features, because VIRTIO_F_RING_RESET is not masked.
vhost-vsock issu
From: Longpeng
This allows the vhost device to batch the setup of all its host notifiers.
This significantly reduces the device starting time, e.g. the vhost-vDPA
generic device [1] start time reduce from 376ms to 9.1ms for a VM with
64 vCPUs and 3 vDPA device(64vq per device).
[1] https://www.m
On Fri, 18 Nov 2022 14:08:36 +0100
Igor Mammedov wrote:
> On Thu, 17 Nov 2022 22:51:46 +0100
> Volker Rümelin wrote:
[...]
> > since this patch SeaBIOS no longer detects the PS/2 keyboard. This means
> > there's no keyboard in SeaBIOS, GRUB or FreeDOS. OVMF and Linux detect
> > the PS/2 keyboa
Am 18/11/2022 um 11:57 schrieb Paolo Bonzini:
> On 11/16/22 15:07, Emanuele Giuseppe Esposito wrote:
>> Here we introduce generated_co_wrapper_simple, a simplification of
>> g_c_w that
>> only considers the case where the caller is not in a coroutine.
>> This simplifies and clarifies a lot when
On Sun, 23 Oct 2022 at 16:37, wrote:
>
> From: Tobias Röhmel
>
> Thanks again for all the help!
>
> Here is v4:
> 2. Made patch cleaner
> 3. Changed commit message
> 4. Replaced V8_R flag with ARM_FEATURE_PMSA|ARM_FEATURE_V8
> 5.
> Reworked the code to use existing pmsav7 variables
> Added migrat
On Sun, 23 Oct 2022 at 16:37, wrote:
>
> From: Tobias Röhmel
>
> Add PMSAv8r translation.
>
> Signed-off-by: Tobias Röhmel
> ---
> target/arm/ptw.c | 130 +++
> 1 file changed, 110 insertions(+), 20 deletions(-)
>
> diff --git a/target/arm/ptw.c b/tar
On Fri, Nov 18, 2022 at 4:01 PM Emanuele Giuseppe Esposito
wrote:
> > - generated_co_wrapper_simple -> coroutine_wrapper
> > - generated_co_wrapper_blk -> coroutine_wrapper_mixed
> > - generated_co_wrapper -> coroutine_wrapper_mixed_bdrv
> >
> > ? It is not clear to me yet if you will have bdrv_*
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> Fix typos, add background information
>
> Signed-off-by: Axel Heider
> --
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> remove unused defines, add needed defines
>
> Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> Signed-off-by: Axel Heider
> ---
> hw/timer/imx_epit.c | 27 +++
> 1 file changed, 11 insertions(+), 16 deletions(-)
>
> diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
> index 8ec770f674..2
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> Signed-off-by: Axel Heider
> ---
> hw/timer/imx_epit.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
> index 2e9dae0bc8..5315d9633e 100644
> --- a/hw/timer/imx_epit
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> Signed-off-by: Axel Heider
> ---
> hw/timer/imx_epit.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
> index 5315d9633e..6af460946f 100644
> ---
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> The CNT register is a read-only register. There is no need to
> store it's value, it can be calculated on demand.
> The calculated frequency is needed temporarily only.
This patch bumps the vmstate version ID for the devic
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> - inline software reset
> - make hardware reset invoke software reset
> - simplify code flow
I think this patch is fixing a bug, right? We weren't
previously clearing CR for the hardware reset. If so,
that's worth noting i
On Fri, Nov 18, 2022, Alex Bennée wrote:
>
> Chao Peng writes:
>
> > On Thu, Nov 17, 2022 at 03:08:17PM +, Alex Bennée wrote:
> >> >> I think this should be explicit rather than implied by the absence of
> >> >> another flag. Sean suggested you might want flags for RWX failures so
> >> >> ma
On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote:
>
> From: Axel Heider
>
> Signed-off-by: Axel Heider
> ---
> hw/timer/imx_epit.c | 211
> 1 file changed, 115 insertions(+), 96 deletions(-)
Good idea (unfortunate that git diff has not shown the chang
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