Hi Conor,
On 12/11/22 14:34, Conor Dooley wrote:
From: Conor Dooley
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usual
On 12/11/22 12:40, Brad Smith wrote:
qga: Add initial OpenBSD and NetBSD support
Signed-off-by: Brad Smith
---
meson.build | 2 +-
qga/commands-bsd.c | 5 +
qga/commands-posix.c | 9 +++--
qga/main.c | 6 +++---
4 files changed, 16 insertions(+), 6 deletions(-
On 11/11/22 19:25, Alex Bennée wrote:
We can derive the correct CPU from CPUARMState so lets not rely on
current_cpu.
Signed-off-by: Alex Bennée
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 11/11/22 19:25, Alex Bennée wrote:
Both of these functions deal with CPU based access (as is evidenced by
the secure check straight after). Use the new MEMTXATTRS_CPU
constructor to ensure the correct CPU id is filled in should it ever
be needed by any devices later.
Signed-off-by: Alex Benné
On 11/11/22 19:25, Alex Bennée wrote:
Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
with CPU based access. Use the new MEMTXATTRS_CPU constructor to
ensure the correct CPU id is filled in should it ever be needed by any
devices later.
Signed-off-by: Alex Bennée
---
targe
The upcoming capstone 5.0 drops support for the old way
of including its header, due to this change:
https://github.com/capstone-engine/capstone/commit/6656bcb63ab4e87dc6079bd6b6b12cc8dd9b2ad8
The official way is to use
This change has already been proposed before, see
https://patchwork.kernel.or
On 12/11/22 06:50, Richard Henderson wrote:
On 11/12/22 04:25, Alex Bennée wrote:
This is simulating a bus master writing data back into system memory.
Mark it as such.
Signed-off-by: Alex Bennée
---
hw/audio/intel-hda.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
On 11/11/22 19:25, Alex Bennée wrote:
This allows us to drop the current_cpu hack and properly model an
invalid access to the vapic.
Signed-off-by: Alex Bennée
---
hw/i386/kvmvapic.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/i386/kvmvapic.c b
On 11/11/22 19:25, Alex Bennée wrote:
Some of the callbacks need a CPUState so extend the interface so we
can pass that down rather than relying on current_cpu hacks.
Signed-off-by: Alex Bennée
---
include/hw/isa/apm.h | 2 +-
hw/acpi/ich9.c | 1 -
hw/acpi/piix4.c | 2 +-
hw/
The upcoming capstone 5.0 drops support for the old way
of including its header, due to this change:
https://github.com/capstone-engine/capstone/commit/6656bcb63ab4e87dc6079bd6b6b12cc8dd9b2ad8
The official way is to use
This change has already been proposed before, see
https://patchwork.kernel.or
On Sun, Nov 13, 2022 at 08:30:42PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Conor,
>
> On 12/11/22 14:34, Conor Dooley wrote:
> > From: Conor Dooley
> >
> > The system controller on PolarFire SoC is access via a mailbox. The
> > control registers for this mailbox lie in the "IOSCB" region & the
On 11/13/22 12:32, Weiwei Li wrote:
+} else if ((get_xl_max(ctx) == MXL_RV32) &&
+!ctx->cfg_ptr->ext_zcf &&
+(((opcode & 0xe003) == 0x6000) ||
+ ((opcode & 0xe003) == 0x6002) ||
+ ((opcode & 0xe003) == 0xe000) ||
+ ((opcode & 0xe
On Fri, Nov 11, 2022 at 10:20 PM Frédéric Pétrot
wrote:
>
> Commit 40244040 changed the way the S irqs are numbered. This breaks when
> using numa configuration, e.g.:
> ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
> -m 2G -smp cpus=16 \
>
The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.
Get rid of the unused dt property which may lead to confusion.
[1]
https://lore.kernel.org/lkml/2022044207.1478350-5-apa...@ventanamicro.com/
> -Original Message-
> From: Ilya Dryomov
> Sent: 11 November 2022 15:01
> To: Or Ozeri
> Cc: qemu-devel@nongnu.org; qemu-bl...@nongnu.org; Danny Harnik
>
> Subject: [EXTERNAL] Re: [PATCH v1] block/rbd: Add support for layered
> encryption
>
> I don't understand the need for this char
Starting from ceph Reef, RBD has built-in support for layered encryption,
where each ancestor image (in a cloned image setting) can be possibly
encrypted using a unique passphrase.
A new function, rbd_encryption_load2, was added to librbd API.
This new function supports an array of passphrases (vi
On Fri, 11 Nov 2022 at 07:46, Philippe Mathieu-Daudé wrote:
>
> From: Philippe Mathieu-Daudé
>
> GCC 8 added a -Wstringop-truncation warning:
>
> The -Wstringop-truncation warning added in GCC 8.0 via r254630 for
> bug 81117 is specifically intended to highlight likely unintended
> uses of
W dniu 9.11.2022 o 14:35, Leif Lindholm pisze:
We have mainly (well, as will become clear, in fact "exclusively") been using
sbsa-ref with the "max" CPU. But sbsa-ref was created with a default CPU of
Cortex-A57, which we have not updated along the way.
However, the "max" cpu has seen a bug whe
Hi qemu team：
Recently, during the development based on virtio net/vhost net, it was
found that when virtio enabled multiple queues, there was always another
queue whose interrupts were not triggered, and no useful logs were found.
The interrupt statistics in Guest are as follows:
19 matches
Mail list logo
