The glibc on the hppa platform uses the "iitlbp %r0,(%sr0, %r0)"
assembler instruction as ABORT_INSTRUCTION.
If this (in userspace context) illegal assembler statement is found,
dump the registers and report the failure to userspace the same way as
the Linux kernel on physical hardware.
For other
On 25/10/2022 16.28, Amarjargal Gundjalam wrote:
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Reviewed-by: Daniel P. Berrangé
Signed-off-by: A
On 25/10/2022 16.28, Amarjargal Gundjalam wrote:
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Reviewed-by: Daniel P. Berrangé
Signed-off-by: A
On 12/09/2022 14.26, Milica Lazarevic wrote:
Hi,
This patchset converts the nanomips disassembler to plain C. C++ features
like class, std::string type, exception handling, and function overloading
have been removed and replaced with the equivalent C code.
Hi Philippe, hi Stefan,
as far as I
blk_set_enable_write_cache() is defined as GLOBAL_STATE_CODE
but can be invoked from iothreads when handling scsi requests.
This triggers an assertion failure:
0x7fd6c3515ce1 in raise () from /lib/x86_64-linux-gnu/libc.so.6
0x7fd6c34ff537 in abort () from /lib/x86_64-linux-gnu/libc.so.6
These patches are to support vIOMMU in vdpa device
changes in V3
1. Move function vfio_get_xlat_addr to memory.c
2. Use the existing memory listener, while the MR is
iommu MR then call the function iommu_region_add/
iommu_region_del
changes in V4
1.make the comments in vfio_get_xlat_addr more gen
Add support for vIOMMU. add the new function to deal with iommu MR.
- during iommu_region_add register a specific IOMMU notifier,
and store all notifiers in a list.
- during iommu_region_del, compare and delete the IOMMU notifier from the list
Verified in vp_vdpa and vdpa_sim_net driver
Signed-o
Move the function vfio_get_xlat_addr to softmmu/memory.c, and
change the name to memory_get_xlat_addr().So we can use this
function in other devices,such as vDPA device.
Signed-off-by: Cindy Lu
---
hw/vfio/common.c | 92 ++-
include/exec/memory.h | 4
On 24/10/2022 11.02, Daniel P. Berrangé wrote:
On Sat, Oct 22, 2022 at 02:03:50PM -0300, Daniel Henrique Barboza wrote:
'make check-avocado' will download any images that aren't present in the
cache via 'get-vm-images' in tests/Makefile.include. The target that
downloads fedora 31 images, get-vm
ping
On Wed, Aug 31, 2022 at 11:33 AM Vadim Rozenfeld
wrote:
> Just a bit more info related to this issue.
> Below is a quote from my previous conversation with Yan
>
>
> QEMU RTC function periodic_timer_update is calling in response
> to Windows HAL calls
> _HalpRtcArmTimer@16
> and
> _HalpRtc
Hi All:
This series tries to introduce PASID support for Intel IOMMU. The work
is based on the previous scalabe mode support by implement the
ECAP_PASID. A new "x-pasid-mode" is introduced to enable this
mode. All internal vIOMMU codes were extended to support PASID instead
of the current RID2PASI
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus struct
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during initialization. So
let's don't warn in this case.
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/i386
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
with PASID
2) tag IOTLB with PASID
3) PASID cache and its flush
4) PASID bas
We used to have a macro for VTD_PE_GET_FPD_ERR() but it has an
internal goto which prevents it from being reused. This patch convert
that macro to a dedicated function and let the caller to decide what
to do (e.g using goto or not). This makes sure it can be re-used for
other function that requires
Am 27.10.2022 um 04:45 hat Bin Meng geschrieben:
> Hi Kevin,
> [...]
> Will you queue this patch via the block tree?
Just to be sure, you mean only patch 5? Yes, I can do that.
Kevin
On 24/10/2022 21.25, Janis Schoetterl-Glausch wrote:
On Wed, 2022-10-12 at 18:20 +0200, Pierre Morel wrote:
In the S390x CPU topology the core_id specifies the CPU address
and the position of the core withing the topology.
Let's build the topology based on the core_id.
s390x/cpu topology: core_
Vikram Garhwal writes:
> Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
> TPM emulator and connects to swtpm running on host machine via chardev socket
> and support TPM functionalities for a guest domain.
>
> Extra command line for aarch64 xenpv QEMU to connect
On Thu, Oct 27, 2022 at 3:41 PM Cindy Lu wrote:
>
> Add support for vIOMMU. add the new function to deal with iommu MR.
> - during iommu_region_add register a specific IOMMU notifier,
> and store all notifiers in a list.
> - during iommu_region_del, compare and delete the IOMMU notifier from the
On Thu, Oct 27, 2022 at 3:41 PM Cindy Lu wrote:
>
> Move the function vfio_get_xlat_addr to softmmu/memory.c, and
> change the name to memory_get_xlat_addr().So we can use this
> function in other devices,such as vDPA device.
>
> Signed-off-by: Cindy Lu
Acked-by: Jason Wang
> ---
> hw/vfio/co
On 12/10/2022 18.21, Pierre Morel wrote:
The guest can use the STSI instruction to get a buffer filled
with the CPU topology description.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
---
include/hw/s390x/cpu-topology.h | 3 +
On 12/10/2022 18.21, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pierre Morel
Reviewed-by: Nico Boehr
Revie
On Thu, Oct 27, 2022 at 3:55 PM Kevin Wolf wrote:
>
> Am 27.10.2022 um 04:45 hat Bin Meng geschrieben:
> > Hi Kevin,
> > [...]
> > Will you queue this patch via the block tree?
>
> Just to be sure, you mean only patch 5? Yes, I can do that.
>
Yes, only this one. Thank you.
Regards,
Bin
Am 16. September 2022 14:36:05 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 12/9/22 21:50, Bernhard Beschow wrote:
>> Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow
>> :
>
>>> Testing done:
>>>
>>> * `qemu-system-ppc -machine pegasos2 -rtc base=localtime -device
>>> ati-vga,guest_hwcu
On Thu, Oct 27, 2022 at 7:52 AM Mayuresh Chitale
wrote:
>
> Currently the single and multi letter ISA extensions exposed to the guest
> vcpu don't confirm to the KVM policies. This patchset updates the kvm headers
> and applies policies set in KVM to the extensions exposed to the guest.
>
> Mayure
Vikram Garhwal writes:
> Hi,
> This series add xenpv machine for aarch64. Motivation behind creating xenpv
> machine with IOREQ and TPM was to enable each guest on Xen aarch64 to have
> it's
> own unique and emulated TPM.
>
> This series does following:
> 1. Moved common xen functionalitie
Julien Grall writes:
> Hi,
>
> There seem to be some missing patches on xen-devel (including the
> cover letter). Is that expected?
>
> On 15/10/2022 06:07, Vikram Garhwal wrote:
>> Add a new machine xenpv which creates a IOREQ server to register/connect with
>> Xen Hypervisor.
>
> I don't like
Vikram Garhwal writes:
> Add a new machine xenpv which creates a IOREQ server to register/connect with
> Xen Hypervisor.
>
> Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
> TPM emulator and connects to swtpm running on host machine via chardev socket
> and supp
Vikram Garhwal writes:
> From: Stefano Stabellini
>
> On ARM it is possible to have a functioning xenpv machine with only the
> PV backends and no IOREQ server. If the IOREQ server creation fails continue
> to the PV backends initialization.
>
> Signed-off-by: Stefano Stabellini
> ---
> hw/x
Vikram Garhwal writes:
> From: Stefano Stabellini
>
> In preparation to moving most of xen-hvm code to an arch-neutral location,
> move:
> - shared_vmport_page
> - log_for_dirtybit
> - dirty_bitmap
> - suspend
> - wakeup
>
> out of XenIOState struct as these are only used on x86, especially t
On Thu, Oct 27, 2022 at 09:46:29AM +0200, Thomas Huth wrote:
> On 24/10/2022 11.02, Daniel P. Berrangé wrote:
> > On Sat, Oct 22, 2022 at 02:03:50PM -0300, Daniel Henrique Barboza wrote:
> > > 'make check-avocado' will download any images that aren't present in the
> > > cache via 'get-vm-images' i
On 14.10.22 15:47, David Hildenbrand wrote:
This is a follow-up on "util: NUMA aware memory preallocation" [1] by
Michal.
Setting the CPU affinity of threads from inside QEMU usually isn't
easily possible, because we don't want QEMU -- once started and running
guest code -- to be able to mess up
Vikram Garhwal writes:
> From: Stefano Stabellini
>
> In preparation to moving most of xen-hvm code to an arch-neutral location,
> move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
>
> Also move handle_vmport_ioreq to arch_handle_ioreq.
>
> NOTE: This patch breaks the bui
On Thu, 2022-10-27 at 10:05 +0200, Thomas Huth wrote:
> On 24/10/2022 21.25, Janis Schoetterl-Glausch wrote:
> > On Wed, 2022-10-12 at 18:20 +0200, Pierre Morel wrote:
> > > In the S390x CPU topology the core_id specifies the CPU address
> > > and the position of the core withing the topology.
> >
Vikram Garhwal writes:
> Add CONFIG_XEN for aarch64 device to support build for ARM targets.
So to be clear a --enable-xen only build for any of these binaries
essentially ends up being the same thing just with a slightly less
discombobulating name?
Maybe given there is no real architecture s
On 10/27/22 10:14, Thomas Huth wrote:
On 12/10/2022 18.21, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pi
Vikram Garhwal writes:
> From: Stefano Stabellini
>
> have_xen_pci_passthrough is only used for Xen x86 VMs.
>
> Signed-off-by: Stefano Stabellini
I think this might want to before 11/12. Anyway:
Reviewed-by: Alex Bennée
> ---
> meson.build | 2 ++
> 1 file changed, 2 insertions(+)
>
> d
Hi Peter,
> V8 always implies V7, so we only need to check V7 here.
>From silicon perspective - yes, but as I see in qemu,
ARM_FEATURE_V7 and ARM_FEATURE_V8 are independent bits which do not affect
each
other in arm_feature() and set_feature() so they should be tested
separately.
Did I miss somethi
Vikram Garhwal writes:
> xenstore_record_dm_state() will also be used in aarch64 xenpv machine.
>
> Signed-off-by: Vikram Garhwal
> Signed-off-by: Stefano Stabellini
> ---
> accel/xen/xen-all.c | 2 +-
> include/hw/xen/xen.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff
Vikram Garhwal writes:
> Hi,
> This series add xenpv machine for aarch64. Motivation behind creating xenpv
> machine with IOREQ and TPM was to enable each guest on Xen aarch64 to have
> it's
> own unique and emulated TPM.
>
> This series does following:
> 1. Moved common xen functionalitie
On Thu, 27 Oct 2022 at 10:22, Timofey Kutergin wrote:
> > V8 always implies V7, so we only need to check V7 here.
> From silicon perspective - yes, but as I see in qemu,
> ARM_FEATURE_V7 and ARM_FEATURE_V8 are independent bits which do not affect
> each
> other in arm_feature() and set_feature()
On 10/27/22 05:21, Bernhard Beschow wrote:
Am 16. September 2022 14:36:05 UTC schrieb "Philippe Mathieu-Daudé"
:
On 12/9/22 21:50, Bernhard Beschow wrote:
Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow :
Testing done:
* `qemu-system-ppc -machine pegasos2 -rtc base=localtime
On 10/27/22 16:31, Helge Deller wrote:
The fid instruction (Floating-Point Identify) puts the FPU model and
revision into the Status Register. Since those values shouldn't be 0,
store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
would return.
Signed-off-by: Helge Deller
di
On 10/27/22 11:11, Pierre Morel wrote:
On 10/27/22 10:14, Thomas Huth wrote:
On 12/10/2022 18.21, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case o
From: Brice Goglin
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by h
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:
Brice Goglin: to support -numa without initiators on q35/x86.
https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
https:/
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_hel
The value passed is always true.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 +-
accel/tcg/tb-maint.c | 4 ++--
accel/tcg/translate-all.c | 15 +++
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/i
Add a way to examine the unwind data without actually
restoring the data back into env.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 4 +--
include/exec/exec-all.h | 21 ---
accel/tcg/translate-all.c | 74 ++-
3 files changed, 68
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 5 +
accel/tcg/cpu-exec-common.c | 2 +-
accel/tcg/tr
As per #1269, this affects NetBSD installer boot.
The problem is that one of the x86 acpi callbacks modifies
env->eip during an mmio store, which means that the tracking
that translate.c does is thrown out of whack.
Introduce a method to extract unwind data without the
writeback to env. This isn
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
Signed-off-by: Hesham Almatary
Reviewed-by: Igor Mammedov
---
hw/arm/Kconfig | 1 +
* Expected ACPI Data Table [HMAT]
[000h 4]Signature : "HMAT"[Heterogeneous
Memory Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010
Avoid cpu_restore_state, and modifying env->eip out from
underneath the translator with TARGET_TB_PCREL. There is
some slight duplication from x86_restore_state_to_opc,
but it's just a few lines.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269
Signed-off-by: Richard Henderson
---
t
From: Brice Goglin
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6]
From: Brice Goglin
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
Signed-off-by: Hesham Almatary
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.acpihmat-noinitiator
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | 0
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/PPTT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios-
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_hel
This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.
Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_EFI
Hello Pierre,
On 10/12/22 18:21, Pierre Morel wrote:
The S390 CPU topology accepts the smp.threads argument while
in reality it does not effectively allow multthreading.
Let's keep this behavior for machines older than 7.3 and
refuse to use threads in newer machines until multithreading
is real
On 10/27/22 11:48, Richard Henderson wrote:
On 10/27/22 16:31, Helge Deller wrote:
The fid instruction (Floating-Point Identify) puts the FPU model and
revision into the Status Register. Since those values shouldn't be 0,
store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
wo
Commit 85c4bf8aa6 ("vl: Unlink absolute PID file path") made it a
critical error when the PID file path cannot be resolved. Before this
commit, it was possible to invoke QEMU when the PID file was a file
created with mkstemp that was already unlinked at the time of the
invocation. There might be ot
On Thu, Oct 27, 2022 at 8:54 AM Jason Wang wrote:
>
> On Thu, Oct 27, 2022 at 2:47 PM Eugenio Perez Martin
> wrote:
> >
> > On Thu, Oct 27, 2022 at 6:32 AM Jason Wang wrote:
> > >
> > >
> > > 在 2022/10/26 17:53, Eugenio Pérez 写道:
> > > > Now that qemu can handle and emulate it if the vdpa backen
On 10/26/22 23:36, Alex Bennée wrote:
Richard Henderson writes:
Finish weaning user-only away from PageDesc.
Using an interval tree to track page permissions means that
we can represent very large regions efficiently.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290
Resolves: htt
Hi,
On Tue, Oct 25, 2022 at 4:18 PM Chao Peng wrote:
>
> From: "Kirill A. Shutemov"
>
> Introduce 'memfd_restricted' system call with the ability to create
> memory areas that are restricted from userspace access through ordinary
> MMU operations (e.g. read/write/mmap). The memory content is ex
On Thu, Oct 27 2022, Thomas Huth wrote:
> On 26/10/2022 18.05, Cornelia Huck wrote:
>> +qtest_add_data_func("/arm/max/query-cpu-model-expansion/tag-memory",
>> +NULL, mte_tests_tag_memory_on);
>
> Is it already possible to compile qemu-system-aarch64 with --dis
Hi,
On Tue, Oct 25, 2022 at 4:19 PM Chao Peng wrote:
>
> This new KVM exit allows userspace to handle memory-related errors. It
> indicates an error happens in KVM at guest memory range [gpa, gpa+size).
> The flags includes additional information for userspace to handle the
> error. Currently bit
The helpers for reset_rf, cli, sti, clac, stac are
completely trivial; implement them inline.
Drop some nearby #if 0 code.
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 5 -
target/i386/tcg/cc_helper.c | 41 -
target/i386/tcg/transla
On Tue, Oct 25, 2022 at 4:18 PM Chao Peng wrote:
>
> In memory encryption usage, guest memory may be encrypted with special
> key and can be accessed only by the guest itself. We call such memory
> private memory. It's valueless and sometimes can cause problem to allow
> userspace to access guest
Hi,
On Tue, Oct 25, 2022 at 4:19 PM Chao Peng wrote:
>
> Currently in mmu_notifier validate path, hva range is recorded and then
> checked against in the mmu_notifier_retry_hva() of the page fault path.
> However, for the to be introduced private memory, a page fault may not
> have a hva associat
Hi,
On Tue, Oct 25, 2022 at 4:20 PM Chao Peng wrote:
>
> Expose KVM_MEM_PRIVATE and memslot fields restricted_fd/offset to
> userspace. KVM register/unregister private memslot to fd-based
> memory backing store and responses to invalidation event from
> restrictedmem_notifier to zap the existing
Hi,
On Tue, Oct 25, 2022 at 4:19 PM Chao Peng wrote:
>
> Introduce generic private memory register/unregister by reusing existing
> SEV ioctls KVM_MEMORY_ENCRYPT_{UN,}REG_REGION. It differs from SEV case
> by treating address in the region as gpa instead of hva. Which cases
> should these ioctls
> 2022年10月26日 20:18，Philippe Mathieu-Daudé 写道：
>
> This is a respin of Jiaxun v3 [1] addressing the semihosting review
> comment [2].
>
> [1]
> https://lore.kernel.org/qemu-devel/20210127065424.114125-1-jiaxun.y...@flygoat.com/
> [2]
> https://lore.kernel.org/qemu-devel/5a22bbe1-5023-6fc3-a
On Wed, 26 Oct 2022 at 15:52, Stefan Hajnoczi wrote:
>
> On Tue, 25 Oct 2022 at 12:51, Peter Maydell wrote:
> > target-arm queue:
> > * Implement FEAT_E0PD
> > * Implement FEAT_HAFDBS
>
> A second CI failure:
> libqemu-aarch64-softmmu.fa.p/target_arm_ptw.c.o -MF
> libqemu-aarch64-softmmu.fa.p/
On Fri, Oct 21, 2022 at 05:30:01PM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/s390x/helper.h | 2 +-
> target/s390x/tcg/mem_helper.c | 7 +++
> target/s390x/tcg/translate.c | 6 --
> 3 files changed, 8 insertions(+), 7 deletions(-)
Acked-by
On Fri, Oct 21, 2022 at 05:30:02PM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/s390x/helper.h | 2 +-
> target/s390x/tcg/mem_helper.c | 7 +++
> target/s390x/tcg/translate.c | 7 +--
> 3 files changed, 9 insertions(+), 7 deletions(-)
Acked-b
On 10/27/22 12:02, Richard Henderson wrote:
> Add a way to examine the unwind data without actually
> restoring the data back into env.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/internal.h | 4 +--
> include/exec/exec-all.h | 21 ---
> accel/tcg/translate-all.c | 74
Understood, thank you a lot :)
Best regards
Timofey
On Thu, Oct 27, 2022 at 12:35 PM Peter Maydell
wrote:
> On Thu, 27 Oct 2022 at 10:22, Timofey Kutergin
> wrote:
> > > V8 always implies V7, so we only need to check V7 here.
>
> > From silicon perspective - yes, but as I see in qemu,
> > ARM
27.10.2022 09:40, Laurent Vivier wrote:
..
I tried O_CLOEXEC, but it seems the fd is closed before it is needed by execveat() to re-spawn the process, so it exits with an error (something like
EBADF)
It works here for me with a simple test program:
#include
#include
#include
#include
#defi
On 27/10/22 12:02, Richard Henderson wrote:
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Phili
On Tue, Oct 04, 2022 at 10:32:05AM +0100, Daniel P. Berrangé wrote:
> Various areas of QEMU have a dependency on Linux kernel header
> definitions. This falls under the scope of our supported platforms
> matrix, but historically we've not checked for a minimum kernel
> headers version. This has mad
ping: Jason, are you willing to queue this since it has two
positive reviews.
On Mon, Oct 03, 2022 at 11:06:12AM +0100, Daniel P. Berrangé wrote:
> The current message when using '-net user...' with SLIRP disabled at
> compile time is:
>
> qemu-system-x86_64: -net user: Parameter 'type' expects
On Fri, Oct 21, 2022 at 05:30:03PM +1000, Richard Henderson wrote:
> Make a copy of wout_x1 before modifying it, as wout_x1_P
> emphasizing that it operates on the out/out2 pair. The insns
> that use x1_P are data movement that will not change to Int128.
>
> Signed-off-by: Richard Henderson
> --
On 27/10/22 09:25, Thomas Huth wrote:
On 12/09/2022 14.26, Milica Lazarevic wrote:
Hi,
This patchset converts the nanomips disassembler to plain C. C++ features
like class, std::string type, exception handling, and function
overloading
have been removed and replaced with the equivalent C code
On Wed, 26 Oct 2022 16:47:18 -0400
Gregory Price wrote:
> On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> > On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > > Submitted as an extention to the multi-feature branch maintained
> > > by Jonathan Cameron at:
> >
On Fri, Oct 21, 2022 at 05:30:04PM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tests/tcg/s390x/long-double.c | 24
> tests/tcg/s390x/Makefile.target | 1 +
> 2 files changed, 25 insertions(+)
> create mode 100644 tests/tcg/s390x/long-dou
Begin weaning user-only away from PageDesc.
Since, for user-only, all TB (and page) manipulation is done with
a single mutex, and there is no virtual/physical discontinuity to
split a TB across discontinuous pages, place all of the TBs into
a single IntervalTree. This makes it trivial to find all
On 10/27/22 11:58, Cédric Le Goater wrote:
On 10/27/22 11:11, Pierre Morel wrote:
On 10/27/22 10:14, Thomas Huth wrote:
On 12/10/2022 18.21, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Chan
Continue weaning user-only away from PageDesc.
Use an interval tree to record target data.
Chunk the data, to minimize allocation overhead.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 1 -
accel/tcg/user-exec.c | 99 ---
2 files changed,
On 10/27/22 10:12, Thomas Huth wrote:
On 12/10/2022 18.21, Pierre Morel wrote:
The guest can use the STSI instruction to get a buffer filled
with the CPU topology description.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
---
On Fri, Oct 21, 2022 at 05:30:05PM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/s390x/helper.h | 22 +++
> target/s390x/tcg/fpu_helper.c | 29 ++--
> target/s390x/tcg/translate.c | 49 +++---
>
- Use CPSR.PAN to check for PAN state in aarch32 mode
- throw permission fault during address translation when PAN is
enabled and kernel tries to access user acessible page
- ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN).
Signed-off-by: Timofey Kutergin
---
Finish weaning user-only away from PageDesc.
Using an interval tree to track page permissions means that
we can represent very large regions efficiently.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/967
Resolves: https://gitla
On 10/27/22 12:00, Cédric Le Goater wrote:
Hello Pierre,
On 10/12/22 18:21, Pierre Morel wrote:
The S390 CPU topology accepts the smp.threads argument while
in reality it does not effectively allow multthreading.
Let's keep this behavior for machines older than 7.3 and
refuse to use threads
The only thing that still touches PageDesc in translate-all.c
are some locking routines related to tb-maint.c which have not
yet been moved. Do so now.
Move some code up in tb-maint.c as well, to untangle the maze
of ifdefs, and allow a sensible final ordering.
Move some declarations from exec/t
This page tracking implementation is specific to user-only,
since the system softmmu version is in cputlb.c. Move it
out of translate-all.c to user-exec.c.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 17 ++
accel/tcg/translate-all.c | 350
Copy and simplify the Linux kernel's interval_tree_generic.h,
instantiating for uint64_t.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/interval-tree.h| 99
tests/unit/test-interval-tree.c | 209
util/interval-tree.c| 882 +
On 10/27/22 20:40, Claudio Fontana wrote:
On 10/27/22 12:02, Richard Henderson wrote:
Add a way to examine the unwind data without actually
restoring the data back into env.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 4 +--
include/exec/exec-all.h | 21 ---
Now that PageDesc is not used for user-only, and for system
it is only used for tb maintenance, move the implementation
into tb-main.c appropriately ifdefed.
We have not yet eliminated all references to PageDesc for
user-only, so retain a typedef to the structure without definition.
Signed-off-by
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