The following changes since commit e750a7ace492f0b450653d4ad368a77d6f660fb8:
Merge tag 'pull-9p-20221024' of https://github.com/cschoenebeck/qemu into
staging (2022-10-24 14:27:12 -0400)
are available in the Git repository at:
https://repo.or.cz/qemu/armbru.git tags/pull-qapi-2022-10-25-v2
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/stats.json.
Said commit explains the transfor
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qga/qapi-schema.json.
Said commit explains the tra
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/dump.json.
Said commit explains the transform
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/virtio.json.
Said commit explains the transfo
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/run-state.json.
Said commit explains the tran
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/migration.json.
Said commit explains the tran
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/misc.json.
Said commit explains the transform
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for
tests/qapi-schema/qapi-schema-test.json.
Said comm
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/acpi.py.
Said commit explains the transformat
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/job.json.
Said commit explains the transforma
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/qdev.json and
qapi/qom.json.
Said commit expl
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/tpm.json.
Said commit explains the transforma
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/char.json.
Said commit explains the transform
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/block*.json.
Said commit explains the transfo
Signed-off-by: Markus Armbruster
Reviewed-by: Daniel P. Berrangé
Message-Id: <20221018062849.3420573-29-arm...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
---
scripts/qapi/schema.py | 6 --
1 file changed, 6 deletions(-)
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
inde
Stefan Hajnoczi writes:
> The following CI failures were reported. I think they may be related
> to this pull request:
[...]
They are. v2 sent & fingers crossed. Thanks!
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/audio.json.
Said commit explains the transfor
Signed-off-by: Markus Armbruster
Reviewed-by: Daniel P. Berrangé
Message-Id: <20221018062849.3420573-2-arm...@redhat.com>
---
docs/devel/qapi-code-gen.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst
index cd9b544
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/machine*.json.
Said commit explains the trans
Registering an I/O buffer is only a performance optimization hint but it
is still necessary to return errors when it fails.
Later patches will need to detect errors when registering buffers but an
immediate advantage is that error_report() calls are no longer needed in
block driver .bdrv_register_
Add a function to get the file descriptor for a RAMBlock. Device
emulation code typically uses the MemoryRegion APIs but vhost-style code
may use RAMBlock directly for sharing guest memory with another process.
This new API will be used by the libblkio block driver so it can share
guest memory via
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Make list traversal work when a callback removes a notifier
mid-traversal. This is a cleanup to prevent bugs in the future.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Message-id: 20221013185908.1297568-9-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
hw/core/numa.c |
Vikram Garhwal writes:
> Build fails when have_xen_pci_passthrough is disabled. This is because of
> incorrect build configuration for xen_pt_stub.c.
>
> Signed-off-by: Stefano Stabellini
> Signed-off-by: Vikram Garhwal
Reviewed-by: Alex Bennée
--
Alex Bennée
Avoid bounce buffers when QEMUIOVector elements are within previously
registered bdrv_register_buf() buffers.
The idea is that emulated storage controllers will register guest RAM
using bdrv_register_buf() and set the BDRV_REQ_REGISTERED_BUF on I/O
requests. Therefore no blkio_map_mem_region() cal
When a RAMBlockNotifier is added, ->ram_block_added() is called with all
existing RAMBlocks. There is no equivalent ->ram_block_removed() call
when a RAMBlockNotifier is removed.
The util/vfio-helpers.c code (the sole user of RAMBlockNotifier) is fine
with this asymmetry because it does not rely o
The blkio block driver will need to look up the file descriptor for a
given pointer. This is possible in softmmu builds where the RAMBlock API
is available for querying guest RAM.
Add stubs so tools like qemu-img that link the block layer still build
successfully. In this case there is no guest RA
The only implementor of bdrv_register_buf() is block/nvme.c, where the
size is not needed when unregistering a buffer. This is because
util/vfio-helpers.c can look up mappings by address.
Future block drivers that implement bdrv_register_buf() may not be able
to do their job given only the buffer
Emulated devices and other BlockBackend users wishing to take advantage
of blk_register_buf() all have the same repetitive job: register
RAMBlocks with the BlockBackend using RAMBlockNotifier.
Add a BlockRAMRegistrar API to do this. A later commit will use this
from hw/block/virtio-blk.c.
Signed-
The following changes since commit 79fc2fb685f35a5e71e23629760ef4025d6aba31:
Merge tag 'trivial-branch-for-7.2-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2022-10-25 11:37:17 -0400)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/b
On Thu, Oct 13, 2022 at 02:58:55PM -0400, Stefan Hajnoczi wrote:
> v7:
> - Add nvme-io_uring and virtio-blk-vhost-user syntax examples to commit
> description [Markus]
> - Add missing nvme-io_uring QAPI [Markus, Alberto]
> - Rename mem-regions-pinned to may-pin-mem-regions [Alberto]
> - Fix value/
libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
high-performance disk I/O. It currently supports io_uring,
virtio-blk-vhost-user, and virtio-blk-vhost-vdpa with additional drivers
under development.
One of the reasons for developing libblkio is that other applications
besides QEM
Use the enum type so GDB displays the enum members instead of printing a
numeric constant.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Message-id: 20221013185908.1297568-6-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
include/block/block_int-common.h | 8
1
When a coroutine wakes up it may determine that it must re-queue.
Normally coroutines are pushed onto the back of the CoQueue, but for
fairness it may be necessary to push it onto the front of the CoQueue.
Add a flag to specify that the coroutine should be pushed onto the front
of the CoQueue. A l
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Register guest RAM using BlockRAMRegistrar and set the
BDRV_REQ_REGISTERED_BUF flag so block drivers can optimize memory
accesses in I/O requests.
This is for vdpa-blk, vhost-user-blk, and other I/O interfaces that rely
on DMA mapping/unmapping.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefan
Block drivers may optimize I/O requests accessing buffers previously
registered with bdrv_register_buf(). Checking whether all elements of a
request's QEMUIOVector are within previously registered buffers is
expensive, so we need a hint from the user to avoid costly checks.
Add a BDRV_REQ_REGISTER
Make guest displays disconnected when not visible. Setting ui size to 0
is used to indicate that the display is disconnected. When the VC is
visible again, the ui size is set to associated window's size again which
makes the display reconnected and available to the guest.
Cc: Gerd Hoffmann
Cc: D
From: Jiaxun Yang
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang
Message-Id: <20210127065424.114125-3-jiaxun.y...@flygoat.com>
[PMD: Pass semihosting_get_argc() to bl_gen_jump_kernel()]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 43 ---
When one of the $sp/$a[0..3] register is already set, we might
want bl_gen_jump_kernel() to NOT set it again. Pass a boolean
argument for each register, to allow to optionally set them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 28 +---
hw/m
This patchset adds a new mechanism in gtk/ui that makes it stop
scheduling a render event if VC is invisible and also change the status
of guest display to disconnected so that the guest stop further
submission of new frames.
This prevents the guest (using blob scanout w/ egl fence sync) from bei
This is a respin of Jiaxun v3 [1] addressing the semihosting review
comment [2].
[1]
https://lore.kernel.org/qemu-devel/20210127065424.114125-1-jiaxun.y...@flygoat.com/
[2]
https://lore.kernel.org/qemu-devel/5a22bbe1-5023-6fc3-a41b-8d72ec2bb...@flygoat.com/
*** BLURB HERE ***
Jiaxun Yang (2):
A new flag "visible" that shows visibility status of the gfx console.
The polarity of the flag determines whether the drawing surface should
continuously updated upon scanout flush. The flag is set to 'true' as far as
it is in visible state but set to 'false' if its tab is inactivated or
untabifie
Add a callback for window-state-event that resets vc->gfx.visible when
associated window is minimized and vice versa.
Cc: Gerd Hoffmann
Cc: Daniel P. Berrangé
Cc: Markus Armbruster
Cc: Philippe Mathieu-Daudé
Cc: Marc-André Lureau
Cc: Thomas Huth
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Ki
From: Jiaxun Yang
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang
Message-Id: <20210127065424.114125-4-jiaxun.y...@flygoat.com>
[PMD: Explode addresses/values to ease review/maintainance]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c |
This patch adds the code necessary to cache fsqrt for usage
with hardfpu in Power. It is also the first instruction to
use the new cache instruction system.
fsqrt is an instruction that receives two arguments, one f64 and
one status, and returns f64. This info will be cached inside a new
union in
As can be seem in the mailing thread that added hardfloat support in
QEMU [1], a requirement for it to work is to have float_flag_inexact
set when entering the API in softfloat.c. However, in the same thread,
it was explained that PPC target would not work by default with this
implementation.
The p
This patch adds the code necessary to cache add/sub/mul/div
instructions for usage with hardfpu in Power.
These instructions receives three arguments, two f64 and
one status, and returns f64. This info will be cached inside the
union in env, which grows when other instructions with other
signature
This patch adds the code necessary to cache muladd instructions
for usage with hardfpu in Power.
muladd is an instruction that receives four arguments, three f64 and
one status, and returns f64. This info will be cached inside the
union in env, which grows when other instructions with other
signat
When enabling hardfpu for Power and adding the instruction caching
feature, it will be necessary to uncache when the instruction
is garanteed to be executed in softfloat. If the cache is not cleared
in this situation, it could lead to a previous instruction being
reexecuted and yield a different re
Change the build conditional from softfloat.c, allowing TARGET_PPC
to use hardfpu. For PPC, this is only implemented in linux-user.
Signed-off-by: Víctor Colombo
---
fpu/softfloat.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
i
Am 25.10.22 um 09:44 schrieb Marc-André Lureau:
Hi
On Tue, Oct 25, 2022 at 12:31 AM Volker Rümelin wrote:
Am 24.10.22 um 10:13 schrieb Marc-André Lureau:
Hi
On Mon, Oct 24, 2022 at 9:28 AM Volker Rümelin
wrote:
Test if the audio subsystem can handle extreme up- and down-
sampling
On Tue, Oct 11, 2022 at 10:05:22PM +0200, Laurent Vivier wrote:
> "-netdev socket" only supports inet sockets.
>
> It's not a complex task to add support for unix sockets, but
> the socket netdev parameters are not defined to manage well unix
> socket parameters.
Acked-by: Michael S. Tsirkin
Hi
On Wed, Oct 26, 2022 at 12:55 PM wrote:
> From: Marc-André Lureau
>
> The following changes since commit
> e750a7ace492f0b450653d4ad368a77d6f660fb8:
>
> Merge tag 'pull-9p-20221024' of https://github.com/cschoenebeck/qemu
> into staging (2022-10-24 14:27:12 -0400)
>
> are available in the
Bernhard posted a series merging both PIIX3/PIIX4 models
in one [1]. Due to Malta-specific board code forced into
the PIIX4 reset values, Bernhard had to include an array
of "register values at reset" as a class property. This
is not wrong, but to model properly the model, we should
simply use the
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included values specific to
the Malta board.
On 26/10/22 21:46, Philippe Mathieu-Daudé wrote:
Bernhard posted a series merging both PIIX3/PIIX4 models
in one [1]. Due to Malta-specific board code forced into
the PIIX4 reset values, Bernhard had to include an array
of "register values at reset" as a class property. This
is not wrong, but to
The PIIX4 PCI-ISA bridge function is always located at 10:0.
Since we want to re-use its address, add the PIIX4_PCI_DEVFN
definition.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Signed-off-by: Philippe Mathie
Am 26. Oktober 2022 17:18:14 UTC schrieb Daniel Henrique Barboza
:
>Hi,
>
>Since this is being sent to qemu-ppc and has to do with e500 I decided to
>take a look. I acked the e500 related patches, 5 and 7. Patch 6 LGTM as well
>but I'd rather not ack it it's SD specific code.
>
>I'll send a Pow
Am 24. Oktober 2022 07:35:48 UTC schrieb "Philippe Mathieu-Daudé"
:
>Hi Bernhard,
>
>On 22/10/22 17:04, Bernhard Beschow wrote:
>> Having an i8259 proxy allows for ISA PICs to be created and wired up in
>> southbridges. This is especially interesting for PIIX3 for two reasons:
>> First, the sou
On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote:
> Current code sets to STORAGE_EXPRESS and then overrides it.
>
> Signed-off-by: Gregory Price
If you expect me to merge it you need to CC me.
Also, do we need this separately from the series?
> ---
> hw/mem/cxl_type3.c | 3 +--
>
He does but in the end he sends patches not pull requests.
I don't care really as long as someone will send it up.
On Wed, Oct 26, 2022 at 08:09:45PM +, Gregory Price wrote:
> I believe this was dropped from my line because Jonathan carried a similar
> commit on his branch.
>
> Happy to pus
On Wed, Oct 12, 2022 at 05:37:57PM +0200, Markus Armbruster wrote:
> Markus Armbruster (4):
> qom: Improve error messages when property has no getter or setter
> backends: Improve error messages when property can no longer be set
> qtest: Improve error messages when property can not be set ri
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://urldefense.com/v3/__https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24__;!!EwVzqGoTKBqv-0DWAJBm!RyiGL5B1XmQnVFwgxikKJeosPMKtoO1cTr61
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
BTW pls set subject prefix for all patches, and put it before the patch #.
-v parameter
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 29 +++--
include/hw/pci/pci.h | 12 ++--
2 files changed, 9 insertions(+), 32 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 8ee2171011..8ff71e4553 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/i82801b11.c | 14 ++
h
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8 deletion
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msix_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msix.c | 8 ++--
1 file changed, 2 insertions(+), 6 deleti
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Indeed
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
I believe this was dropped from my line because Jonathan carried a similar
commit on his branch.
Happy to push it up again as a separate commit if that is what you want.
Noted for the future on upstreams
-Original Message-
From: Michael S. Tsirkin
Sent: Wednesday, October 26, 2022 4:0
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of shpc_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
hw/pci-bridge/pcie_pci_bridg
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of slotid_cap_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/slotid_cap.c | 8 ++--
1 file changed, 2 insertions(
On Fri, Oct 14, 2022 at 03:20:02PM +0200, Laurent Vivier wrote:
> When virtio_net_flush_tx() reaches the tx_burst value all the queue is
> not flushed and nothing restart the timer or the bottom half function.
>
> For BH, this is only missing in the virtio_net_tx_complete() function.
> For the tim
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of a PCIe function which calls
pci_add_capability() in turn is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
Acked-by: Jonathan Cameron (for CXL parts)
---
docs/pcie_sriov.txt
On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
> During migration the virtio device state can be restored before we
> restart the VM. As no devices can be running while the VM is paused it
> makes sense to bail out early in that case.
>
> This returns the order introduced in:
>
> 9
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
>
I am not supposed to merge this patchset yet, right?
That branch has a bunch of patc
On Tue, Oct 25, 2022 at 08:47:34PM -0400, Gregory Price wrote:
> Early-boot e820 records will be inserted by the bios/efi/early boot
> software and be reported to the kernel via insert_resource. Later, when
> CXL drivers iterate through the regions again, they will insert another
> resource and ma
On Tue, Oct 25, 2022 at 10:55:18AM -0600, Alex Williamson wrote:
> On Wed, 26 Oct 2022 00:37:33 +0800
> Cindy Lu wrote:
> > diff --git a/softmmu/memory.c b/softmmu/memory.c
> > index 7ba2048836..03940c551d 100644
> > --- a/softmmu/memory.c
> > +++ b/softmmu/memory.c
> ...
> > +/*
> > +
On Tue, Oct 25, 2022 at 11:13:42PM +0800,
Chao Peng wrote:
> When private/shared memory are mixed in a large page, the lpage_info may
> not be accurate and should be updated with this mixed info. A large page
> has mixed pages can't be really mapped as large page since its
> private/shared pages
On Thu, Oct 20, 2022 at 12:34:22PM +0200, Eugenio Pérez wrote:
> A gratuitous ARP is recommended after a live migration to reduce the amount of
> time needed by the network links to be aware of the new location. A hypervisor
> may not have the knowledge of the guest network configuration, and this
On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://urldefense.com/v3/__https://gitlab.com/jic23/qemu/-/tree/cxl
On Wed, Oct 26, 2022 at 04:20:40PM -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
> >
>
> I
On Wed, Oct 26, 2022 at 11:53:00AM +0200, Eugenio Pérez wrote:
> The net config space is already copied from the device so it can me modified
> by qemu. In particular, this is already done to fix cases where the NIC does
> not expose the right fields.
>
> It's trivial to emulate _F_STATE with qemu
On Thu, Oct 20, 2022 at 05:52:47PM +0200, Eugenio Pérez wrote:
> Event idx helps to reduce the number of notifications between the device
> and the driver. It allows them to specify an index on the circular
> descriptors rings where to issue the notification, instead of a single
> binary indicator.
Early-boot e820 records will be inserted by the bios/efi/early boot
software and be reported to the kernel via insert_resource. Later, when
CXL drivers iterate through the regions again, they will insert another
resource and make the RESERVED memory area a child.
This RESERVED memory area causes
On Wed, Oct 26, 2022 at 04:11:29PM -0400, Michael S. Tsirkin wrote:
> He does but in the end he sends patches not pull requests.
> I don't care really as long as someone will send it up.
>
Jonathan will submit this, it's not a critical issue so it can wait for
the larger feature set.
On Wed, Oct 26, 2022 at 9:46 PM Philippe Mathieu-Daudé
wrote:
> IRQRC[A:D] registers reset value is 0x80. We were forcing
> the MIPS Malta machine routing to be able to boot a Linux
> kernel without any bootloader.
> We now have these registers initialized in the Malta machine
> write_bootloader(
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