SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be
immediates or taken from an XMM register. In both cases, the fields are
6-bit wide and the top two bits in the byte are ignored. translate.c is
doing that correctly for the immediate case, but not for the XMM case, so
f
On 9/14/22 20:25, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 13:44, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/13/22 21:52, BALATON Zoltan wrote:
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is
On 9/14/22 20:32, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 13:44, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/13/22 21:52, BALATON Zoltan wrote:
The do_init parameter of ppc4xx_sdram_i
INSERTQ is defined to not modify any bits in the lower 64 bits of the
destination, other than the ones being replaced with bits from the
source operand. QEMU instead is using unshifted bits from the source
for those bits.
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 10 +-
From: Frank Chang
After RISCVException enum is introduced, riscv_csrrw_debug() returns
RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
should check the result against RISCV_EXCP_NONE instead of value 0.
Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
whe
ping
Kevin, Hanna, I hope you have time to take a look.
https://lists.nongnu.org/archive/html/qemu-block/2022-09/msg00021.html
On Thu, Sep 1, 2022 at 5:32 PM Nir Soffer wrote:
>
> Since blkhash is available only via copr now, the new command is added as
> optional feature, built only if blkhas
On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
On 14/9/22 13:34, BALATON Zoltan wrote:
Move the check for valid memory sizes from board to sdram controller
init. Board now only checks for additional restrictions imposed by
firmware then sdram init checks for valid sizes for SoC.
Signed-off-
On Sun, 18 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 20:32, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 13:44, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/13/22 21:52, BALATON Zoltan w
On Sun, 18 Sep 2022, BALATON Zoltan wrote:
On Sun, 18 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 20:32, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 13:44, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goate
On Tue, Feb 22, 2022 at 3:15 PM Carlo Bramini
<1772...@bugs.launchpad.net> wrote:
>
> I'm also trying to run QEMU for emulating Raspberry PI, but I'm still unable
> to make working external USB devices like keyboard and mouse.
> Unlike previous users, I'm not using a linux distro but Microsoft Win
On 15/9/22 17:25, Bernhard Beschow wrote:
Gives users more fine-grained control over what should be compiled into
QEMU.
Signed-off-by: Bernhard Beschow
---
configs/devices/ppc-softmmu/default.mak | 3 ++-
hw/ppc/Kconfig | 8
hw/ppc/meson.build
On 15/9/22 17:25, Bernhard Beschow wrote:
Having a dedicated config switch makes dependency handling cleaner.
Signed-off-by: Bernhard Beschow
---
hw/gpio/Kconfig | 3 +++
hw/gpio/meson.build | 2 +-
hw/ppc/Kconfig | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
Reviewed-b
On 15/9/22 17:25, Bernhard Beschow wrote:
The sudden change of topics is slightly confusing and makes the
networking information less visible. So separate the networking chapter
to improve comprehensibility.
Signed-off-by: Bernhard Beschow
---
docs/system/ppc/ppce500.rst | 3 +++
1 file chan
On 15/9/22 17:25, Bernhard Beschow wrote:
Now that the MPC8544DS board also has a platform bus, the if statement
was always true.
s/was/is/.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/ppc/e500.c | 30 ++
hw/ppc/e500.h
On 15/9/22 17:25, Bernhard Beschow wrote:
These defines aren't used outside of sdhci.c, so can be defined there.
Signed-off-by: Bernhard Beschow
---
hw/sd/sdhci-internal.h | 20
hw/sd/sdhci.c | 19 +++
2 files changed, 19 insertions(+), 20 delet
On 15/9/22 17:25, Bernhard Beschow wrote:
This series adds support for -pflash and direct SD card access to the
PPC e500 boards. The idea is to increase compatibility with "real" firmware
images where only the bare minimum of drivers is compiled in.
The series is structured as follows:
Patches
The png_destroy_write_struct() function frees all memory used by
libpng. Don't use the glib auto cleanup mechanism to free the
memory allocated by libpng again. For the pixman image, use only the
auto cleanup mechanism and remove the qemu_pixman_image_unref()
function call to prevent another double
I send this patch to continue our works discussed about two years ago.
Due to my personal issue, I couldn't noticed that there were some issues
in license statements in the code.
I am very sorry for my late response and politely request to check this patch.
Signed-off-by: Heecheol Yang
---
hw
Am 14/09/2022 um 14:36 schrieb Vladimir Sementsov-Ogievskiy:
> On 8/26/22 16:20, Emanuele Giuseppe Esposito wrote:
>> Now that the API offers also _locked() functions, take advantage
>> of it and give also the caller control to take the lock and call
>> _locked functions.
>>
>> This makes sense
Am 14/09/2022 um 15:25 schrieb Vladimir Sementsov-Ogievskiy:
> On 8/26/22 16:20, Emanuele Giuseppe Esposito wrote:
>> In order to make it thread safe, implement a "fake rwlock",
>> where we allow reads under BQL *or* job_mutex held, but
>> writes only under BQL *and* job_mutex.
>>
>> The only wr
Am 15/09/2022 um 16:52 schrieb Vladimir Sementsov-Ogievskiy:
> On 8/26/22 16:21, Emanuele Giuseppe Esposito wrote:
>> Change the job_{lock/unlock} and macros to use job_mutex.
>>
>> Now that they are not nop anymore, remove the aiocontext
>> to avoid deadlocks.
>>
>> Therefore:
>> - when possibl
Am 14/09/2022 um 16:28 schrieb Vladimir Sementsov-Ogievskiy:
> On 8/26/22 16:21, Emanuele Giuseppe Esposito wrote:
>> These public functions are not used anywhere, thus can be dropped.
>> Also, since this is the final job API that doesn't use AioContext
>> lock and replaces it with job_lock, adj
+Kshitij
On Sun, Sep 18, 2022 at 6:24 PM Volker Rümelin wrote:
>
> The png_destroy_write_struct() function frees all memory used by
> libpng. Don't use the glib auto cleanup mechanism to free the
> memory allocated by libpng again. For the pixman image, use only the
> auto cleanup mechanism and r
On 9/17/22 22:11, Stefan Hajnoczi wrote:
On Sat, 17 Sept 2022 at 15:31, Philippe Mathieu-Daudé wrote:
On 17/9/22 16:26, Stefan Hajnoczi wrote:
The close_range(2) man page says:
close_range() first appeared in Linux 5.9. Library support was added
in glibc in version 2.34.
The qemu-user GitLa
On 01/09/2022 17:25, Bernhard Beschow wrote:
Having an i8259 proxy allows for ISA PICs to be created and wired up in
southbridges. This is especially interesting for PIIX3 for two reasons:
First, the southbridge doesn't need to care about the virtualization
technology used (KVM, TCG, Xen) due to
On 01/09/2022 17:25, Bernhard Beschow wrote:
Rather than registering the reset handler via a function which
appends the handler to a global list, prefer to implement it as
a virtual method - PIIX4 does the same already.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 8 +++-
1 file
Here is a bunch of patches for linux-user.
Most of them add missing syscalls and enhance the tracing/logging.
Some of the patches are target-hppa specific.
I've tested those on productive hppa debian buildd servers (running qemu-user).
Thanks!
Helge
Changes to v2:
- Fix build of close_range() an
Signed-off-by: Helge Deller
---
linux-user/strace.c| 15 +++
linux-user/strace.list | 3 ++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 2f539845bb..6f818212d5 100644
--- a/linux-user/strace.c
+++ b/linux-user/str
Allow linux-user to strace the clock_gettime64() syscall.
This syscall is used a lot on 32-bit guest architectures which use newer
glibc versions.
Signed-off-by: Helge Deller
---
linux-user/strace.c| 53 ++
linux-user/strace.list | 4
2 files cha
I noticed those were missing when running the glib2.0 testsuite.
Add the syscalls including the strace output.
Signed-off-by: Helge Deller
---
linux-user/strace.c| 28
linux-user/strace.list | 9 +
linux-user/syscall.c | 34
Signed-off-by: Helge Deller
---
linux-user/strace.list | 3 +++
linux-user/syscall.c | 16
2 files changed, 19 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 215d971b2a..ad9ef94689 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.l
Some of the guest signal numbers are currently not converted to
their representative names in the strace output, e.g. SIGVTALRM.
This patch introduces a smart way to generate and keep in sync the
host-to-guest and guest-to-host signal conversion tables for usage in
the qemu signal and strace code.
Signed-off-by: Helge Deller
---
linux-user/strace.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 6f818212d5..b6b9abaea4 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -3714,11 +3714,20 @@ print_futex
Signed-off-by: Helge Deller
---
linux-user/strace.list | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index ad9ef94689..97d8ccadac 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -355,7 +355,7 @@
{ TARGET_NR
On the parisc architecture the stack grows upwards.
Move the TASK_UNMAPPED_BASE to high memory area as it's done by the
kernel on physical machines.
Signed-off-by: Helge Deller
---
linux-user/mmap.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
ind
Enhance the EXCP_DUMP() macro to print out the failing program too.
During debugging it's sometimes hard to track down the actual failing
program if you are e.g. building a whole debian package.
Signed-off-by: Helge Deller
---
linux-user/cpu_loop-common.h | 2 ++
1 file changed, 2 insertions(+)
Enhance the hppa linux-user cpu_loop() to show more debugging info
on hard errors.
Signed-off-by: Helge Deller
---
linux-user/hppa/cpu_loop.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index 64263c3dc4..1ef3b46
Include the IIR register (which holds the opcode of the failing
instruction) when dumping the hppa registers.
Signed-off-by: Helge Deller
---
target/hppa/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index e2758d8df
If the mode parameter of chmod() is zero, this value isn't shown
when stracing a program:
chmod("filename",)
This patch fixes it up to show the zero-value as well:
chmod("filename",000)
Signed-off-by: Helge Deller
---
linux-user/strace.c | 5 +
1 file changed, 5 insertions(+)
diff -
On 01/09/2022 17:25, Bernhard Beschow wrote:
This aligns PIIX4 with PIIX3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 44
hw/mips/malta.c | 6 --
2 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/hw/isa/piix4.c b/h
On 01/09/2022 17:26, Bernhard Beschow wrote:
The - deliberately exported - components can still be accessed
via QOM properties.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix.c | 52 +
include/hw/southbridge/piix.h | 54 --
On 01/09/2022 17:25, Bernhard Beschow wrote:
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges and is an extended version of [1]. The motivation is to share as much
code as possible and to bring both device models to feature parity such that
perhaps PIIX4 can beco
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
v2: Use pointer for ram_banks in the pr
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 6 ++
hw/ppc/ppc4xx_devs.c | 8 ++--
2 fi
This is the end of the QOMify series started by Cédric. This series
handles the SDRAM controller models to clean them up, QOMify and unify
them and at least partially clean up the mess that has accumulated
around these in the past. This includes the not yet merged patches
from the last series and n
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 49 +--
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use i
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index edfb8c9709..7ec7c7c43d 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan
---
v5: Add functi
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_devs.c | 40
1 file changed, 20
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 8eae4ad9f0..900b7ab998 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdr
Rename local sdram variable in ppc440_sdram_init to s for readability.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/ppc/ppc440_uc.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --gi
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place allowing sharing some code between them.
Signed-off-by: BALATON Zoltan
---
hw/ppc/meson.build | 3 +-
hw/ppc/ppc440_uc.c | 332 --
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc405_boards.c | 2 +-
h
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 4 GiB, 16 and 8 MiB
to the DoC and the board now only checks for additional restrictions
imposed by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BAL
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_sdram.c | 158 +++
On 18/9/22 21:45, Helge Deller wrote:
Include the IIR register (which holds the opcode of the failing
instruction) when dumping the hppa registers.
Signed-off-by: Helge Deller
---
target/hppa/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models.
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we on
On 18/9/22 22:24, BALATON Zoltan wrote:
This is the end of the QOMify series started by Cédric. This series
handles the SDRAM controller models to clean them up, QOMify and unify
them and at least partially clean up the mess that has accumulated
around these in the past. This includes the not yet
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zolt
On 18/9/22 22:24, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 18/9/22 21:45, Helge Deller wrote:
Enhance the EXCP_DUMP() macro to print out the failing program too.
During debugging it's sometimes hard to track down the actual failing
program if you are e.g. building a whole debian package.
Signed-off-by: Helge Deller
---
linux-user/cpu_loop-common.h
On 18/9/22 21:45, Helge Deller wrote:
Signed-off-by: Helge Deller
---
linux-user/strace.list | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index ad9ef94689..97d8ccadac 100644
--- a/linux-user/strace.list
+++ b/linux-user/st
On 18/9/22 21:45, Helge Deller wrote:
If the mode parameter of chmod() is zero, this value isn't shown
when stracing a program:
chmod("filename",)
This patch fixes it up to show the zero-value as well:
chmod("filename",000)
Signed-off-by: Helge Deller
---
linux-user/strace.c | 5 +++
On 18/9/22 22:24, BALATON Zoltan wrote:
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan
---
Hi Zoltan,
On 18/9/22 22:24, BALATON Zoltan wrote:
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place allowing sharing some code between them.
Signed-off-by: BALATON Zoltan
---
hw/ppc/meson.bu
On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 18/9/22 22:24, BALATON Zoltan wrote:
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place allowing sharing some code between them.
Am 18. September 2022 20:21:09 UTC schrieb Mark Cave-Ayland
:
>On 01/09/2022 17:26, Bernhard Beschow wrote:
>
>> The - deliberately exported - components can still be accessed
>> via QOM properties.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> hw/isa/piix.c | 52
On Sun, 18 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 20:25, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/14/22 13:44, BALATON Zoltan wrote:
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
On 9/13/22 21:52, BALATON Zoltan wrote:
The do_init parameter of ppc4xx_sdram
On 18/9/22 23:24, BALATON Zoltan wrote:
On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 18/9/22 22:24, BALATON Zoltan wrote:
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place a
Am 1. September 2022 19:13:22 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 1/9/22 18:25, Bernhard Beschow wrote:
>> The USB controller is an integral part of PIIX3 (function 2). So create
>> it as part of the south bridge.
>>
>> Note that the USB function is optional in QEMU. This is why it gets
>>
Am 18. September 2022 20:10:51 UTC schrieb Mark Cave-Ayland
:
>On 01/09/2022 17:25, Bernhard Beschow wrote:
>
>> This aligns PIIX4 with PIIX3.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> hw/isa/piix4.c | 44
>> hw/mips/malta.c | 6 --
>>
Am 18. September 2022 20:22:55 UTC schrieb Mark Cave-Ayland
:
>On 01/09/2022 17:25, Bernhard Beschow wrote:
>
>> This series consolidates the implementations of the PIIX3 and PIIX4 south
>> bridges and is an extended version of [1]. The motivation is to share as much
>> code as possible and to bri
Stefan Hajnoczi 于2022年9月18日周日 04:17写道：
>
> On Thu, Sep 15, 2022 at 06:06:38PM +0800, Sam Li wrote:
> > Eric Blake 于2022年9月15日周四 16:05写道：
> > >
> > > On Sat, Sep 10, 2022 at 01:27:53PM +0800, Sam Li wrote:
> > > > Signed-off-by: Sam Li
> > > > Reviewed-by: Stefan Hajnoczi
> > > > Reviewed-by: Da
This patch adds a new backend called LKCF to cryptodev, LKCF stands
for Linux Kernel Cryptography Framework. If a cryptographic
accelerator that supports LKCF is installed on the the host (you can
see which algorithms are supported in host's LKCF by executing
'cat /proc/crypto'), then RSA operation
Add encoding interfaces for DER encoding:
1. support decoding of 'bit string', 'octet string', 'object id'
and 'context specific tag' for DER encoder.
2. implemented a simple DER encoder.
3. add more testsuits for DER encoder.
Signed-off-by: lei he
---
crypto/der.c | 307
virtio-crypto: Modify the current interface of virtio-crypto
device to support asynchronous mode.
Signed-off-by: lei he
---
backends/cryptodev-builtin.c| 69 ++---
backends/cryptodev-vhost-user.c | 51 +--
backends/cryptodev.c| 44 +++---
hw/virtio/virtio-crypto.c
cryptodev: Added a new type of backend named lkcf-backend for
cryptodev. This backend upload asymmetric keys to linux kernel,
and let kernel do the accelerations if possible.
The lkcf stands for Linux Kernel Cryptography Framework.
Signed-off-by: lei he
---
backends/cryptodev-lkcf.c | 640 +
crypto: support export RSA private keys with PKCS#8 standard.
So that users can upload this private key to linux kernel.
Signed-off-by: lei he
---
crypto/akcipher.c | 17 +
crypto/rsakey.c | 42 ++
crypto/rsakey.h
On 9/17/2022 5:57 AM, Peter Xu wrote:
On Thu, Sep 15, 2022 at 05:28:39PM +0800, Chenyi Qiang wrote:
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means
On 9/19/2022 1:46 PM, Chenyi Qiang wrote:
Not sure some warning would be also useful here, but I really don't know
the whole context so I can't tell whether there can easily be false
positives to pollute qemu log.
The false positive case is not easy to happen unless some potential
issues in s
The png_destroy_write_struct() function frees all memory used by
libpng. Don't use the glib auto cleanup mechanism to free the
memory allocated by libpng again. For the pixman image, use only the
auto cleanup mechanism and remove the qemu_pixman_image_unref()
function call to prevent another double
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 87 +++
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.h | 4 +
This series adds support for the Smstateen specification which provides a
mechanism to plug the potential covert channels which are opened by extensions
that add to processor state that may not get context-switched. Currently access
to *envcfg registers and floating point(fcsr) is controlled via sm
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23 +
target/riscv/insn_trans
Hi Markus,
On 9/17/22 2:44 PM, Philippe Mathieu-Daudé via wrote:
> Hi Markus,
>
> On 2/9/22 14:24, Markus Armbruster wrote:
>> Dongli Zhang writes:
>>
>>> The below is printed when printing help information in qemu-system-x86_64
>>> command line, and when CONFIG_TRACE_LOG is enabled:
>>>
>>> ---
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aee14a239a..1252ca71b3 1
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