Re: [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()

On 9/13/22 21:52, BALATON Zoltan wrote: Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater

Re: [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

On 9/13/22 21:52, BALATON Zoltan wrote: Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. So, we are relying on ppc4xx_sdram_banks() to check the RAM size and report the error. The problem

Re: [PATCH v3 07/20] ppc4xx_sdram: QOM'ify

On 9/13/22 21:52, BALATON Zoltan wrote: Change the ppc4xx_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly modelling the DDR SDRAM controller found in the 440EP (used on the bamboo board) but also backward compatible with the older DDR con

Re: [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility

On 9/13/22 21:52, BALATON Zoltan wrote: Rename local sdram variable in ppc440_sdram_init to s for readibility. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater Thanks, C. --- hw/ppc/ppc440_uc.c | 36 ++-- 1 file changed, 18 insertions(+),

Re: [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM

On 9/13/22 21:52, BALATON Zoltan wrote: To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan Please consider adding a define instead. Thanks, C. --- v2: replace 0x0800

Re: [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse

On 9/13/22 21:52, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 5db59d1190..01184e717b 100644 --- a/hw/ppc/ppc440_uc

Re: [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups

On 9/13/22 21:52, BALATON Zoltan wrote: This is the end of the QOMify series started by Cédric. This series handles the SDRAM controller models to clean them up, QOMify and unify them and at least partially clean up the mess that has accumulated around these in the past. This includes the not yet

[PATCH] bochs-display: Modify mismatched return value

Modify the return value of unsigned int to 0. Signed-off-by: jianchunfu --- hw/display/bochs-display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 8ed734b195..3bd22b4ea7 100644 --- a/hw/display/bochs-display.c

Re: [PATCH 49/51] io/channel-watch: Fix socket watch on Windows

On Wed, Sep 7, 2022 at 1:07 PM Bin Meng wrote: > > Hi Clément, > > On Tue, Sep 6, 2022 at 8:06 PM Clément Chigot wrote: > > > > > > > I checked your patch, what you did seems to be something one would > > > > > naturally write, but what is currently in the QEMU sources seems to be > > > > > writt

Re: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough device

On 13/09/2022 04:02, Ji, Ruili wrote: [AMD Official Use Only - General] Hi Paul, Could you help to review this patch? LGTM. You can add my R-b to it. Paul Thanks *From:* Ji, Ruili *Sent:* 2022年9月7日 9:04 *To:* 'Paul Durrant' ; 'qemu-devel@nongnu.org' *Cc:* Liu, Aaron ; 'xen-de...@lis

Re: [PATCH] chardev: fix segfault in finalize

+ vsementsov@- pbonzini@   26.08.2022, 11:21, "Marc-André Lureau" :Hi  On Thu, Aug 25, 2022 at 9:02 PM Maksim Davydov wrote:If finalize chardev-msmouse or chardev-wctable is called immediately afterinit it cases QEMU to crash with segfault. This happens because ofQTAILQ

[PATCH 1/3] target/riscv: Set the CPU resetvec directly

Instead of using our properties to set a config value which then might be used to set the resetvec (depending on your timing), let's instead just set the resetvec directly in the env struct. This allows us to set the reset vec from the command line with: -global driver=riscv.hart_array,propert

[PATCH 2/3] hw/riscv: opentitan: Fixup resetvec

The resetvec for the OpenTitan machine ended up being set to an out of date value, so let's fix that and bump it to the correct start address (after the boot ROM) Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version" Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 2 +- 1

[PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues

The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot ROM flow. This series makes it more configurguable from the command line and fixes the default. Alistair Francis (3): target/riscv: Set the CPU resetvec directly hw/riscv: opentitan: Fixup resetvec hw/riscv: opentitan: E

[PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property

On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something

RE: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough device

[AMD Official Use Only - General] Hi Paul, Thank you! But how could we merge this patch ? Ruili -Original Message- From: Paul Durrant Sent: 2022年9月14日 17:08 To: Ji, Ruili ; qemu-devel@nongnu.org Cc: Liu, Aaron ; xen-de...@lists.xenproject.org Subject: Re: [PATCH] hw/xen: set pci Atomic

[PATCH] target/arm: Fix alignment for VLD4.32

When requested, the alignment for VLD4.32 is 8 and not 16. See ARM documentation about VLD4 encoding: ebytes = 1 << UInt(size); if size == '10' then alignment = if a == '0' then 1 else 8; else alignment = if a == '0' then 1 else 4*ebytes; Signed-off-by: Clément Chigot

[PATCH v2 2/4] python/qmp: increase read buffer size

After modification of "query-machines" command the buffer size should be more than 452kB to contain output with compat-props. Signed-off-by: Maksim Davydov Reviewed-by: Vladimir Sementsov-Ogievskiy --- python/qemu/qmp/qmp_client.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[PATCH v2 0/4] compare machine type compat_props

v2 -> v1: * fix script code style and descriptions * reorder patches v1 -> previous iteration: * new default value print concept * QEMU python library is used to collect qmp data * remove auxiliary patches (that was used to fix ->get sematics) * print compat_props in the correct order * delete `ab

[PATCH v2 4/4] scripts: add script to compare compatible properties

This script run QEMU to obtain compat_props of machines and default values of different types and produce appropriate table. This table can be used to compare machine types to choose the most suitable machine. Also table in json or csv format should be used to check that new machine doesn't affect

[PATCH v2 1/4] qom: add devault value

qmp_qom_list_properties can print default values if they are available as qmp_device_list_properties does, because both of them use the ObjectPropertyInfo structure with default_value field. This can be useful when working with "not device" types. Signed-off-by: Maksim Davydov Reviewed-by: Vladim

[PATCH v2 3/4] qmp: add dump machine type compatible properties

To control that creating new machine type doesn't affect the previous types (their compat_props) and to check complex compat_props inheritance we need qmp command to print machine type compatible properties. This patch adds the ability to get list of all the compat_props of the corresponding suppor

[PATCH 1/1] s390x/tcg: Fix opcode for lzrf

Fix the opcode for Load and Zero Rightmost Byte (32). Cc: qemu-sta...@nongnu.org Reported-by: Nathan Chancellor Tested-by: Nathan Chancellor Signed-off-by: Christian Borntraeger --- target/s390x/tcg/insn-data.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/

Re: [PATCH 2/3] vdpa: load vlan configuration at NIC startup

On Wed, Sep 14, 2022 at 4:20 AM Jason Wang wrote: > > On Fri, Sep 9, 2022 at 4:02 PM Eugenio Perez Martin > wrote: > > > > On Fri, Sep 9, 2022 at 8:40 AM Jason Wang wrote: > > > > > > On Fri, Sep 9, 2022 at 2:38 PM Jason Wang wrote: > > > > > > > > On Wed, Sep 7, 2022 at 12:36 AM Eugenio Pérez

Re: [PATCH 2/3] vdpa: load vlan configuration at NIC startup

On Fri, Sep 9, 2022 at 10:38 AM Michael S. Tsirkin wrote: > > On Fri, Sep 09, 2022 at 10:01:16AM +0200, Eugenio Perez Martin wrote: > > On Fri, Sep 9, 2022 at 8:40 AM Jason Wang wrote: > > > > > > On Fri, Sep 9, 2022 at 2:38 PM Jason Wang wrote: > > > > > > > > On Wed, Sep 7, 2022 at 12:36 AM Eu

Re: Question about loading bare metal firmware

On Tue, Sep 13, 2022 at 4:57 PM Clément Chigot wrote: > > > > Hi all, > > > > > > I'm wondering if there is an official way to load bare metal software > > > within qemu emulations. > > > I've seen a lot of people (including us) using -kernel. However, the > > > doc seems to imply that the generic

Re: [PATCH] i386: Add new CPU model SapphireRapids

On Thu, 11 Aug 2022 22:57:51 -0700 "Wang, Lei" wrote: > The new CPU model mostly inherits features from Icelake-Server, while > adding new features: > - AMX (Advance Matrix eXtensions) > - Bus Lock Debug Exception > and new instructions: > - AVX VNNI (Vector Neural Network Instruction): >

Re: [PATCH 2/3] vdpa: load vlan configuration at NIC startup

On 9/14/2022 3:20 AM, Jason Wang wrote: On Fri, Sep 9, 2022 at 4:02 PM Eugenio Perez Martin wrote: On Fri, Sep 9, 2022 at 8:40 AM Jason Wang wrote: On Fri, Sep 9, 2022 at 2:38 PM Jason Wang wrote: On Wed, Sep 7, 2022 at 12:36 AM Eugenio Pérez wrote: To have enabled vlans at device star

[PATCH v4 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size

Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/ppc/ppc440_bamboo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 2aac8a3fe9..2bd5e41140 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c

[PATCH v4 01/21] ppc440_bamboo: Remove unnecessary memsets

In ppc4xx_sdram_init() the struct is allocated with g_new0() so no need to clear its elements. In the bamboo machine init memset can be replaced with array initialiser which is shorter. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_bamboo.c | 6 ++ hw/ppc/ppc4xx_devs.c | 8 ++-- 2 fi

[PATCH v4 00/21] ppc4xx_sdram QOMify and clean ups

This is the end of the QOMify series started by Cédric. This series handles the SDRAM controller models to clean them up, QOMify and unify them and at least partially clean up the mess that has accumulated around these in the past. This includes the not yet merged patches from the last series and n

[PATCH v4 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()

Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- v2: Use pointer for ram_banks in the pr

[PATCH v4 07/21] ppc4xx_sdram: QOM'ify

Change the ppc4xx_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly modelling the DDR SDRAM controller found in the 440EP (used on the bamboo board) but also backward compatible with the older DDR controllers on some 405 SoCs so we also use i

[PATCH v4 03/21] ppc4xx_sdram: Get rid of the init RAM hack

The do_init parameter of ppc4xx_sdram_init() is used to map memory regions that is normally done by the firmware by programming the SDRAM controller. This is needed when booting a kernel directly from -kernel without a firmware. Do this from board code accessing normal SDRAM controller registers th

[PATCH v4 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct

Instead of storing sdram bank parameters in unrelated arrays put them in a struct so it's clear they belong to the same bank and simplify the state struct using this bank type. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- hw/ppc/ppc440_uc.c | 49 +--

[PATCH v4 08/21] ppc4xx_sdram: Drop extra zeros for readability

Constants that are written zero padded for no good reason are hard to read, it's easier to see what is meant if it's just 0 or 1 instead. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 40 1 file changed, 20 insertions(+), 20 deletions(-) diff

[PATCH v4 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 -- hw/ppc/ppc405_boards.c | 10 -- hw/ppc/ppc405_uc.c | 11 ++--

[PATCH v4 17/21] ppc4xx_sdram: Use hwaddr for memory bank size

This resolves the target_ulong dependency that's clearly wrong and was also noted in a fixme comment. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- hw/ppc/ppc4xx_sdram.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc4xx_sdr

[PATCH v4 11/21] ppc440_sdram: Get rid of the init RAM hack

Remove the do_init parameter of ppc440_sdram_init and enable SDRAM controller from the board via DCR access instead. Firmware does this so it may not be needed when booting firmware only with -kernel but we enable it unconditionally to preserve previous behaviour. Signed-off-by: BALATON Zoltan --

[PATCH v4 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse

Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 5db59d1190..01184e717b 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -561,26 +561,

[PATCH v4 15/21] ppc440_sdram: QOM'ify

Change the ppc440_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly modelling the DDR2 SDRAM controller found in the 460EX (used on the sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX) may have this controller but we on

[PATCH v4 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init

Move the check for valid memory sizes from board to sdram controller init. Board now only checks for additional restrictions imposed by firmware then sdram init checks for valid sizes for SoC. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440.h| 4 ++-- hw/ppc/ppc440_uc.c | 15 +++

[PATCH v4 19/21] ppc4xx_sdram: Generalise bank setup

Currently only base and size are set on initial bank creation and bcr value is computed on mapping the region. Set bcr at init so the bcr encoding method becomes local to the controller model and mapping and unmapping can operate on the bank so it can be shared between different controller models.

[PATCH v4 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling

Use the generic bank handling introduced in previous patch in the DDR SDRAM controller too. This also fixes previously broken region unmap due to sdram_ddr_unmap_bcr() ignoring container region so it crashed with an assert when the guest tried to disable the controller. Signed-off-by: BALATON Zolt

[PATCH v4 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM

To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan --- v4: Add define for enable bit v2: replace 0x0800 with BIT(27) hw/ppc/ppc440_uc.c | 38

Re: [PATCH 1/1] s390x/tcg: Fix opcode for lzrf

On Wed, Sep 14 2022, Christian Borntraeger wrote: > Fix the opcode for Load and Zero Rightmost Byte (32). Fixes: c2a5c1d718ea ("target/s390x: Implement load-and-zero-rightmost-byte insns") > > Cc: qemu-sta...@nongnu.org > Reported-by: Nathan Chancellor > Tested-by: Nathan Chancellor > Signed

[PATCH v4 18/21] ppc4xx_sdram: Rename local state variable for brevity

Rename the sdram local state variable to s in dcr read/write functions and reset methods for better readability and to match realize methods. Other places not converted will be changed or removed in subsequent patches. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 158 +++

[PATCH v4 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks()

Do not exit from ppc4xx_sdram_banks() but report error via an errp parameter instead. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 05d0

[PATCH v4 12/21] ppc440_sdram: Rename local variable for readability

Rename local sdram variable in ppc440_sdram_init to s for readability. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater --- hw/ppc/ppc440_uc.c | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440

Re: [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

On Wed, 14 Sep 2022, Cédric Le Goater wrote: On 9/13/22 21:52, BALATON Zoltan wrote: Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. So, we are relying on ppc4xx_sdram_banks() to check t

[PATCH v4 13/21] ppc4xx_sdram: Rename functions to prevent name clashes

Rename functions to avoid name clashes when moving the DDR2 controller model currently called ppc440_sdram to ppc4xx_devs. This also more clearly shows which function belongs to which model. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 69 ++--

[PULL 04/20] target/arm: Sort KVM reads of AArch32 ID registers into encoding order

From: Peter Maydell The code that reads the AArch32 ID registers from KVM in kvm_arm_get_host_cpu_features() does so almost but not quite in encoding order. Move the read of ID_PFR2 down so it's really in encoding order. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id:

Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack

On Wed, 14 Sep 2022, Cédric Le Goater wrote: On 9/13/22 21:52, BALATON Zoltan wrote: The do_init parameter of ppc4xx_sdram_init() is used to map memory regions that is normally done by the firmware by programming the SDRAM controller. This is needed when booting a kernel directly from -kernel wi

[PATCH v4 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together

Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file called ppc4xx_sdram to separate from other device models and put them in one place allowing sharing some code between them. Signed-off-by: BALATON Zoltan --- hw/ppc/meson.build | 3 +- hw/ppc/ppc440_uc.c | 325 --

Re: [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse

On Wed, 14 Sep 2022, Cédric Le Goater wrote: On 9/13/22 21:52, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 5db59d

[PULL 10/20] target/arm: Correct value returned by pmu_counter_mask()

From: Peter Maydell pmu_counter_mask() accidentally returns a value with bits [63:32] set, because the expression it returns is evaluated as a signed value that gets sign-extended to 64 bits. Force the whole expression to be evaluated with 64-bit arithmetic with ULL suffixes. The main effect of

[PULL 16/20] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits

From: Peter Maydell FEAT_PMUv3p5 introduces new bits which disable the cycle counter from counting: * MDCR_EL2.HCCD disables the counter when in EL2 * MDCR_EL3.SCCD disables the counter when Secure Add the code to support these bits. (Note that there is a third documented counter-disable bit,

[PULL 01/20] target/arm: Add cortex-a35

From: Hao Wu Add cortex A35 core and enable it for virt board. Signed-off-by: Hao Wu Reviewed-by: Joe Komlodi Reviewed-by: Peter Maydell Message-Id: <20220819002015.1663247-1-wuhao...@google.com> Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c

[PULL 00/20] target-arm.next patch queue

2022-09-07' of git://repo.or.cz/qemu/armbru into staging (2022-09-07 13:13:30 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-arm-20220914 for you to fetch changes up to 761c532ab1ebe9d345c9afe4fb9c2c4b26c58582: target/arm: Make boards pass

[PULL 03/20] target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8

From: Peter Maydell In the AArch32 ID register scheme, coprocessor registers with encoding cp15, 0, c0, c{0-7}, {0-7} are all in the space covered by what in v6 and v7 was called the "CPUID scheme", and are supposed to RAZ if they're not allocated to a specific ID register. For our pre-v8 CPUs w

[PULL 17/20] target/arm: Support 64-bit event counters for FEAT_PMUv3p5

From: Peter Maydell With FEAT_PMUv3p5, the event counters are now 64 bit, rather than 32 bit. (Previously, only the cycle counter could be 64 bit, and other event counters were always 32 bits). For any given event counter, whether the overflow event is noted for overflow from bit 31 or from bit

[PULL 06/20] target/arm: Implement ID_DFR1

From: Peter Maydell In Armv8.6, a new AArch32 ID register ID_DFR1 is defined; implement it. We don't have any CPUs with features that they need to advertise here yet, but plumbing in the ID register gives it the right name when debugging and will help in future when we do add a CPU that has non-z

[PULL 11/20] target/arm: Don't mishandle count when enabling or disabling PMU counters

From: Peter Maydell The PMU cycle and event counter infrastructure design requires that operations on the PMU register fields are wrapped in pmu_op_start() and pmu_op_finish() calls (or their more specific pmmcntr and pmevcntr equivalents). This includes any changes to registers which affect whe

[PULL 02/20] hw/arm/bcm2835_property: Add support for RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS

From: Enrik Berkhan In more recent Raspbian OS Linux kernels, the fb driver gives up immediately if RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS fails or no displays are reported. This change simply always reports one display. It makes bcm2835_fb work again with these more recent kernels. Reviewed

[PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2

From: Peter Maydell The logic in pmu_counter_enabled() for handling the 'prohibit event counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way that assumes that EL2 is never Secure. This used to be true, but the architecture now permits Secure EL2, and QEMU can emulate this. Refacto

[PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows

From: Peter Maydell When the cycle counter overflows, we are intended to set bit 31 in PMOVSR to indicate this. However a missing ULL suffix means that we end up setting all of bits 63-31. Fix the bug. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20220822132358.3524

[PULL 05/20] target/arm: Implement ID_MMFR5

From: Peter Maydell In Armv8.6 a new AArch32 ID register ID_MMFR5 is defined. Implement this; we want to be able to use it to report to the guest that we implement FEAT_ETS. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20220819110052.2942289-4-peter.mayd...@linaro.o

[PULL 07/20] target/arm: Advertise FEAT_ETS for '-cpu max'

From: Peter Maydell The architectural feature FEAT_ETS (Enhanced Translation Synchronization) is a set of tightened guarantees about memory ordering involving translation table walks: * if memory access RW1 is ordered-before memory access RW2 then it is also ordered-before any translation ta

[PULL 08/20] target/arm: Add missing space in comment

From: Peter Maydell Fix a missing space before a comment terminator. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20220819110052.2942289-7-peter.mayd...@linaro.org> Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups

On Wed, 14 Sep 2022, Cédric Le Goater wrote: On 9/13/22 21:52, BALATON Zoltan wrote: This is the end of the QOMify series started by Cédric. This series handles the SDRAM controller models to clean them up, QOMify and unify them and at least partially clean up the mess that has accumulated aroun

[PULL 18/20] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'

From: Peter Maydell Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20220822132358.3524971-11-peter.mayd...@linaro.org> Signed-off-by: Richard Henderson --- docs/system/arm/emulation

[PULL 12/20] target/arm: Ignore PMCR.D when PMCR.LC is set

From: Peter Maydell The architecture requires that if PMCR.LC is set (for a 64-bit cycle counter) then PMCR.D (which enables the clock divider so the counter ticks every 64 cycles rather than every cycle) should be ignored. We were always honouring PMCR.D; fix the bug so we correctly ignore it i

[PULL 19/20] target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel()

From: Peter Maydell Arm system emulation targets always have TARGET_BIG_ENDIAN clear, so there is no need to have handling in armv7m_load_kernel() for the case when it is defined. Remove the unnecessary code. Side notes: * our M-profile implementation is always little-endian (that is, it ma

[PULL 14/20] target/arm: Detect overflow when calculating next PMU interrupt

From: Peter Maydell In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next point at which we will get an overflow and need to fire the PMU interrupt or set the overflow flag. We do this by calculating the number of nanoseconds to the overflow event and then adding it to qemu_clock

[PATCH] target/arm: Do alignment check when translation disabled

If translation is disabled, the default memory type is Device, which requires alignment checking. Document, but defer, the more general case of per-page alignment checking. Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson -

[PATCH v2 3/4] scripts/ci/setup: spice-server only on x86 aarch64

From: "Lucas Mateus Castro (alqotel)" Changed build-environment.yml to only install spice-server on x86_64 and aarch64 as this package is only available on those architectures. Signed-off-by: Lucas Mateus Castro (alqotel) --- scripts/ci/setup/build-environment.yml | 12 +++- 1 file cha

[PULL 15/20] target/arm: Rename pmu_8_n feature test functions

From: Peter Maydell Our feature test functions that check the PMU version are named isar_feature_{aa32,aa64,any}_pmu_8_{1,4}. This doesn't match the current Arm ARM official feature names, which are FEAT_PMUv3p1 and FEAT_PMUv3p4. Rename these functions to _pmuv3p1 and _pmuv3p4. This commit was

[PATCH v2] e1000e: set RX desc status with DD flag in a separate operation

Like commit 034d00d48581 ("e1000: set RX descriptor status in a separate operation"), there is also same issue in e1000e, which would cause lost packets or stop sending packets to VM with DPDK. Do similar fix in e1000e. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/402 Signed-off-by: Di

Re: [PATCH v11 10/21] block/mirror.c: use of job helpers in drivers

On 8/26/22 16:20, Emanuele Giuseppe Esposito wrote: Once job lock is used and aiocontext is removed, mirror has to perform job operations under the same critical section, Note: at this stage, job_{lock/unlock} and job lock guard macros are*nop*. Signed-off-by: Emanuele Giuseppe Esposito Review

[PULL 20/20] target/arm: Make boards pass base address to armv7m_load_kernel()

From: Peter Maydell Currently armv7m_load_kernel() takes the size of the block of memory where it should load the initial guest image, but assumes that it should always load it at address 0. This happens to be true of all our M-profile boards at the moment, but it isn't guaranteed to always be s

Re: [PATCH] target/arm: Fix alignment for VLD4.32

On 9/14/22 11:50, Clément Chigot wrote: When requested, the alignment for VLD4.32 is 8 and not 16. See ARM documentation about VLD4 encoding: ebytes = 1 << UInt(size); if size == '10' then alignment = if a == '0' then 1 else 8; else alignment = if a == '0' then 1

[PULL 01/11] target/nios2: Use semihosting/syscalls.h

This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Signed-off-by: Richard Henderson --- target/nios2/nios2-semi.c | 296 +++--- 1 file changed, 50 insertions(+), 246 deletions(-) diff

[PULL 04/11] target/m68k: Convert semihosting errno to gdb remote errno

The semihosting abi used by m68k uses the gdb remote protocol filesys errnos. Acked-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/m68k-semi.c | 33 +++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/target/m68k/m68k-semi.c b/ta

[PATCH v2 0/4] Patch series to set up a ppc64le CI

From: "Lucas Mateus Castro (alqotel)" This patch series aim to make easier to set up a compilation and CI environment on PPC64 and PPC64LE machines. v2: This patch series are only patches 2-4 of v1 and an alternative to patch 1 suggested by Daniel. Lucas Mateus Castro (alqotel) (4): scripts/c

[PULL 05/11] semihosting: Allow optional use of semihosting from userspace

From: Peter Maydell Currently our semihosting implementations generally prohibit use of semihosting calls in system emulation from the guest userspace. This is a very long standing behaviour justified originally "to provide some semblance of security" (since code with access to the semihosting A

[PULL 08/11] target/mips: Honour -semihosting-config userspace=on

From: Peter Maydell Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the

[PULL 07/11] target/m68k: Honour -semihosting-config userspace=on

From: Peter Maydell Honour the commandline -semihosting-config userspace=on option, instead of never permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(), instead of manually checking and always forbidd

[PATCH v2 1/4] scripts/ci/setup: ninja missing from build-environment

From: "Lucas Mateus Castro (alqotel)" ninja-build is missing from the RHEL environment, so a system prepared with that script would still fail to compile QEMU. Tested on a Fedora 36 Signed-off-by: Lucas Mateus Castro (alqotel) --- scripts/ci/setup/build-environment.yml | 1 + 1 file changed, 1

Proposal for a fixed ram migration stream format for file-based migrations

Hello, Based on several discussions I've had in the past 2 days and time spent looking at the migration stream code I came up with the following proposal for changes to the stream format. Let me recap what we have right now: ...() Where is put only when the current page we are writing to belo

[PATCH v2 2/4] scripts/ci/setup: Fix libxen requirements

From: "Lucas Mateus Castro (alqotel)" XEN hypervisor is only available in ARM and x86, but the yaml only checked if the architecture is different from s390x, changed it to a more accurate test. Tested this change on a Ubuntu 20.04 ppc64le. Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-b

[PULL 10/11] target/xtensa: Honour -semihosting-config userspace=on

From: Peter Maydell Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the

Re: [PATCH v11 11/21] jobs: group together API calls under the same job lock

On 8/26/22 16:20, Emanuele Giuseppe Esposito wrote: Now that the API offers also _locked() functions, take advantage of it and give also the caller control to take the lock and call _locked functions. This makes sense especially when we have for loops, because it makes no sense to have: for(job

Re: [PATCH 2/3] vdpa: load vlan configuration at NIC startup

On Wed, Sep 14, 2022 at 1:33 PM Si-Wei Liu wrote: > > > > On 9/14/2022 3:20 AM, Jason Wang wrote: > > On Fri, Sep 9, 2022 at 4:02 PM Eugenio Perez Martin > > wrote: > >> On Fri, Sep 9, 2022 at 8:40 AM Jason Wang wrote: > >>> On Fri, Sep 9, 2022 at 2:38 PM Jason Wang wrote: > On Wed, Sep 7

Re: [PATCH v11 16/21] blockjob: protect iostatus field in BlockJob struct

On 8/26/22 16:20, Emanuele Giuseppe Esposito wrote: iostatus is the only field (together with .job) that needs protection using the job mutex. It is set in the main loop (GLOBAL_STATE functions) but read in I/O code (block_job_error_action). In order to protect it, change block_job_iostatus_set

[PATCH v2 4/4] tests/docker: run script use realpath instead of readlink

From: "Lucas Mateus Castro (alqotel)" The alpine docker image only comes with busybox, which doesn't have the '-e' option on its readlink, so change it to 'realpath' to avoid that problem. Suggested-by: Daniel P. Berrangé Signed-off-by: Lucas Mateus Castro (alqotel) --- tests/docker/run | 2 +

Re: [PATCH v11 17/21] job.h: categorize JobDriver callbacks that need the AioContext lock

On 8/26/22 16:21, Emanuele Giuseppe Esposito wrote: Some callbacks implementation use bdrv_* APIs that assume the AioContext lock is held. Make sure this invariant is documented. Signed-off-by: Emanuele Giuseppe Esposito Reviewed-by: Vladimir Sementsov-Ogievskiy -- Best regards, Vladimir

[PULL 02/11] target/nios2: Convert semihosting errno to gdb remote errno

The semihosting abi used by nios2 uses the gdb remote protocol filesys errnos. Signed-off-by: Richard Henderson --- target/nios2/nios2-semi.c | 33 +++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi

[PULL 00/11] semihosting patch queue

The following changes since commit 79dfa177ae348bb5ab5f97c0915359b13d6186e2: Merge tag 'pull-qapi-2022-09-07' of git://repo.or.cz/qemu/armbru into staging (2022-09-07 13:13:30 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-semi-202

[PULL 09/11] target/nios2: Honour -semihosting-config userspace=on

From: Peter Maydell Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the

[PULL 03/11] target/m68k: Use semihosting/syscalls.h

This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Acked-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/m68k-semi.c | 281 +++- 1 file changed, 49 insertions(

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