$PROJECT/.cache/clangd/index is the intended location for project index
data when using clangd as the language server. Ignore this directory to
keep the git status clean.
Signed-off-by: Wang, Lei
---
.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitignore b/.gitignore
index 972
On Tue, Sep 06, 2022 at 06:02:00PM +0530, Sunil V L wrote:
> Hi Gerd,
>
> On Tue, Sep 06, 2022 at 12:41:28PM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > > 3)Make the EDK2 image size to match with what qemu flash expects
> > > truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd
> >
> >
On Tue, Sep 06, 2022 at 03:38:54PM -0400, John Snow wrote:
> Hi, I suspect I have asked this before, but I didn't write it down in
> a comment, so I forget my justification...
>
> In the QMP lib, we need to set a buffering limit for how big a QMP
> message can be -- In practice, I found that the l
On 9/5/22 01:34, Daniel Henrique Barboza wrote:
This will enable support for the 'dumpdtb' QMP/HMP command for
all powernv machines.
Cc: Cédric Le Goater
Cc: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/pnv.c | 8 +++-
Hi,
> For this module_load_qom_all() maybe Gerd has a bit more context on
> was should be the error reporting here?
Use case for module_load_qom_all() is someone enumerating the qom
objects available. So we load all modules known to have all object
types registered and can return a complete l
> > Ah I noticed only now... I just sent a series, the module_load_qom_all()
> > then is maybe something to discuss further.
> >
> > Thanks,
> >
> > Claudio
> >
>
> I noticed however that module_load_qom_all() does _not_ pass true for mayfail.
>
> You changed this behavior in:
>
> commit 9f4
On Tue, Sep 06, 2022 at 03:38:54PM -0400, John Snow wrote:
> Hi, I suspect I have asked this before, but I didn't write it down in
> a comment, so I forget my justification...
>
> In the QMP lib, we need to set a buffering limit for how big a QMP
> message can be -- In practice, I found that the l
On Tue, Sep 06, 2022 at 01:27:20PM +0200, Jason A. Donenfeld wrote:
> This reverts 3824e25db1 ("x86: disable rng seeding via setup_data"), but
> for 7.2 rather than 7.1, now that modifying setup_data is safe to do.
>
> Cc: Gerd Hoffmann
> Cc: Laurent Vivier
> Cc: Michael S. Tsirkin
> Cc: Paolo
From: Weiwei Li
- Zmmul is ratified and is now version 1.0
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220710101546.3907-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertion
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 10 ++
target/
From: Weiwei Li
Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-5-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/ri
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Alistair Francis
Signed-off-by: Jaso
From: Frédéric Pétrot
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot
Reviewed-by: W
From: Weiwei Li
Add check for the implicit dependence between H and S
Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Andre
From: Anup Patel
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extens
From: Dao Lu
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Dao Lu
Message-Id: <20220725034728.2620750-2-da...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cp
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 3 +++
target/riscv/in
From: Weiwei Li
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <2022071813
From: Daniel Henrique Barboza
The 'fdt' param is not being used in riscv_setup_rom_reset_vec().
Simplify the API by removing it. While we're at it, remove the redundant
'return' statement at the end of function.
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
Cc: Vijai Kumar K
Signed-of
From: Alexey Baturo
Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-Id: <20220717101543.478533-2-space.monkey.deliv...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 2 +-
1
From: Weiwei Li
Fix the lines with over 80 characters
Fix the lines which are obviously misalgined with other lines in the
same group
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-4-liwei...@is
From: Anup Patel
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Acked-by: dramforever
Message-Id: <20220630061
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 7 +++
target/risc
From: Conor Dooley
When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c00: '#address-cells' is a required property
From schema:
/stuff
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 26 --
1
From: Weiwei Li
Add check for "H depends on an I base integer ISA with 32 x registers"
which is stated at the beginning of chapter 8 of the riscv-privileged
spec(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Mess
l-riscv-to-apply-20220907
for you to fetch changes up to f0551560b5c01b1dcbed1ac46ca0bd1155330f5f:
target/riscv: Update the privilege field for sscofpmf CSRs (2022-09-07
09:19:15 +0200)
First RISC-V PR for QEMU 7.2
* Update [m|h]ti
From: Atish Patra
Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Reviewed-by: Anup Patel
Reviewed-by
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 11 +++
target
From: Weiwei Li
Just add 1 to the effective privledge level when in HS mode, then reuse
the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace
the privilege level related check in hmode. Then, hmode will only check
whether H extension is supported.
When accessing Hypervior CSRs
From: Bin Meng
Upgrade OpenSBI from v1.0 to v1.1 and the pre-built bios images.
The v1.1 release includes the following commits:
5b99603 lib: utils/ipi: Fix size check in aclint_mswi_cold_init()
6dde435 lib: utils/sys: Extend HTIF library to allow custom base address
8257262 platform: sifive_fu
From: Atish Patra
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to lever
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 35 +--
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +++
From: "Yueh-Ting (eop) Chen"
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibi
From: Bin Meng
Since commit fbf43c7dbf18 ("target/riscv: enable riscv kvm accel"),
KVM accelerator is supported on RISC-V. Let's document it.
Signed-off-by: Bin Meng
Reviewed-by: Thomas Huth
Reviewed-by: Alistair Francis
Message-Id: <20220719082635.3741878-1-bin.m...@windriver.com>
Signed-off
From: Weiwei Li
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if no
From: Atish Patra
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.
Reviewed-by: Heiko Stuebner
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220816232321.558250-7-ati...@rivosinc.com>
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +++
From: Conor Dooley
The reset and poweroff features of the syscon were originally added to
top level, which is a valid path for a syscon subnode. Subsequently a
reorganisation was carried out while implementing NUMA in which the
subnodes were moved into the /soc node. As /soc is a "simple-bus", th
From: Anup Patel
The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).
Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32
From: Rahul Pathak
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak
Reviewed-by: Alistair Francis
Message-id: 20220816045408.1231135-1-rpat...@ventanamicro.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1
Peter Maydell writes:
> On Tue, 6 Sept 2022 at 08:55, Daniel P. Berrangé wrote:
>>
>> On Mon, Sep 05, 2022 at 10:21:55PM +0100, Peter Maydell wrote:
>> > On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote:
>> > > when I build qemu, there is a lot of time spent at the end of the build
>> > > w
From: Wilfred Mallawa
The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which
From: Conor Dooley
"platform" is not a valid name for a bus node in dt-schema, so warnings
can be see in dt-validate on a dump of the riscv virt dtb:
/stuff/qemu/qemu.dtb: platform@400: $nodename:0: 'platform@400' does
not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?
From: Atish Patra
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221357.41070-3-ati...@riv
From: Conor Dooley
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
From: Atish Patra
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Reviewed-by: Alistair Francis
Signed-off
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Tested-by: Heiko Stuebner
Signed-off-by: Atish Patra
Signed-off-b
From: Conor Dooley
"uart" is not a node name that complies with the dt-schema.
Change the node name to "serial" to ix warnings seen during
dt-validate on a dtbdump of the virt machine such as:
/stuff/qemu/qemu.dtb: uart@1000: $nodename:0: 'uart@1000' does not
match '^serial(@.*)?$'
From: Atish Patra
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Re
On Thu, 25 Aug 2022 17:18:42 +0100
Shameer Kolothum wrote:
> Hi
>
> On arm/virt platform, Chen Xiang reported a Guest crash while
> attempting the below steps,
>
> 1. Launch the Guest with nvdimm=on
> 2. Hot-add a NVDIMM dev
> 3. Reboot
> 4. Guest boots fine.
> 5. Reboot again.
> 6. Guest boot
From: Atish Patra
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Acked-by:
On Thu, 1 Sep 2022 11:27:19 +0800
Robert Hoo wrote:
> Since it will be heavily used in next patch, define macro
> NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is
> NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec,
> Section 3. [1]
>
> No funct
> > QEMU_EFI reports the below error:
> > ProcessCmdAddPointer: invalid pointer value in "etc/acpi/tables"
> > OnRootBridgesConnected: InstallAcpiTables: Protocol Error
> >
> > Debugging shows that on first reboot(after hot-adding NVDIMM),
> > Qemu updates the etc/table-loader len,
> >
> > qemu_r
From: Atish Patra
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-6-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
targ
On 05/09/2022 01:34, Daniel Henrique Barboza wrote:
This will enable support for the 'dumpdtb' QMP/HMP command for
all powernv machines.
Cc: Cédric Le Goater
Cc: Frederic Barrat
Signed-off-by: Daniel Henrique Barboza
---
LGTM
Reviewed-by: Frederic Barrat
Fred
hw/ppc/pnv.c | 8 +
On 9/6/22 13:55, Claudio Fontana wrote:
> improve error handling during module load, by changing:
>
> bool module_load_one(const char *prefix, const char *lib_name);
> void module_load_qom_one(const char *type);
>
> to:
>
> bool module_load_one(const char *prefix, const char *name, Error **errp)
On 9/7/22 09:36, Gerd Hoffmann wrote:
> Hi,
>
>> For this module_load_qom_all() maybe Gerd has a bit more context on
>> was should be the error reporting here?
>
> Use case for module_load_qom_all() is someone enumerating the qom
> objects available. So we load all modules known to have all o
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> The guest can use the STSI instruction to get a buffer filled
> with the CPU topology description.
>
> Let us implement the STSI instruction for the basis CPU topology
> level, level 2.
>
> Signed-off-by: Pierre Morel
> ---
> hw/s390x/cpu
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> The guest can ask for a topology report on drawer's or book's
> level.
> Let's implement the STSI instruction's handling for the corresponding
> selector values.
>
> Signed-off-by: Pierre Morel
> ---
> hw/s390x/cpu-topology.c | 19
mayfail is always passed as false for every invocation throughout the program.
It controls whether to printf or not to printf an error on
g_module_open failure.
Remove this unused argument.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
i
improve error handling during module load, by changing:
bool module_load_one(const char *prefix, const char *lib_name);
void module_load_qom_one(const char *type);
to:
bool module_load_one(const char *prefix, const char *name, Error **errp);
bool module_load_qom_one(const char *type, Error **err
while investigating a permission issue in accel, where accel-tcg-x86_64.so
was not accessible, I noticed that no errors were produced regarding the
module load failure.
This series attempts to improve module_load_one and module_load_qom_one
to handle the error cases better and produce some errors.
if QEMU is configured with modules enabled, it is possible that the
load of an accelerator module will fail.
Abort in this case, relying on module_object_class_by_name to report
the specific load error if any.
Signed-off-by: Claudio Fontana
---
accel/accel-softmmu.c | 8 +++-
1 file changed,
John Snow writes:
> Hi, I suspect I have asked this before, but I didn't write it down in
> a comment, so I forget my justification...
>
> In the QMP lib, we need to set a buffering limit for how big a QMP
> message can be -- In practice, I found that the largest possible
> response was the QAPI
On Wed, Aug 31, 2022 at 10:23 AM Ani Sinha wrote:
>
> e820 reserved entries were used before the dynamic entries with fw config
> files
> were intoduced. Please see the following change:
> 7d67110f2d9a6("pc: add etc/e820 fw_cfg file")
>
> Identical support was introduced into seabios as well with
On 10.08.22 г. 13:39 ч., Nikolay Borisov wrote:
All pages which are going to be migrated are first added to
MultiFDSendParams::MultiFDPages_t::offset array by the main migration
thread and are subsequently copied to MultiFDSendParams::normal by the
multifd thread. This is really unnecessary as
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2aac8a3fe9..2bd5e41140 10
On 8/19/22 18:55, BALATON Zoltan wrote:
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
It looks like a good clean up. At some point, I think we will need t
sndio is the native API used by OpenBSD, although it has been ported to
other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.).
Signed-off-by: Brad Smith
Signed-off-by: Alexandre Ratchov
---
References to the previous patch versions and related discussions are
here:
https://mar
On 8/19/22 18:55, BALATON Zoltan wrote:
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
con
On 8/19/22 18:55, BALATON Zoltan wrote:
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
I would keep the 0x prefix though.
Thanks,
C.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 40 ++
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3507c35b63..c33f91e134 100644
--- a/hw/ppc/ppc440_uc
* zhenwei pi (pizhen...@bytedance.com) wrote:
> PING!
It's OK, I've got it lined up for a pull I'll do in a few days time.
Dave
> On 8/15/22 20:00, Dr. David Alan Gilbert wrote:
> > * zhenwei pi (pizhen...@bytedance.com) wrote:
> > > Originally we have to get all the vCPU registers and parse the
On 8/19/22 18:55, BALATON Zoltan wrote:
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 --
1 file changed,
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename local sdram variable in ppc440_sdram_init to s for readibility.
readability
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc440_uc.c | 36 ++--
1 file changed, 18 in
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Shouldn't we introduce class handlers instead ?
Thanks,
C.
On 8/19/22 18:55, BALATON Zoltan wrote:
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g.
On 8/19/22 18:55, BALATON Zoltan wrote:
Move the check for valid memory sizes from board to sdram contrller
controller
init. Board now only checks for additinal restrictions imposed by
additional
firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan
---
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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;
> are available in the Git repository at:
>
> g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220907
Hi Alistair,
Please update .git/config to separate the push URL from the fetch URL:
[remote "github"]
url = https://github.com/alistair23/qemu.git
On Sun, 4 Sept 2022 at 03:27, Stafford Horne wrote:
>
> The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60:
>
> Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
> (2022-09-02 13:24:28 -0400)
>
> are available in the Git repository at:
>
> g...@
add a simple help option for -audiodev, so users can do
qemu -audiodev ?
to get the list of drivers available.
Signed-off-by: Claudio Fontana
---
audio/audio.c | 20
1 file changed, 20 insertions(+)
diff --git a/audio/audio.c b/audio/audio.c
index 4f4bb10cce..bd8c18c3cd 1
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
I would keep the 0x prefix though.
I'm not a fan of 0x0 or 0x prefix f
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3507c35
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 +++
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Shouldn't we introd
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Move the check for valid memory sizes from board to sdram contrller
controller
init. Board now only checks for additinal restrictions imposed by
additional
Thanks for finding these spelling mistakes, look
在 2022/9/7 4:46, Peter Xu 写道:
On Fri, Sep 02, 2022 at 01:22:28AM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
v1:
- make parameter vcpu-dirty-limit experimental
- switch dirty limit off when cancel migrate
- add cancel logic in migration test
Please review, thanks,
Yong
A
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
It looks like a good cl
The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80:
Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into
staging (2022-09-06 08:31:24 -0400)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2022-09-07
From: Victor Toso
Example output is missing a ',' delimiter and it has an extra ending
curly bracket. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-7-victort...@redhat.com>
Signed-off-by: Mar
From: Victor Toso
The example return type has the wrong member name. Fix it.
Problem was noticed when using the example as a test case for Go
bindings.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-10-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.jso
From: Victor Toso
Example output has an extra ending curly bracket. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-6-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/net.json
From: Victor Toso
The examples use "qcow2" driver with the wrong member name for
BlockdevRef alternate type. This patch changes all wrong member names
from "file" to "data-file" which is the correct member name in
BlockdevOptionsQcow2 for the BlockdevRef field.
Problem was noticed when using the
From: Victor Toso
Example output has an extra ',' delimiter in member "websocket" and it
lacks it in "family" member. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-3-victort...@redhat.com>
Si
From: Victor Toso
Example output was missing ',' delimiter. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-8-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.json | 2
From: Victor Toso
Example output has an extra ',' delimiter. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-2-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.json |
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