Hi Clément,
On Mon, Sep 5, 2022 at 4:10 PM Clément Chigot wrote:
>
> Hi all,
>
> I did reach the same issue while trying to connect a gdb to qemu on
> Windows hosts. Some inputs send by gdb aren't getting correctly pulled,
> they will be retrieved only once g_poll times out.
>
> As you explained
On Tue, Sep 06, 2022 at 09:54:51AM +0530, Sunil V L wrote:
> To boot S-mode firmware payload like EDK2 from persistent
> flash storage, qemu needs to pass the flash address as the
> next_addr in fw_dynamic_info to the opensbi.
>
> When both -kernel and -pflash options are provided in command line,
On Tue, Sep 06, 2022 at 09:54:50AM +0530, Sunil V L wrote:
> To enable both -kernel and -pflash options, the fw_cfg needs to be
> created prior to loading the kernel.
>
> Signed-off-by: Sunil V L
> ---
> hw/riscv/virt.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
>
On Tue, Sep 06, 2022 at 09:54:49AM +0530, Sunil V L wrote:
> load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
> function will be required by riscv too. So, it's time to refactor and
> move this function to a common path.
>
> Signed-off-by: Sunil V L
> ---
> hw/arm/boot.c
This is the first step towards moving all device config size calculation
logic into the virtio core code. In particular, this adds a struct that
contains all the necessary information for common virtio code to be able
to calculate the final config size for a device. This is expected to be
used with
Make vhost-user-blk backwards compatible when migrating from older VMs
running with modern features turned off, the same way it was done for
virtio-blk in 20764be0421c ("virtio-blk: set config size depending on the
features enabled")
It's currently impossible to migrate from an older VM with
vhos
This way we can reuse it for other virtio-blk devices, e.g
vhost-user-blk, which currently does not control its config space size
dynamically.
Signed-off-by: Daniil Tatianin
Reviewed-by: Raphael Norwitz
---
MAINTAINERS | 2 ++
hw/block/meson.build |
No reason to have this be a separate field. This also makes it more akin
to what the virtio-blk device does.
Signed-off-by: Daniil Tatianin
Reviewed-by: Raphael Norwitz
---
hw/block/vhost-user-blk.c | 6 ++
include/hw/virtio/vhost-user-blk.h | 1 -
2 files changed, 2 insertions(+),
It is useful to have the ability to disable these features for
compatibility with older VMs that don't have these implemented.
Signed-off-by: Daniil Tatianin
Reviewed-by: Raphael Norwitz
---
hw/block/vhost-user-blk.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/b
On Mon, 5 Sep 2022 22:25:25 +0530 (IST)
Ani Sinha wrote:
> On Mon, 5 Sep 2022, Ani Sinha wrote:
>
> >
> >
>
> > > >
> > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > index 0355bd3dda..3dc9379f27 100644
> > > > --- a/hw/i386/acpi-build.c
> > > > +++ b/hw/i386/acpi-build.
This patch set attempts to align vhost-user-blk with virtio-blk in
terms of backward compatibility and flexibility. It also improves
the virtio core by introducing new common code that can be used by
a virtio device to calculate its config space size.
In particular it adds the following things:
-
On 9/6/22 01:08, Ilya Leoshkevich wrote:
Hi,
This series is made of patches from [1]. I've added a test and noticed
that madvise(MADV_DONTNEED) was broken on alpha, fixing which required
adding per-arch MADV_* definitions. This in turn affected the strace
patch, so it made sense to make a series
On Tue, 6 Sep 2022, Igor Mammedov wrote:
> On Mon, 5 Sep 2022 22:25:25 +0530 (IST)
> Ani Sinha wrote:
>
> > On Mon, 5 Sep 2022, Ani Sinha wrote:
> >
> > >
> > >
> >
> > > > >
> > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > > index 0355bd3dda..3dc9379f27 100644
> > >
Hi Bin,
> On Mon, Sep 5, 2022 at 4:10 PM Clément Chigot wrote:
> >
> > Hi all,
> >
> > I did reach the same issue while trying to connect a gdb to qemu on
> > Windows hosts. Some inputs send by gdb aren't getting correctly pulled,
> > they will be retrieved only once g_poll times out.
> >
> > As
On 8/22/22 15:12, Peter Maydell wrote:
Currently our semihosting implementations usually prohibit use of
semihosting calls in system emulation from the guest userspace. This
is a very long standing behaviour justified originally "to provide
some semblance of security" (since code with access to
On 9/5/22 22:28, Philippe Mathieu-Daudé wrote:
+ /*
+ * Allow target-specific additions to this structure.
+ * This may be used to cache items from the guest cpu
+ * page tables for later use by the implementation.
+ */
+#ifdef TARGET_PAGE_ENTRY_EXTRA
+ TARGET_PAGE_ENTRY_EXT
On Mon, Sep 05, 2022 at 10:21:55PM +0100, Peter Maydell wrote:
> On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote:
> > when I build qemu, there is a lot of time spent at the end of the build
> > where one cpu goes 100% on sphinx-build.
> >
> > Is there some way to parallelize that? It seems it
Hyman Huang writes:
> 在 2022/9/5 17:32, Markus Armbruster 写道:
>> Hyman Huang writes:
>>
>>> 在 2022/9/2 16:07, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
> From: Hyman Huang(黄勇)
>
> Introduce migration dirty-limit capability, which can
> be turned on before
Hi Clément,
On Tue, Sep 6, 2022 at 3:41 PM Clément Chigot wrote:
>
> Hi Bin,
>
> > On Mon, Sep 5, 2022 at 4:10 PM Clément Chigot wrote:
> > >
> > > Hi all,
> > >
> > > I did reach the same issue while trying to connect a gdb to qemu on
> > > Windows hosts. Some inputs send by gdb aren't getting
Peter Maydell writes:
> On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote:
>> when I build qemu, there is a lot of time spent at the end of the build
>> where one cpu goes 100% on sphinx-build.
>>
>> Is there some way to parallelize that? It seems it is the current bottleneck
>> for rebuilds
On Tue, Sep 06, 2022 at 11:56:33AM +0530, Ani Sinha wrote:
> On Thu, Jul 14, 2022 at 6:54 PM Peter Maydell
> wrote:
> >
> > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote:
> > >
> > > On Sun, Jul 10, 2022 at 10:30:03PM +0530, Ani Sinha wrote:
> > > > Changelog:
> > > > v2:
> > > > - a n
Quoting Pierre Morel (2022-09-02 09:55:24)
> The guest can use the STSI instruction to get a buffer filled
> with the CPU topology description.
>
> Let us implement the STSI instruction for the basis CPU topology
> level, level 2.
I like this. It is so much simpler. Thanks.
[...]
> diff --git a/
On 9/5/22 22:55, Philippe Mathieu-Daudé wrote:
> On 5/9/22 17:55, Claudio Fontana wrote:
>> mayfail is always passed as false for every invocation throughout the
>> program.
>> It controls whether to printf or not to printf an error on
>> g_module_open failure.
>>
>> Remove this unused argument.
>
The current implementation is a no-op, simply returning addr.
This is incorrect, because we ought to be checking the page
permissions for execution.
Make get_page_addr_code inline for both implementations.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Acked-by: Alistair Francis
Signed
5 18:01:02 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220906
for you to fetch changes up to 00c07344fa245b22e895b363320ba4cd0ec1088a:
target/riscv: Make translator stop before the end of a page (2022-09-06
08:0
We're about to start validating PAGE_EXEC, which means that we've
got to mark the vsyscall page executable. We had been special
casing this entirely within translate.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 23
Quoting Pierre Morel (2022-09-02 09:55:27)
> During a subsystem reset the Topology-Change-Report is cleared
> by the machine.
> Let's ask KVM to clear the Modified Topology Change Report (MTCR)
> bit of the SCA in the case of a subsystem reset.
>
> Signed-off-by: Pierre Morel
Reviewed-by: Nico
We're about to start validating PAGE_EXEC, which means that we've
got to mark page zero executable. We had been special casing this
entirely within translate.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 34
We're about to start validating PAGE_EXEC, which means
that we've got to mark the commpage executable. We had
been placing the commpage outside of reserved_va, which
was incorrect and lead to an abort.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
The mmap_lock is held around tb_gen_code. While the comment
is correct that the lock is dropped when tb_gen_code runs out
of memory, the lock is *not* dropped when an exception is
raised reading code for translation.
Acked-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkev
From: Ilya Leoshkevich
Introduce a function that checks whether a given address is on the same
page as where disassembly started. Having it improves readability of
the following patches.
Reviewed-by: Alistair Francis
Signed-off-by: Ilya Leoshkevich
Message-Id: <20220811095534.241224-3-...@linu
Map the stack executable if required by default or on demand.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/elf.h| 1 +
linux-user/qemu.h| 1 +
linux-user/elfload.c | 19 ++-
3 files changed, 20 insertions(+),
The base qemu_ram_addr_from_host function is already in
softmmu/physmem.c; move the nofail version to be adjacent.
Reviewed-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 1 +
accel/tcg/cputlb.c
From: Ilya Leoshkevich
Currently it's possible to execute pages that do not have PAGE_EXEC
if there is an existing translation block. Fix by invalidating TBs
that touch the affected pages.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20220817150506.592862-2-...@linux.ibm.com>
Signed-off-by: Ric
The function is not used outside of cpu-exec.c. Move it and
its subroutines up in the file, before the first use.
Reviewed-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 -
accel/tcg/cpu-exec.c
It was non-obvious to me why we can raise an exception in
the middle of a comparison function, but it works.
While nearby, use TARGET_PAGE_ALIGN instead of open-coding.
Acked-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 11 ++-
1 file changed, 10 inse
From: Ilya Leoshkevich
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
An implementation, like the one arm and s390x have, would require an
i386 length disas
Cache the translation from guest to host address, so we may
use direct loads when we hit on the primary translation page.
Look up the second translation page only once, during translation.
This obviates another lookup of the second page within tb_gen_code
after translation.
Fixes a bug in that pl
We're about to start validating PAGE_EXEC, which means
that we've got to put this code into a section that is
both writable and executable.
Note that this test did not run on hardware beforehand either.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
These will be useful in properly ending the TB.
Reviewed-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/transla
Pass these along to translator_loop -- pc may be used instead
of tb->pc, and host_pc is currently unused. Adjust all targets
at one time.
Acked-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 1
The only user can easily use translator_lduw and
adjust the type to signed during the return.
Reviewed-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 -
target/i386/tcg/translate.c | 2 +-
2 file
Simplify the implementation of get_page_addr_code_hostp
by reusing the existing probe_access infrastructure.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 76 --
1 file changed, 26 in
Right now the translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1155
Reviewed-by: Alistair Francis
Acked-by: Ilya
We already validate that LUKS keyslots don't overlap with the
header, or with each other. This closes the remain hole in
validation of LUKS file regions.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/crypto/block-luks.c b/cry
From: Ilya Leoshkevich
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Richard Henderson
Message-Id: <20220817
Validate that we diagnose each malformed LUKS header scenario with a
distinct error report.
Signed-off-by: Daniel P. Berrangé
---
tests/unit/test-crypto-block.c | 299 +
1 file changed, 299 insertions(+)
diff --git a/tests/unit/test-crypto-block.c b/tests/unit/te
The unit test suite is shortly going to want to convert header
endianness separately from the main I/O functions.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks-priv.h | 6 +++
crypto/block-luks.c | 79
2 files changed, 53 insertions(+), 32
Richard pointed out that we didn't do all that much validation against
bad parameters in the LUKS header metadata. This series adds a bunch
more validation checks along with unit tests to demonstrate they are
having effect against maliciously crafted headers.
Daniel P. Berrangé (11):
crypto: san
Although the LUKS stripes are encoded in the keyslot header and so
potentially configurable, in pratice the cryptsetup impl mandates
this has the fixed value 4000. To avoid incompatibility apply the
same enforcement in QEMU too. This also caps the memory usage for
key material when QEMU tries to op
If given a malformed LUKS header, it is possible that the algorithm
names end up being an empty string. This leads to confusing error
messages unless quoting is used to highlight where the empty string
is subsituted in the error message.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks.c
The LUKS header data on disk is a fixed size, however, there's expected
to be a gap between the end of the header and the first key slot to get
alignment with the 2nd sector on 4k drives. This wasn't originally part
of the LUKS spec, but was always part of the reference implementation,
so it is wor
Pierre Morel writes:
> S390x defines two topology levels above sockets: nbooks and drawers.
nbooks or books?
> Let's add these two levels inside the CPU topology implementation.
>
> Signed-off-by: Pierre Morel
> ---
[...]
> diff --git a/qapi/machine.json b/qapi/machine.json
> index 6afd1936b
Both the master key and key slot passphrases are run through the PBKDF2
algorithm. The iterations count is expected to be generally very large
(many 10's or 100's of 1000s). It is hard to define a low level cutoff,
but we can certainly say that iterations count should be non-zero. A
zero count like
We already check that key material doesn't overlap between key slots,
and that it doesn't overlap with the payload. We didn't check for
overlap with the LUKS header.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks.c | 8
1 file changed, 8 insertions(+)
diff --git a/crypto/block
load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
function will be required by riscv too. So, it's time to refactor and
move this function to a common path.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
---
hw/arm/boot.c | 49 -
GNUTLS is supported as a crypto provider since
commit cc4c7c738297958b3d1d16269f57d71d22f5a9ff
Author: Daniel P. Berrangé
Date: Wed Jun 30 17:20:02 2021 +0100
crypto: introduce build system for gnutls crypto backend
So enable the LUKS tests in this config.
Signed-off-by: Daniel P.
To boot S-mode firmware payload like EDK2 from persistent
flash storage, qemu needs to pass the flash address as the
next_addr in fw_dynamic_info to the opensbi.
When both -kernel and -pflash options are provided in command line,
the kernel (and initrd if -initrd) will be copied to fw_cfg table.
T
This will allow unit testing code to use the structs.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks-priv.h | 137 +++
crypto/block-luks.c | 94 +--
2 files changed, 138 insertions(+), 93 deletions(-)
create mode 100644
To enable both -kernel and -pflash options, the fw_cfg needs to be
created prior to loading the kernel.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
ind
The LUKS spec requires that header strings are NUL-terminated, and our
code relies on that. Protect against maliciously crafted headers by
adding validation.
Signed-off-by: Daniel P. Berrangé
---
crypto/block-luks.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/crypto/b
The goal here is to reduce the amount of code generation when the
guest kernel enables address space randomization. This requires
extensive changes to each target, so opt-in with TARGET_TB_PCREL.
This is split out of v3, which also contained target/arm changes,
as I now have patches for x86 and s
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
Signed-
Bool is more appropriate type for the alloc parameter.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f5e8592d4a..d2946f8e59 100644
--- a
On Tue, Sep 06, 2022 at 09:41:38AM +0100, Daniel P. Berrangé wrote:
> Although the LUKS stripes are encoded in the keyslot header and so
> potentially configurable, in pratice the cryptsetup impl mandates
> this has the fixed value 4000. To avoid incompatibility apply the
> same enforcement in QEMU
On Tue, Sep 06, 2022 at 09:41:42AM +0100, Daniel P. Berrangé wrote:
> Both the master key and key slot passphrases are run through the PBKDF2
> algorithm. The iterations count is expected to be generally very large
> (many 10's or 100's of 1000s). It is hard to define a low level cutoff,
> but we c
Wrap the bare TranslationBlock pointer into a structure.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 8 ++--
accel/tcg/cpu-exec.c | 9 ++---
accel/tcg/cputlb.c| 2 +-
accel/tcg/translate-all.c | 4 ++--
4 files changed, 15 insertions(+), 8 deletions(-)
This series adds the support to boot S-mode FW like EDK2 from the flash. The
S-mode firmware should be kept in pflash unit 1.
When -kernel (and -initrd) option is also provided along with the flash,
the kernel (and initrd) will be loaded into fw_cfg table and opensbi will
branch to the flash addre
Let tb->page_addr[0] contain the offset within the page of the
start of the translation block. We need to recover this value
anyway at various points, and it is easier to discard the page
offset when it's not needed, which happens naturally via the
existing find_page shift.
Signed-off-by: Richard
Prepare for targets to be able to produce TBs that can
run in more than one virtual context.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 3 +++
include/exec/exec-all.h | 41 ++---
include/hw/core/cpu.h | 1 +
accel/tcg/cpu-exec.c | 55 +++
The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12 ++
accel/tcg/cpu-exec.c| 20 -
accel/tcg/translate-all.c
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 7fe42269ea..ac8eec7f54 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -292,12 +292,1
On Tue, Sep 06, 2022 at 09:41:36AM +0100, Daniel P. Berrangé wrote:
> Richard pointed out that we didn't do all that much validation against
> bad parameters in the LUKS header metadata. This series adds a bunch
> more validation checks along with unit tests to demonstrate they are
> having effect
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 41 +++---
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a
On Tue, Sep 06, 2022 at 09:41:40AM +0100, Daniel P. Berrangé wrote:
> We already validate that LUKS keyslots don't overlap with the
> header, or with each other. This closes the remain hole in
remain -> remaining
> validation of LUKS file regions.
>
> Signed-off-by: Daniel P. Berrangé
> ---
>
On 9/6/22 10:11, Richard Henderson wrote:
The goal here is to reduce the amount of code generation when the
guest kernel enables address space randomization. This requires
extensive changes to each target, so opt-in with TARGET_TB_PCREL.
This is split out of v3, which also contained target/arm
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 63a4
On Tue, Sep 06, 2022 at 09:41:37AM +0100, Daniel P. Berrangé wrote:
> The LUKS spec requires that header strings are NUL-terminated, and our
> code relies on that. Protect against maliciously crafted headers by
> adding validation.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> crypto/block-luks.
On 9/6/22 10:28, Richard Henderson wrote:
On 9/6/22 10:11, Richard Henderson wrote:
The goal here is to reduce the amount of code generation when the
guest kernel enables address space randomization. This requires
extensive changes to each target, so opt-in with TARGET_TB_PCREL.
This is split
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 40 --
target/arm/translate.c | 10 ++
2 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/target
The DisasContext member and the disas_insn local variable of
the same name are identical to DisasContextBase.pc_next.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 114 +++-
1 file changed, 60 insertions(+), 54 deletions(-)
diff --git a/targe
> In any case, the only thing that "mayfail" seems to control, is in
> module_load_file, and is a single printf:
>
> g_module = g_module_open(fname, flags);
> if (!g_module) {
> if (!mayfail) {
> fprintf(stderr, "Failed to open module: %s\n",
> g_mo
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 ++
target/arm/translate.h | 6
target/arm/cpu.c | 23 +++---
target/arm/translate-a64.c | 37 ++-
target/arm/translate.c | 62 ++
5 files c
Like gen_update_cc_op, sync EIP before doing something
that could raise an exception. Replace all gen_jmp_im
that use s->base.pc_next.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 52 -
1 file changed, 28 insertions(+), 24 deletions(-)
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/
This is the Arm specific changes required to reduce the
amount of translation for address space randomization.
This is a re-base and split, with no other significant
changes over v3.
r~
Based-on: 20220906091126.298041-1-richard.hender...@linaro.org
("[PATCH v4 0/7] tcg: pc-relative translation
Add a few DISAS_TARGET_* aliases to reduce the number of
calls to gen_eob() and gen_eob_inhibit_irq(). So far,
only update i386_tr_translate_insn for exiting the block
because of single-step or previous inhibit irq.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 23 +
This is the x86 specific changes required to reduce the
amount of translation for address space randomization.
This is a re-base, with no other significant changes over v1.
r~
Based-on: 20220906091126.298041-1-richard.hender...@linaro.org
("[PATCH v4 0/7] tcg: pc-relative translation blocks")
A simple helper to retrieve the length of the current insn.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 5 +
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.h b/
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4d13e365e2
Replace sequences of gen_update_cc_op, gen_update_eip_next,
and gen_eob with the new is_jmp enumerator.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 40 -
1 file changed, 13 insertions(+), 27 deletions(-)
diff --git a/target/i386/tcg/tra
All callers pass s->base.pc_next and s->pc, which we can just
as well compute within the functions. Pull out common helpers
and reduce the amount of code under macros.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 116 ++--
1 file changed, 57
All callers pass s->base.pc_next - s->cs_base, which we can just
as well compute within the function. Note the special case of
EXCP_VSYSCALL in which s->cs_base didn't have the subtraction,
but cs_base is always zero in 64-bit mode, when vsyscall is used.
Signed-off-by: Richard Henderson
---
ta
In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.
Signed-off-by: Richard Henderson
---
target/arm/translate-a32.h | 2 +-
target/arm/translate.h | 6 ++--
target/arm/translate-a64.c | 32 +-
target/arm/translate-vfp.c | 2 +
Create a common helper for pc-relative branches.
The jmp jb insn was missing a mask for CODE32.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 57 ++---
1 file changed, 27 insertions(+), 30 deletions(-)
diff --git a/target/i386/tcg/translate.c
Create helpers for loading the address of the next insn.
Use tcg_constant_* in adjacent code where convenient.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 44 +++--
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/i386/
Signed-off-by: Richard Henderson
---
target/i386/cpu-param.h | 1 +
target/i386/tcg/tcg-cpu.c | 8 ++--
target/i386/tcg/translate.c | 86 ++---
3 files changed, 77 insertions(+), 18 deletions(-)
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.
Set is_jmp properly in gen_movl_seg_T0, so that the callers
need to nothing special.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 36 +---
1 file changed, 5 insertions(+), 31 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i38
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 4 ++--
target/arm/translate-a64.c| 28 +++--
target/arm/translate-m-nocp.c | 6 +++---
target/arm/translate-mve.c| 2 +-
ta
With gen_jmp_rel, we may chain between two translation blocks
which may only be separated because of TB size limits.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
i
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