On 8/25/2022 7:36 PM, Gerd Hoffmann wrote:
On Tue, Aug 02, 2022 at 03:47:25PM +0800, Xiaoyao Li wrote:
Bit 28, named SEPT_VE_DISABLE, disables EPT violation conversion to #VE
on guest TD access of PENDING pages when set to 1. Some guest OS (e.g.,
Linux TD guest) may require this bit set as 1. Ot
Set data_end to the end of the last cluster inside the image.
In such a way we can be shure that corrupted offsets in the BAT
can't affect on the image size.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/block/parallels.c b/block/para
This helper will be reused in next patches during parallels_co_check
rework to simplify its code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/parallels.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff
Replace the way we use mutex in parallels_co_check() for simplier
and less error prone code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/block/parallels.
> First, multiple QEMU instances cannot access nvme:// devices sharing the
> same IOMMU group. I don't think this will ever be possible because it
> opens a backdoor around process memory isolation.
>
> However, a single QEMU (or qemu-storage-daemon) instance should be able
> to access multiple n
Shellcheck correctly reports that we set python_version and never use
it. This is a leftover from commit f9332757898a7: we used to use
python_version purely to as part of the summary information printed
at the end of a configure run, and that commit changed to printing
the information from meson (
Shellcheck warns that we have one place where we run a command and
then check if it failed using $?; this is better written to simply
check the command in the 'if' statement directly.
Signed-off-by: Peter Maydell
---
configure | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a
Currently if you run shellcheck on our configure script it
generates a ton of warnings. This patchset fixes some of the
easier ones. I wasn't aiming for completeness or consistency;
I just wanted to zap some of the ones where the fix is clear
and didn't take long to write and is hopefully easy to r
Shellcheck warns that in
rm -f */config-devices.mak.d
the glob might expand to something with a '-' in it, which would
then be misinterpreted as an option to rm. Fix this by adding './'.
Signed-off-by: Peter Maydell
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
We use the non-POSIX 'local' keyword in just two places in configure;
rewrite to avoid it.
In do_compiler(), just drop the 'local' keyword. The variable
'compiler' is only used elsewhere in the do_compiler_werror()
function, which already uses the variable as a normal non-local one.
In probe_tar
The meson_args variable was added in commit 3b4da13293482134b, but
was not used in that commit and isn't used today. Delete the
unnecessary assignment.
Signed-off-by: Peter Maydell
---
configure | 1 -
1 file changed, 1 deletion(-)
diff --git a/configure b/configure
index efe28050234..b1acaca6
This commit adds quotes in some places which:
* are spotted by shellcheck
* are obviously incorrect
* are easy to fix just by adding the quotes
It doesn't attempt fix all of the places shellcheck finds errors,
or even all the ones which are easy to fix. It's just a random
sampling which is hope
There's only one place in configure where we use `...` to execute a
command and capture the result. Switch to $() to match the rest of
the script. This silences a shellcheck warning.
Signed-off-by: Peter Maydell
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/c
/legoater/qemu/ tags/pull-aspeed-20220825
for you to fetch changes up to 7ccff968f65cfad573bc0015cb0ab800d4337a6e:
hw/i2c/aspeed: Fix old reg slave receive (2022-08-25 10:46:42 +0200)
Aspeed queue:
* hw/i2c/aspeed: Fix old reg
On 8/25/2022 6:12 PM, Gerd Hoffmann wrote:
Hi,
+r = tdx_platform_ioctl(KVM_TDX_CAPABILITIES, 0, caps);
+if (r == -E2BIG) {
+g_free(caps);
+nr_cpuid_configs *= 2;
+if (nr_cpuid_configs > KVM_MAX_CPUID_ENTRIES) {
+error_report
On 8/24/22 23:48, Paolo Bonzini wrote:
On 8/25/22 02:23, Richard Henderson wrote:
+ op->v = v;
+}
Surely this assignment...
+static void gen_writeback(DisasContext *s, X86DecodedOp *op)
+{
...
+ case X86_ALU_GPR:
+ gen_op_mov_reg_v(s, op->ot, op->n, s->T0);
... can be used h
On 8/25/22 05:34, Paolo Bonzini wrote:
Cover all BMI1 and BMI2 instructions, both 32- and 64-bit.
Due to the use of inlines, the test now has to be compiled with -O2.
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 1 +
tests/tcg/i386/test-i386-bmi2.c | 169
On 8/25/22 05:34, Paolo Bonzini wrote:
Include test-i386-bmi2, and specify manually the tests (only one for now)
that need -cpu max.
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/x86_64/Makefile.target | 4 +++-
2 files changed, 4 insertions(+), 2 delet
The computation must not overwrite neither the destination
nor the source before the last element has been computed.
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 49 +--
1 file changed, 29 insertions(+), 20 deletions(-)
diff --git a/target/i38
On 8/25/22 08:48, Paolo Bonzini wrote:
The computation must not overwrite neither the destination
nor the source before the last element has been computed.
Too many negatives. Clearer to use use either/or.
Reviewed-by: Richard Henderson
r~
Create virgl renderer context with flags using context_id when valid.
v2:
- The feature can be enabled via the context_init config option.
- A warning message will be emitted and the feature will not be used
when linking with virglrenderer versions without context_init support.
Signed-off-by: A
This is a different attempt at upstreaming the work I have been doing to
enable support for the Venus Virtio-GPU Vulkan driver.
I believe the previous one [0] was a bit too much stuff in one place,
therefore with this I would like to try a more fine-grained approach.
I will just start by the CONT
Hi
On arm/virt platform, Chen Xiang reported a Guest crash while
attempting the below steps,
1. Launch the Guest with nvdimm=on
2. Hot-add a NVDIMM dev
3. Reboot
4. Guest boots fine.
5. Reboot again.
6. Guest boot fails.
QEMU_EFI reports the below error:
ProcessCmdAddPointer: invalid pointer val
Philippe Mathieu-Daudé writes:
> On 24/8/22 19:29, Alex Bennée wrote:
>> Thomas Huth writes:
>>
>>> It's still based on Fedora 30 - which is not supported anymore by QEMU
>>> since years. Seems like nobody is using (and refreshing) this, and it's
>>> easier to test this via a container anyway
On Wed, Aug 24, 2022 at 3:35 AM Bin Meng wrote:
> From: Bin Meng
>
> The test cases 'test_{tx,rx}' call socketpair() which does not exist
> on win32. Exclude them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Hao Wu
> ---
>
> tests/qtest/npcm7xx_emc-test.c | 8
> 1 file changed, 8 ins
The DPPS (Dot Product) instruction is defined to first sum pairs of
intermediate results, then sum those values to get the final result.
i.e. (A+B)+(C+D)
We incrementally sum the results, i.e. ((A+B)+C)+D, which can result
in incorrect rouding.
For consistency, also change the variable names to t
The DPPS (Dot Product) instruction is defined to first sum pairs of
intermediate results, then sum those values to get the final result.
i.e. (A+B)+(C+D)
We incrementally sum the results, i.e. ((A+B)+C)+D, which can result
in incorrect rouding.
For consistency, also change the variable names to t
If finalize chardev-msmouse or chardev-wctable is called immediately after
init it cases QEMU to crash with segfault. This happens because of
QTAILQ_REMOVE in qemu_input_handler_unregister tries to dereference
NULL pointer.
For instance, this error can be reproduced via `qom-list-properties`
comman
On 8/25/22 09:48, Paolo Bonzini wrote:
The DPPS (Dot Product) instruction is defined to first sum pairs of
intermediate results, then sum those values to get the final result.
i.e. (A+B)+(C+D)
We incrementally sum the results, i.e. ((A+B)+C)+D, which can result
in incorrect rouding.
For consist
On 25/08/2022 16.02, Philippe Mathieu-Daudé wrote:
On 24/8/22 19:29, Alex Bennée wrote:
Thomas Huth writes:
It's still based on Fedora 30 - which is not supported anymore by QEMU
since years. Seems like nobody is using (and refreshing) this, and it's
easier to test this via a container anywa
This allows to simplify the code. Rename to status while we're at it.
Signed-off-by: Eugenio Pérez
---
v3: Rename it to status.
---
net/vhost-vdpa.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 6ce68fcd3f.
Finally enable SVQ with MQ feature.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index c6cbe2fb5c..4bc3fd01a8 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -94,6 +94,7 @@ static const uint64_t
So we are sure we can update the device model properly before sending to
the device.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 3950e4f25d..c6cbe2fb5c 100644
--- a/net/vhost-vdpa.c
+++ b
Same way as with the MAC, restore the expected number of queues at
device's start.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index e799e744cd..3950e4f25d 100644
--- a/net/v
This series enables shadowed CVQ to intercept multiqueue commands through
shadowed CVQ, update the virtio NIC device model so qemu send it in a
migration, and the restore of that MQ state in the destination.
It needs to be applied on top of [1].
[1] https://lists.gnu.org/archive/html/qemu-devel/2
It was returned as error before. Instead of it, simply update the
corresponding field so qemu can send it in the migration data.
Signed-off-by: Eugenio Pérez
---
hw/net/virtio-net.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/ne
Since there may be many commands we need to issue to load the NIC
state, let's split them in individual functions
Signed-off-by: Eugenio Pérez
--
v2: Add vhost_vdpa_net_load_cmd helper
v3: Move ctrl header definition to vhost_vdpa_net_load_cmd
---
net/vhost-vdpa.c | 62 ++
The Windows jobs are currently aborting at weird places - and
there's the suspicion that it's due to memory constraints in
the Windows containers. Let's switch to single-threaded compilation
to decrease the pressure on the memory load, and to make the
jobs more deterministic for further investigati
Hi Elena, Jagannathan & John!
I noticed that the libvfio-user test-client-server test is recently hanging
in the check-system-centos jobs in QEMU's gitlab-CI. Normally the test
finishes within 20 minutes, see e.g. here:
https://gitlab.com/qemu-project/qemu/-/jobs/2928561403
(notice that
On Aug 25, 2022, at 3:54 PM, Thomas Huth
mailto:th...@redhat.com>> wrote:
Hi Elena, Jagannathan & John!
I noticed that the libvfio-user test-client-server test is recently hanging in
the check-system-centos jobs in QEMU's gitlab-CI. Normally the test finishes
within 20 minutes, see e.g. her
From: Klaus Jensen
This is a re-spin of Jinhao's irqfd support series that fixes msix
vector masking/unmasking to work correctly.
I kept being bugged out about that msi route not getting updated, so I
hit the code into submission with a hammer.
I finally noticed the core issue:
1. The vector
From: Jinhao Fan
When the new option 'irq-eventfd' is turned on, the IO emulation code
signals an eventfd when it want to (de)assert an irq. The main loop
eventfd handler does the actual irq (de)assertion. This paves the way
for iothread support since QEMU's interrupt emulation is not thread
saf
From: Jinhao Fan
Use KVM's irqfd to send interrupts when possible. This approach is
thread safe. Moreover, it does not have the inter-thread communication
overhead of plain event notifiers since handler callback are called
in the same system call as irqfd write.
Signed-off-by: Jinhao Fan
Signed
.
Thanks,
C.
r~
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-20220825
for you to fetch changes up to 7ccff968f65cfad573bc0015cb0ab800d4337a6e:
hw/i2c/aspeed: Fix old reg slave receive (2022-08-25 10:46:42 +0200
From: Paul Brook
Add a flags field each row in sse_op_table6 and sse_op_table7.
Initially this is only used as a replacement for the magic
SSE41_SPECIAL pointer. The other flags will become relevant
as the rest of the avx implementation is built out.
Signed-off-by: Paul Brook
Message-Id: <202
From: Paul Brook
Add a flags field each row in sse_op_table1.
Initially this is only used as a replacement for the magic
SSE_SPECIAL and SSE_DUMMY pointers, the other flags will become relevant
as the rest of the AVX implementation is built out.
Signed-off-by: Paul Brook
Message-Id: <202204242
This is the first half of Paul's series from last April, reorganized
to have no occurrence of YMM_ONLY or SHIFT == 2---meaning it can be
committed without much fuss, even without a plan for the implementation
of AVX decoding.
In most cases this is done by using loops that apply the same code for
a
From: Paul Brook
For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of
floating point helpers. Add the register type suffix to the existing
*PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors)
No functional changes.
Signed-off-by: Paul Brook
Message
From: Paul Brook
Rewrite the "simple" vector integer helpers in preperation for AVX support.
While the current code is able to use the same prototype for unary
(a = F(b)) and binary (a = F(b, c)) operations, future changes will cause
them to diverge.
No functional changes to existing helpers
S
From: Paul Brook
More perparatory work for AVX support in various integer vector helpers
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-13-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 164 +++
From: Paul Brook
Handle 3DNOW instructions early to avoid complicating the AVX logic.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-25-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 30 +-
1 file changed, 17 insertions
From: Paul Brook
Perpare the horizontal atithmetic vector helpers for AVX
These currently use a dummy Reg typed variable to store the result then
assign the whole register. This will cause 128 bit operations to corrupt
the upper half of the register, so replace it with explicit temporaries
and e
From: Paul Brook
Prepare the "easy" floating point vector helpers for AVX
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-16-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 138 --
From: Paul Brook
Reject invalid VEX encodings on MMX instructions.
Signed-off-by: Paul Brook
Reviewed-by: Richard Henderson
Message-Id: <20220424220204.2493824-7-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 26 ++
1 file changed, 26 in
From: Paul Brook
Make the pclmulqdq helper AVX ready
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-21-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/target
From: Paul Brook
Make the dpps and dppd helpers AVX-ready
I can't see any obvious reason why dppd shouldn't work on 256 bit ymm
registers, but both AMD and Intel agree that it's xmm only.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-17-p...@nowt.org>
Signed-off-by: Paolo Bonzi
From: Paul Brook
Rewrite the vector shift helpers in preperation for AVX support (3 operand
form and 256 bit vectors).
For now keep the existing two operand interface.
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-11-p...@nowt.org>
Si
This is a bunch of related changes leading up to building ROMs
with container-based cross compilers:
- detect pc-bios/ CC options just once instead of using make's $(shell)
function
- move CC option detection to tests/tcg Makefiles from QEMU's root
configure
- put all configuration of tests/
In preparation for adding Docker container support, detect compiler options
just once rather than once per Make run; container startup overhead is
substantial and doing the detection just once makes things faster.
Signed-off-by: Paolo Bonzini
---
pc-bios/s390-ccw/Makefile| 33 +++
From: Paul Brook
Rewrite the blendv helpers so that they can easily be extended to support
the AVX encodings, which make all 4 arguments explicit.
No functional changes to the existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-20-p...@nowt.org>
Signed-off-by: Paolo
From: Paul Brook
Add a convenience macro to get the address of an xmm_regs element within
CPUX86State.
This was originally going to be the basis of an implementation that broke
operations into 128 bit chunks. I scrapped that idea, so this is now a purely
cosmetic change. But I think a worthwhile
Just use using the compiler binary, with -nostdlib in the case of the
linker; the compiler driver (whether i686-*-gcc, or x86_64-*-gcc with
the -m32 option) will then pick the right magic option to as and ld.
Signed-off-by: Paolo Bonzini
---
configure | 22 +-
For now, return 1 for container-based compilers. This will change as
soon as ROMs will be buildable with them.
Signed-off-by: Paolo Bonzini
---
configure | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index c533eaada0..6f15f3c687 100755
From: Paul Brook
Make the AES vector helpers AVX ready
No functional changes to existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-22-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 49 +++
1 file cha
From: Paul Brook
These helpers need to take special care to avoid overwriting source values
before the wole result has been calculated. Currently they use a dummy
Reg typed variable to store the result then assign the whole register.
This will cause 128 bit operations to corrupt the upper half o
In preparation for removing $(DOCKER_SCRIPT) from the tests/tcg configuration
files, have Make use the same container engine that had been probed at
configure time.
Signed-off-by: Paolo Bonzini
---
configure | 11 ---
tests/docker/Makefile.include | 2 +-
2 files cha
In preparation for adding Docker container support, detect compiler options
just once rather than once per Make run; container startup overhead is
substantial and doing the detection just once makes things faster.
Signed-off-by: Paolo Bonzini
---
pc-bios/optionrom/Makefile | 37 +
Signed-off-by: Paolo Bonzini
---
pc-bios/vof/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/pc-bios/vof/Makefile b/pc-bios/vof/Makefile
index 8809c82768..990f26af31 100644
--- a/pc-bios/vof/Makefile
+++ b/pc-bios/vof/Makefile
@@ -19,4 +19,6 @@ vof.elf: entry.o mai
From: Paul Brook
AVX includes additional a more extensive set of comparison predicates,
some of some of which our softfloat implementation does not expose directly.
Rewrite the helpers in terms of floatN_compare for future extensibility.
Signed-off-by: Paul Brook
Signed-off-by: Paolo Bonzini
-
Instead of linking tests/tcg/Makefile.target into the build tree, name
the symbolic link "Makefile" and create it in every target subdirectory.
This makes it possible to just invoke "make" in tests/tcg subdirectories.
Signed-off-by: Paolo Bonzini
---
configure | 3 ++-
tests/Makefil
Make tests/tcg/ppc64le include tests/tcg/ppc64 instead of duplicating
the rules. Because the ppc64le vpath includes tests/tcg/ppc64 but
not vice versa, the tests have to be moved from tests/tcg/ppc64le/
to tests/tcg/ppc64.
Signed-off-by: Paolo Bonzini
---
tests/tcg/ppc64/Makefile.target
Signed-off-by: Paolo Bonzini
---
Makefile | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 13234f2aa4..ef0fbb4dee 100644
--- a/Makefile
+++ b/Makefile
@@ -186,7 +186,7 @@ include $(SRC_PATH)/tests/Makefile.include
all: recurse-all
-ROMS_RULES
From: Paul Brook
Fixup various vector helpers that either trivially exten to 256 bit,
or don't have 256 bit variants.
No functional changes to existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-19-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse
Remove the DOCKER_SCRIPT and TARGET variable from the Makefile invocation
for tests/tcg. For DOCKER_SCRIPT, resolve the path to docker.py in configure;
for TARGET, move it to config-$(TARGET).mak and use a symbolic link to break
the cycle.
The symbolic link is still needed because tests/tcg inclu
It will not be specific to tests/tcg anymore, since it will be possible to
build firmware using container-based cross compilers too.
Signed-off-by: Paolo Bonzini
---
Makefile | 5 -
configure | 15 +++
tests/Makefile.include | 3 ---
3 files changed,
Let write_target_makefile handle both host and container cross compilers.
Signed-off-by: Paolo Bonzini
---
configure | 94 +--
1 file changed, 43 insertions(+), 51 deletions(-)
diff --git a/configure b/configure
index 6dc6a5a48b..37ddd90bb1 10
Signed-off-by: Paolo Bonzini
---
tests/Makefile.include| 11 +++
tests/tcg/Makefile.target | 3 +++
2 files changed, 14 insertions(+)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index caef287957..9ed67721e2 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.in
Remove the symlink to tests/tcg/config-*.mak, which is possible now
that unused target config files are not created anymore.
Signed-off-by: Paolo Bonzini
---
Makefile| 2 +-
configure | 12 +---
meson.build | 2 +-
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/Ma
Almost all invocations of run-test have either "$* on $(TARGET_NAME)"
or "$< on $(TARGET_NAME)" as the last argument. So provide a default
test name, while allowing an escape hatch for custom names.
As an additional simplification, remove the need to do shell quoting.
Signed-off-by: Paolo Bonzin
s390-ccw remains a bit more complex, because the -march=z900 test is done
only for the native cross compiler. Otherwise, all that is needed is
to pass the (now mandatory) target argument to write_target_makefile.
Signed-off-by: Paolo Bonzini
---
configure | 30 ++
1
Further decoupling of tests/tcg from the main QEMU Makefile, and making
the build more similar between the cross compiler case and the vetted
container images.
Signed-off-by: Paolo Bonzini
---
configure | 65 +--
tests/tcg/Makefile.target
Signed-off-by: Paolo Bonzini
---
pc-bios/optionrom/Makefile | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile
index f514e4f84b..b1fff0ba6c 100644
--- a/pc-bios/optionrom/Makefile
+++ b/pc-bios/optionrom/Makef
Signed-off-by: Paolo Bonzini
---
pc-bios/s390-ccw/Makefile| 12 ++--
pc-bios/s390-ccw/netboot.mak | 20 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/pc-bios/s390-ccw/Makefile b/pc-bios/s390-ccw/Makefile
index 965e633f43..10e8f5cb63 100644
--- a
Signed-off-by: Paolo Bonzini
---
pc-bios/vof/Makefile | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/pc-bios/vof/Makefile b/pc-bios/vof/Makefile
index 990f26af31..be8bd96294 100644
--- a/pc-bios/vof/Makefile
+++ b/pc-bios/vof/Makefile
@@ -2,19 +2,26 @@ includ
Hello,
Peter Delevoryas, le jeu. 25 août 2022 15:38:53 -0700, a ecrit:
> It seems like there's support for an IPv6 dns proxy, and there's literally a
> file called "dhcpv6.c" in slirp, but it has a comment saying it only supports
> whatever is necessary for TFTP network boot I guess.
For which DN
I'm having a hard time figuring this out from looking at the code and the
user-level help options.
It seems like there's support for an IPv6 dns proxy, and there's literally a
file called "dhcpv6.c" in slirp, but it has a comment saying it only supports
whatever is necessary for TFTP network boot
On Fri, Aug 26, 2022 at 12:56:10AM +0200, Samuel Thibault wrote:
> Hello,
>
> Peter Delevoryas, le jeu. 25 août 2022 15:38:53 -0700, a ecrit:
> > It seems like there's support for an IPv6 dns proxy, and there's literally a
> > file called "dhcpv6.c" in slirp, but it has a comment saying it only
>
Peter Delevoryas, le jeu. 25 août 2022 16:15:26 -0700, a ecrit:
> On Fri, Aug 26, 2022 at 12:56:10AM +0200, Samuel Thibault wrote:
> > Peter Delevoryas, le jeu. 25 août 2022 15:38:53 -0700, a ecrit:
> > > It seems like there's support for an IPv6 dns proxy, and there's
> > > literally a
> > > file
On 8/25/22 15:13, Paolo Bonzini wrote:
This is the first half of Paul's series from last April, reorganized
to have no occurrence of YMM_ONLY or SHIFT == 2---meaning it can be
committed without much fuss, even without a plan for the implementation
of AVX decoding.
In most cases this is done by u
On 8/25/22 15:13, Paolo Bonzini wrote:
@@ -3112,6 +3165,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
{
int b1, op1_offset, op2_offset, is_xmm, val;
int modrm, mod, rm, reg;
+struct SSEOpHelper_table1 sse_op;
SSEFunc_0_epp sse_fn_epp;
SSEFunc_0_
On Fri, Aug 19, 2022, Kirill A. Shutemov wrote:
> On Fri, Jun 17, 2022 at 09:30:53PM +, Sean Christopherson wrote:
> > > @@ -4088,7 +4144,12 @@ static int direct_page_fault(struct kvm_vcpu
> > > *vcpu, struct kvm_page_fault *fault
> > > read_unlock(&vcpu->kvm->mmu_lock);
> > > else
On 8/25/22 15:13, Paolo Bonzini wrote:
static void gen_sse(CPUX86State *env, DisasContext *s, int b,
target_ulong pc_start)
{
int b1, op1_offset, op2_offset, is_xmm, val;
int modrm, mod, rm, reg;
struct SSEOpHelper_table1 sse_op;
+struct SSEOpHelper
On 8/25/22 15:13, Paolo Bonzini wrote:
From: Paul Brook
Handle 3DNOW instructions early to avoid complicating the AVX logic.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-25-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 30 +--
On 8/25/22 15:13, Paolo Bonzini wrote:
From: Paul Brook
Rewrite the vector shift helpers in preperation for AVX support (3 operand
form and 256 bit vectors).
For now keep the existing two operand interface.
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id:<20220
On Thu, Aug 25, 2022 at 8:14 AM Atish Patra wrote:
>
> This series implements Sstc extension[1] which was ratified recently.
>
> The first patch is a prepartory patches while PATCH 2 adds stimecmp
> support while PATCH 3 adds vstimecmp support. This series is based on
> on top of upstream commit (
On 8/25/22 15:14, Paolo Bonzini wrote:
+#define SSE_HELPER_2(name, elem, num, F)\
+void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
+{ \
+ Reg *v = d;
On 8/25/22 15:14, Paolo Bonzini wrote:
From: Paul Brook
More perparatory work for AVX support in various integer vector helpers
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id:<20220424220204.2493824-13-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i3
On 8/25/22 15:14, Paolo Bonzini wrote:
void glue(helper_pshufd, SUFFIX)(Reg *d, Reg *s, int order)
{
-Reg r;
+uint32_t r0, r1, r2, r3;
-r.L(0) = s->L(order & 3);
-r.L(1) = s->L((order >> 2) & 3);
-r.L(2) = s->L((order >> 4) & 3);
-r.L(3) = s->L((order >> 6) & 3);
-
On 8/25/22 15:14, Paolo Bonzini wrote:
From: Paul Brook
For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of
floating point helpers. Add the register type suffix to the existing
*PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors)
No functional chan
On 8/25/22 15:14, Paolo Bonzini wrote:
From: Paul Brook
Prepare the "easy" floating point vector helpers for AVX
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id:<20220424220204.2493824-16-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h |
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