Tested with https://github.com/ksco/rvv-decoder-tests
Expected checkpatch errors for consistency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Yang Liu
---
disas
On Thu, Aug 18, 2022 at 08:00:41PM -0700, Hugh Dickins wrote:
> tmpfs and hugetlbfs and page cache are designed around sharing memory:
> TDX is designed around absolutely not sharing memory; and the further
> uses which Sean foresees appear not to need it as page cache either.
>
> Except perhaps f
Thank you for the suggestions for CDB sizes! Especially the tricky ones
in spapr_vscsi.c and dev-uas.c.
v2: https://lists.gnu.org/archive/html/qemu-devel/2022-08/msg02997.html
On Fri, Aug 19, 2022 at 06:06:13PM +0200, Paolo Bonzini wrote:
> On 8/17/22 07:34, John Millikin wrote:
> > The sigil SCS
The DMA engine is started by I/O access and then itself accesses the
I/O registers, triggering a reentrancy bug.
The following log can reveal it:
==5637==ERROR: AddressSanitizer: stack-overflow
#0 0x5595435f6078 in tulip_xmit_list_update qemu/hw/net/tulip.c:673
#1 0x5595435f204a in tulip_w
The DMA engine is started by I/O access and then itself accesses the
I/O registers, triggering a reentrancy bug.
The following log can reveal it:
==5637==ERROR: AddressSanitizer: stack-overflow
#0 0x5595435f6078 in tulip_xmit_list_update qemu/hw/net/tulip.c:673
#1 0x5595435f204a in tulip_w
On Fri, Aug 19, 2022 at 1:26 PM Richard Henderson
wrote:
>
> From: Ilya Leoshkevich
>
> Introduce a function that checks whether a given address is on the same
> page as where disassembly started. Having it improves readability of
> the following patches.
>
> Signed-off-by: Ilya Leoshkevich
> Me
On Fri, Aug 19, 2022 at 1:29 PM Richard Henderson
wrote:
>
> The mmap_lock is held around tb_gen_code. While the comment
> is correct that the lock is dropped when tb_gen_code runs out
> of memory, the lock is *not* dropped when an exception is
> raised reading code for translation.
>
> Signed-of
On Fri, Aug 19, 2022 at 1:33 PM Richard Henderson
wrote:
>
> The function is not used outside of cpu-exec.c. Move it and
> its subroutines up in the file, before the first use.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> include/exec/exec-all.h | 3
On Fri, Aug 19, 2022 at 1:34 PM Richard Henderson
wrote:
>
> The base qemu_ram_addr_from_host function is already in
> softmmu/physmem.c; move the nofail version to be adjacent.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> include/exec/cpu-common.h | 1
On Fri, Aug 19, 2022 at 1:36 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> include/exec/exec-all.h | 10 +-
> accel/tcg/cputlb.c | 8
> accel/tcg/plugin-gen.c | 4 ++--
> accel/tcg/user-exec.c | 4 +
On Fri, Aug 19, 2022 at 1:40 PM Richard Henderson
wrote:
>
> The current implementation is a no-op, simply returning addr.
> This is incorrect, because we ought to be checking the page
> permissions for execution.
>
> Make get_page_addr_code inline for both implementations.
>
> Signed-off-by: Rich
On Fri, Aug 19, 2022 at 1:40 PM Richard Henderson
wrote:
>
> We currently ignore PROT_EXEC on the initial lookup, and
> defer raising the exception until cpu_ld*_code().
> It makes more sense to raise the exception early.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
On Fri, Aug 19, 2022 at 1:36 PM Richard Henderson
wrote:
>
> The only user can easily use translator_lduw and
> adjust the type to signed during the return.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> include/exec/translator.h | 1 -
> target/i386/tc
From: Wilfred Mallawa
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/i
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 34 --
From: Wilfred Mallawa
This patch series cleans up the ibex_spi driver,
fixes the specified coverity issue,
implements register rw1c functionality and
updates an incorrect register offset.
Patch V3 fixes up:
- Style errors (excess indentation on multi-line)
- Remove patch note from commit
From: Wilfred Mallawa
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1 insertio
On Fri, Aug 19, 2022 at 1:42 PM Richard Henderson
wrote:
>
> Pass these along to translator_loop -- pc may be used instead
> of tb->pc, and host_pc is currently unused. Adjust all targets
> at one time.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> include
On Fri, Aug 19, 2022 at 1:42 PM Richard Henderson
wrote:
>
> These will be useful in properly ending the TB.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html
Fixes: Coverity CID 1488107
Signed-off-by: Wilfr
On Fri, Aug 19, 2022 at 1:39 PM Richard Henderson
wrote:
>
> Right now the translator stops right *after* the end of a page, which
> breaks reporting of fault locations when the last instruction of a
> multi-insn translation block crosses a page boundary.
>
> Resolves: https://gitlab.com/qemu-proj
Reviewed-by: Jim Shu
On Fri, Aug 19, 2022 at 3:11 PM Tommy Wu wrote:
>
> Fix the type of parent_obj of SiFiveEState from 'SysBusDevice'
> to 'MachineState'. Because the parent of SiFiveEState is 'MachineState'.
>
> Signed-off-by: Tommy Wu
> ---
> include/hw/riscv/sifive_e.h | 2 +-
> 1 file c
On Fri, Aug 19, 2022 at 06:42:34AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 8/18/22 23:11, Alexey Kardashevskiy wrote:
> >
> >
> > On 05/08/2022 19:39, Daniel Henrique Barboza wrote:
> > > The pSeries machine never bothered with the common machine->fdt
> > > attribute. We do all the FDT r
On 22/08/2022 13:05, David Gibson wrote:
On Fri, Aug 19, 2022 at 06:42:34AM -0300, Daniel Henrique Barboza wrote:
On 8/18/22 23:11, Alexey Kardashevskiy wrote:
On 05/08/2022 19:39, Daniel Henrique Barboza wrote:
The pSeries machine never bothered with the common machine->fdt
attribute.
On Fri, Aug 19, 2022 at 5:12 PM Tommy Wu wrote:
>
> Fix the type of parent_obj of SiFiveEState from 'SysBusDevice'
> to 'MachineState'. Because the parent of SiFiveEState is 'MachineState'.
>
> Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/riscv/sifive_e.h
On Thu, Aug 11, 2022 at 5:09 AM Conor Dooley wrote:
>
> From: Conor Dooley
>
> The device trees produced automatically for the virt and spike machines
> fail dt-validate on several grounds. Some of these need to be fixed in
> the linux kernel's dt-bindings, but others are caused by bugs in QEMU.
On Tue, Aug 16, 2022 at 2:54 PM Rahul Pathak wrote:
>
> XVentanaCondOps is Ventana custom extension. Add
> its extension entry in the ISA Ext array
>
> Signed-off-by: Rahul Pathak
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> This patch is based on branch riscv-to-apply.next (Alis
On Mon, Aug 22, 2022 at 9:53 AM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> This patch addresses the coverity issues specified in [1],
> as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
> implemented to clean up the code.
>
> [1] https://www.mail-archive.com/qemu-devel@nongnu
On Sat, Aug 20, 2022 at 2:30 PM Anup Patel wrote:
>
> The arch review of AIA spec is completed and we now have official
> extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
> AIA CSRs).
>
> Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
> https://github.com/ris
On Mon, 2022-08-22 at 13:42 +1000, Alistair Francis wrote:
> On Mon, Aug 22, 2022 at 9:53 AM Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > This patch addresses the coverity issues specified in [1],
> > as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
> > implemented
Hi,
On Fri, Aug 19, 2022 at 10:25:26AM -0500, Andrea Bolognani wrote:
> > func (s QCryptoBlockOpenOptions) MarshalJSON() ([]byte, error) {
> > var bytes []byte
> > var err error
> > if s.Qcow != nil {
> > tmp := struct {
> > QCryptoBlockOptionsQCow
> >
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