On Fri, Aug 19, 2022 at 6:52 AM Juan Quintela wrote:
>
> Leonardo Brás wrote:
> > On Tue, 2022-08-02 at 08:39 +0200, Juan Quintela wrote:
> >> We are going to create a new function for multifd latest in the series.
> >>
> >> Signed-off-by: Juan Quintela
> >> Reviewed-by: Dr. David Alan Gilbert
On Fri, Aug 19, 2022 at 7:03 AM Juan Quintela wrote:
>
> Leonardo Brás wrote:
> > On Tue, 2022-08-02 at 08:39 +0200, Juan Quintela wrote:
> >> Use of flags with respect to locking was incensistant. For the
> >> sending side:
> >> - it was set to 0 with mutex held on the multifd channel.
> >> - M
On Fri, Aug 19, 2022 at 8:32 AM Juan Quintela wrote:
>
> Leonardo Brás wrote:
> > On Tue, 2022-08-02 at 08:39 +0200, Juan Quintela wrote:
> >> We do the send_prepare() and the fill of the head packet without the
> >> mutex held. It will help a lot for compression and later in the
> >> series for
No, I had not seen it indeed. Queued now, thanks.
Paolo
Il gio 4 ago 2022, 14:39 John Millikin ha scritto:
> SunOS expects CD-ROM devices to have a block size of 512, and will
> fail to mount or install using QEMU's default block size of 2048.
>
> When initializing the SCSI device, allow the `p
From: Tobias Röhmel
Thanks for the review!
Here is v3:
v3:
PATCH 2 (Don't add all MIDR aliases for cores that immplement PMSA):
fixed the comment and changed to single element instead of array.
Also the alias is not added for all PMSA CPUs as Peter suggested.
PATCH 3 (Make RVBAR available for al
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
---
target/ar
From: Tobias Röhmel
The Cortex-R52 has a 2 stage MPU translation process but doesn't have the
FEAT_S2FWB feature. This makes it neccessary to allow for the old cache
attribut combination. This is facilitated by changing the control path
of combine_cacheattrs instead of failing if the second cache
From: Tobias Röhmel
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address to be changed with
the rvbar property.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c| 6 +-
target/arm/hel
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h| 10 +++
target/arm/helper.c | 171
2 files changed, 181 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 86e06116a9..632d0d13c6 100644
--- a/target/arm/c
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
---
target/arm/cpu_tcg.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
ind
From: Tobias Röhmel
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel
---
target/arm/helper.c | 14 ++
1 file changed, 10 ins
From: Tobias Röhmel
This flag is necessary to add features for the Cortex-R52.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df677b2d5d..86e06116a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/c
From: Tobias Röhmel
Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare
for the Cortex-R52 MPU which uses and combines cache attributes
of different translation levels.
Signed-off-by: Tobias Röhmel
---
target/arm/internals.h | 13 +++--
target/arm/m_helper.c | 3 ++-
t
From: Tobias Röhmel
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel
---
target/arm/ptw.c | 171 +--
1 file changed, 150 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index c4f5721012..c7e37c66d0 100644
--- a/t
On 8/11/22 10:16, Peter Maydell wrote:
FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD,
which disable the cycle counter from counting at EL2 and EL3.
Add the code to support these bits.
While HCCD is v3p5, it seems MCCD (typo above) is v3p7.
+if (counter == 31) {
+
On 8/11/22 10:16, Peter Maydell wrote:
+static bool pmevcntr_is_64_bit(CPUARMState *env, int counter)
+{
+/* Return true if the specified event counter is configured to be 64 bit */
+
+/* This isn't intended to be used with the cycle counter */
+assert(counter < 31);
+
+if (!cpu_i
On 8/11/22 10:26, Peter Maydell wrote:
On Thu, 11 Aug 2022 at 18:16, Peter Maydell wrote:
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.
Signed-off-by: Peter Maydell
Oops, forgot the docs update:
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/a
I think when Klaus ported his slave mode changes from the original patch
series to the rewritten I2C module, he changed the behavior of the first
byte that is received by the slave device.
What's supposed to happen is that the AspeedI2CBus's slave device's
i2c_event callback should run, and if the
Hey everyone,
I haven't gotten a chance to work on the Aspeed I2C controller in a little
while, but I finally started looking at it again and noticed the
old-register mode slave receive function (master-send-to-slave) does the
wrong thing for the first byte. See the commit message for details.
I
Hello!
Thank you all again for your initial guidance.
I've been able to write an initial Teensy 4.1 machine, for now with only
the few important memory regions initialized, and successfully ran some
hand-written ARM code on it.
I was wondering what your opinions might be for implementing the nex
On Sat, 20 Aug 2022, Kirill A. Shutemov wrote:
>
> Yes, INACCESSIBLE is increase of complexity which you do not want to deal
> with in shmem.c. It get it.
It's not so much that INACCESSIBLE increases the complexity of
memfd/shmem/tmpfs, as that it is completely foreign to it.
And by handling all
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