Re: [PATCH 04/19] ppc/ppc405: Introduce a PPC405 SoC

On 8/1/22 10:10, Cédric Le Goater wrote: It is an initial model to start QOMification of the PPC405 board. Signed-off-by: Cédric Le Goater --- Reviewed-by: Daniel Henrique Barboza hw/ppc/ppc405.h| 17 ++ hw/ppc/ppc405_boards.c | 29 ++- hw/ppc/

Re: [PATCH 1/1] vfio-user: update submodule to latest

On Tue, 2 Aug 2022 at 05:44, Daniel P. Berrangé wrote: > On Mon, Aug 01, 2022 at 09:24:04PM -0400, Jagannathan Raman wrote: > > Update libvfio-user submodule to the latest > > > > Signed-off-by: Jagannathan Raman > > --- > > subprojects/libvfio-user | 2 +- > > 1 file changed, 1 insertion(+), 1

Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function

On Wed, Jul 27, 2022 at 5:56 PM Weiwei Li wrote: > > 在 2022/7/28 上午5:40, Atish Kumar Patra 写道: > > > > On Wed, Jul 27, 2022 at 1:35 AM Weiwei Li wrote: > >> >> 在 2022/7/27 下午2:49, Atish Patra 写道: >> > All the hpmcounters and the fixed counters (CY, IR, TM) can be >> represented >> > as a unified

Re: [PATCH 05/19] ppc/ppc405: Start QOMification of the SoC

On Tue, 2 Aug 2022, Daniel Henrique Barboza wrote: On 8/1/22 10:10, Cédric Le Goater wrote: This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 ++-- hw/ppc/ppc405_boards.c | 12

installing qemu on linux

Good Morning, My name is Victor Herrera and I am attempting to install qemu on linux, I am trying to run CAN Bus well in the process of reseaching all these things. I am research assistant with the University of Texas at El Paso. I tried the link provided in the git repository, but there is an e

Re: [RFC 0/3] Add Generic SPI GPIO model

Thanks everyone for the insightful feedback! This is really helpful for me. I am taking a look at all the comments now and will investigate into it. Best, Iris

[PATCH v12 0/6] Improve PMU support

The latest version of the SBI specification includes a Performance Monitoring Unit(PMU) extension[1] which allows the supervisor to start/stop/configure various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Fil

[PATCH v12 2/6] target/riscv: Simplify counter predicate function

All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng

[PATCH v12 1/6] target/riscv: Add sscofpmf extension support

The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. A

[PATCH v12 6/6] target/riscv: Remove additional priv version check for mcountinhibit

With .min_priv_version, additiona priv version check is uncessary for mcountinhibit read/write functions. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Atish Patra --- target/riscv/csr.c | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/csr.c b/targ

[PATCH v12 4/6] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis Si

[PATCH v12 3/6] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off-b

[PATCH v12 5/6] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30 delet

Re: [PATCH v5 0/1] target/riscv: Add Zihintpause support

On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis wrote: > > On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote: > > > > This patch adds RISC-V Zihintpause support. The extension is set to be > > enabled > > by default and opcode has been added to insn32.decode. > > > > Added trans_pause to exit the TB

[PULL 0/1] semihosting patch queue

The following changes since commit 430a388ef4a6e02e762a9c5f86c539f886a6a61a: Merge tag 'pull-migration-20220802c' of https://gitlab.com/dagrh/qemu into staging (2022-08-02 10:03:18 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-sem

Re: [PATCH 1/2] hw/arm/virt: Improve address assignment for highmem IO regions

Hi Eric, On 8/2/22 7:41 PM, Eric Auger wrote: On 8/2/22 08:45, Gavin Shan wrote: There are 3 highmem IO regions as below. They can be disabled in two situations: (a) The specific region is disabled by user. (b) The specific region doesn't fit in the PA space. However, the base address and highe

[PULL 1/1] target/mips: Advance pc after semihosting exception

Delay generating the exception until after we know the insn length, and record that length in env->error_code. Fixes: 8ec7e3c53d4 ("target/mips: Use an exception for semihosting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richa

Re: [PATCH] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

On Fri, Jul 29, 2022 at 2:19 AM Daniel Henrique Barboza wrote: > > The 'fdt' param is not being used in riscv_setup_rom_reset_vec(). > Simplify the API by removing it. While we're at it, remove the redundant > 'return' statement at the end of function. > > Cc: Palmer Dabbelt > Cc: Alistair Franci

Re: [PULL 9/9] hw/i386: pass RNG seed via setup_data entry

On 8/2/2022 11:13 PM, Jason A. Donenfeld wrote: Hi Xiaoyao, On Tue, Aug 2, 2022 at 5:06 PM Jason A. Donenfeld wrote: Hi Xiaoyao, On Tue, Aug 02, 2022 at 10:53:07PM +0800, Xiaoyao Li wrote: yes, with >= 7.1, pcmc->legacy_no_rng_seed = false by default, and RNG seed is used. This is intende

Re: [PATCH] hw/nvme: Add helper functions for qid-db conversion

at 4:54 PM, Klaus Jensen wrote: > I am unsure if the compiler will transform that division into the shift > if it can infer that the divisor is a power of two (it most likely > will be able to). > > But I see no reason to have a potential division here when we can do > without and to me it is ju

[PATCH v2] hw/nvme: Add helper functions for qid-db conversion

With the introduction of shadow doorbell and ioeventfd, we need to do frequent conversion between qid and its doorbell offset. The original hard-coded calculation is confusing and error-prone. Add several helper functions to do this task. Signed-off-by: Jinhao Fan --- Changes since v1: - Use lef

Re: [PATCH v12 1/6] target/riscv: Add sscofpmf extension support

在 2022/8/3 上午7:33, Atish Patra 写道: The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmabl

Re: [PATCH] hw/nvme: Add helper functions for qid-db conversion

On Wed, Aug 03, 2022 at 09:46:05AM +0800, Jinhao Fan wrote: > at 4:54 PM, Klaus Jensen wrote: > > > I am unsure if the compiler will transform that division into the shift > > if it can infer that the divisor is a power of two (it most likely > > will be able to). > > > > But I see no reason to

Re: [PATCH v5 0/1] target/riscv: Add Zihintpause support

On Wed, Aug 3, 2022 at 9:42 AM Atish Patra wrote: > > On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis wrote: > > > > On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote: > > > > > > This patch adds RISC-V Zihintpause support. The extension is set to be > > > enabled > > > by default and opcode has be

Re: [PATCH] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

On Fri, Jul 29, 2022 at 4:19 AM Daniel Henrique Barboza wrote: > > The 'fdt' param is not being used in riscv_setup_rom_reset_vec(). > Simplify the API by removing it. While we're at it, remove the redundant > 'return' statement at the end of function. > > Cc: Palmer Dabbelt > Cc: Alistair Franci

Re: [PULL 0/1] semihosting patch queue

https://gitlab.com/rth7680/qemu.git tags/pull-semi-20220802 for you to fetch changes up to d44971e725c02e0656d2f53d4fb564f92e06aef7: target/mips: Advance pc after semihosting exception (2022-08-02 12:34:00 -0700) Fix mips semihosting

Re: [PATCH 2/2] hw/arm/virt: Warn when high memory region is disabled

Hi Eric, On 8/2/22 7:49 PM, Eric Auger wrote: On 8/2/22 08:45, Gavin Shan wrote: When one specific high memory region is disabled due to the PA limit, it'd better to warn user about that. The warning messages help to identify the cause in some cases. For example, PCIe device that has large MMIO

Re: [PATCH v12 1/6] target/riscv: Add sscofpmf extension support

On Tue, Aug 2, 2022 at 7:13 PM Weiwei Li wrote: > > 在 2022/8/3 上午7:33, Atish Patra 写道: > > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, > > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) > > extension allows the perf to handle overflow interrupts and filt

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