Gentle ping.
Regards,
eop Chen
> ~eopxd 於 2022年6月20日 下午2:50 寫道：
>
> According to v-spec, mask agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of mask policies, QEMU should be able to simulate the mask
> agnostic behavior as
On Fri, Jul 8, 2022 at 2:51 PM Markus Armbruster wrote:
>
> Eugenio Perez Martin writes:
>
> > On Thu, Jul 7, 2022 at 8:23 AM Markus Armbruster wrote:
> >>
> >> Eugenio Pérez writes:
> >>
> >> > Finally offering the possibility to enable SVQ from the command line.
> >>
> >> QMP, too, I guess.
>
On Fri, Jul 8, 2022 at 2:53 PM Markus Armbruster wrote:
>
> Eugenio Pérez writes:
>
> > Finally offering the possibility to enable SVQ from the command line.
> >
> > Signed-off-by: Eugenio Pérez
>
> Please carry forward Acked-by and Reviewed-by you received for prior
> revisions unless you chang
Am 08/07/2022 um 21:25 schrieb Vladimir Sementsov-Ogievskiy:
>> static bool job_started(Job *job)
>
> So we can call it both with mutex locked and without. Hope it never race
> with job_start.
Where exactly do you see it called with mutex not held?
I don't see it anywhere, and if you agree
On 06/07/2022 08:45, Cédric Le Goater wrote:
On 7/5/22 08:57, Cédric Le Goater wrote:
On 7/5/22 08:51, Mark Cave-Ayland wrote:
On 04/07/2022 18:34, Cédric Le Goater wrote:
On 7/2/22 15:34, Daniel Henrique Barboza wrote:
On 7/2/22 03:24, Cédric Le Goater wrote:
On 6/30/22 21:42, Daniel He
On 05/07/2022 15:58, Cédric Le Goater wrote:
Hello,
This replaces the IRQ array 'irq_inputs' with GPIO lines and removes
'irq_inputs' when all CPUs have been converted.
Thanks,
C.
Cédric Le Goater (5):
ppc64: Allocate IRQ lines with qdev_init_gpio_in()
ppc/40x: Allocate IRQ lines with
On 7/11/22 09:37, Mark Cave-Ayland wrote:
On 06/07/2022 08:45, Cédric Le Goater wrote:
On 7/5/22 08:57, Cédric Le Goater wrote:
On 7/5/22 08:51, Mark Cave-Ayland wrote:
On 04/07/2022 18:34, Cédric Le Goater wrote:
On 7/2/22 15:34, Daniel Henrique Barboza wrote:
On 7/2/22 03:24, Cédric Le
From: Marc-André Lureau
Hi
This is a small series to attempt to debug "Intermittent meson failures on
msys2" and improve a bit msys2/gitlab reports.
Marc-André Lureau (2):
gitlab-ci: grab msys2 meson-logs as artifacts
gitlab-ci: add msys2 meson test to junit report
.gitlab-ci.d/windows.ym
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
.gitlab-ci.d/windows.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index 4e5c348e59ba..63d89fbefe08 100644
--- a/.gitlab-ci.d/windows.yml
+++ b/.gitlab-ci.d/windows.yml
@
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
.gitlab-ci.d/windows.yml | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index 1b2ede49e1ac..4e5c348e59ba 100644
--- a/.gitlab-ci.d/windows.yml
+++ b/.gitl
在 2022/7/7 02:39, Eugenio Pérez 写道:
VirtQueueElement comes from the guest, but we're heading SVQ to be able
to inject element without the guest's knowledge.
To do so, make this accept sg buffers directly, instead of using
VirtQueueElement.
Add vhost_svq_add_element to maintain element conveni
Fixes: c09c1ce7e9 ("configure: switch directory options to automatic parsing",
2022-05-07)
Signed-off-by: Paolo Bonzini
---
meson_options.txt | 2 +-
scripts/meson-buildoptions.sh | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/meson_options.txt b/meson_options
On Fri, Jul 8, 2022 at 3:39 PM Kito Cheng wrote:
> Default ELEN is setting to 64 for now, which is incorrect setting for
> Zve32*, and spec has mention minimum VLEN and supported EEW in chapter
> "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32.
>
> ELEN actaully could be derived
On 7/7/22 21:04, Peter Delevoryas wrote:
On Thu, Jul 07, 2022 at 10:53:57AM -0700, Peter Delevoryas wrote:
On Thu, Jul 07, 2022 at 10:56:02AM +0200, Cédric Le Goater wrote:
On 7/7/22 09:17, Peter Delevoryas wrote:
It seems that aspeed_gpio_update is allowing the value for input pins to be
modi
On Fri, Jul 8, 2022 at 4:57 PM Kito Cheng wrote:
> Add new option for -d vu to dump the content of vector unit, many target
> has vector register, but there is no easy way to dump the content, we
> use this on downstream for a while to help debug, and I feel that's
> really useful, so I think it
On Mon, Jul 11, 2022 at 10:00 AM Jason Wang wrote:
>
>
> 在 2022/7/7 02:39, Eugenio Pérez 写道:
> > VirtQueueElement comes from the guest, but we're heading SVQ to be able
> > to inject element without the guest's knowledge.
> >
> > To do so, make this accept sg buffers directly, instead of using
> >
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
This comment applies more on job, it was left in blockjob as in the past
the whole job logic was implemented there.
Note: at this stage, job_{lock/unlock} and job lock guard macros
are*nop*.
No functional change intended.
Signed-off-by: Emanue
在 2022/7/7 02:39, Eugenio Pérez 写道:
This will allow SVQ to add metadata to the different queue elements. To
simplify changes, only store actual element at this patch.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 8 --
hw/virtio/vhost-shadow-virtqueue.c | 41 ++
在 2022/7/7 02:39, Eugenio Pérez 写道:
We will allow SVQ user to store opaque data for each element, so its
easier if we store this kind of information just at avail.
Signed-off-by: Eugenio Pérez
Note that kernel driver doesn't have this optimization so far. I wonder
if this is not a must,
在 2022/7/7 02:39, Eugenio Pérez 写道:
When qemu injects buffers to the vdpa device it will be used to maintain
contextual data. If SVQ has no operation, it will be used to maintain
the VirtQueueElement pointer.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 3 ++-
hw/
在 2022/7/7 02:39, Eugenio Pérez 写道:
This allows qemu to inject buffers to the device.
Not a native speaker but we probably need a better terminology than
inject here.
Since the CVQ is totally under the control of the Qemu anyhow.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-sha
在 2022/7/7 02:39, Eugenio Pérez 写道:
It allows the Shadow Control VirtQueue to wait the device to use the commands
that restore the net device state after a live migration.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 1 +
hw/virtio/vhost-shadow-virtqueue.c | 54 ++
在 2022/7/7 02:40, Eugenio Pérez 写道:
Shadow CVQ will copy buffers on qemu VA, so we avoid TOCTOU attacks that
can set a different state in qemu device model and vdpa device.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
include/hw/virtio/vhost-vdpa.h | 4
hw/virtio/vhost
On Mon, Jul 11, 2022 at 11:00 AM Jason Wang wrote:
>
>
> 在 2022/7/7 02:39, Eugenio Pérez 写道:
> > This will allow SVQ to add metadata to the different queue elements. To
> > simplify changes, only store actual element at this patch.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > hw/virtio/vhos
On Sun, Jul 10, 2022 at 10:30:03PM +0530, Ani Sinha wrote:
> Changelog:
> v2:
> - a new class of python based tests introduced that is separate from avocado
>tests or qtests. Can be run by using "make check-pytest".
> - acpi biosbits tests are the first tests to use pytest environment.
> - b
On Mon, Jul 11, 2022 at 11:14 AM Jason Wang wrote:
>
>
> 在 2022/7/7 02:39, Eugenio Pérez 写道:
> > This allows qemu to inject buffers to the device.
>
>
> Not a native speaker but we probably need a better terminology than
> inject here.
>
> Since the CVQ is totally under the control of the Qemu any
Signed-off-by: Gerd Hoffmann
---
docs/system/devices/usb.rst | 12
1 file changed, 12 insertions(+)
diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst
index 18e7c8b4d716..f39a88f080ff 100644
--- a/docs/system/devices/usb.rst
+++ b/docs/system/devices/usb.rst
@@ -
Suggested-by: Michal Prívozník
Signed-off-by: Gerd Hoffmann
---
docs/system/devices/usb.rst | 29 +
1 file changed, 29 insertions(+)
diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst
index 872d9167589b..18e7c8b4d716 100644
--- a/docs/system/devic
Gerd Hoffmann (2):
usb: document guest-reset and guest-reset-all
usb: document pcap (aka usb traffic capture)
docs/system/devices/usb.rst | 41 +
1 file changed, 41 insertions(+)
--
2.36.1
Let's use more inclusive language here and avoid terms
that are frowned upon nowadays.
Signed-off-by: Thomas Huth
---
docs/devel/submitting-a-patch.rst | 2 +-
docs/tools/qemu-nbd.rst | 2 +-
scripts/vmstate-static-checker.py | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
di
On Mon, Jul 11, 2022 at 11:05 AM Jason Wang wrote:
>
>
> 在 2022/7/7 02:39, Eugenio Pérez 写道:
> > When qemu injects buffers to the vdpa device it will be used to maintain
> > contextual data. If SVQ has no operation, it will be used to maintain
> > the VirtQueueElement pointer.
> >
> > Signed-off-b
'returns-whitelist' has been renamed to 'command-returns-exceptions' in
commit b86df3747848 ("qapi: Rename pragma *-whitelist to *-exceptions").
Signed-off-by: Thomas Huth
---
python/qemu/qmp/legacy.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/python/qemu/qmp/legacy.py
On 7/9/22 21:51, B wrote:
> Am 1. Juli 2022 16:10:07 UTC schrieb Joao Martins :
>> Use the pre-initialized pci-host qdev and fetch the
>> pci-hole64-size into pc_memory_init() newly added argument.
>> piix needs a bit of care given all the !pci_enabled()
>> and that the pci_hole64_size is private t
Hi Alexander,
Thanks for the reproducer! It looks like ABORT, CLEAR QUEUE and BUS
DEVICE RESET messages can all cancel the current request, so yes I
guess a similar change is needed there, too. Will try to send a v2
soon.
Best regards.
On Sat, Jul 9, 2022 at 2:22 AM Alexander Bulekov wrote:
>
On Fri, 8 Jul 2022 at 12:01, Daniel P. Berrangé wrote:
> What alternative options do we have for addressing this scenario.
>
> I can think of
>
> - Auto-create array elements, if seeing an element set before length.
>
> This is based on the theory that 'len-PROP' field is largely
> redun
On 7/11/22 10:30, Emanuele Giuseppe Esposito wrote:
Am 08/07/2022 um 21:25 schrieb Vladimir Sementsov-Ogievskiy:
static bool job_started(Job *job)
So we can call it both with mutex locked and without. Hope it never race
with job_start.
Where exactly do you see it called with mutex not h
From: Brice Goglin
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/FACP.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.ac
This patch set adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:
Brice Goglin: to support -numa without initiators on q35/x86.
https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
https:
From: Brice Goglin
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by h
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
On Fri, 8 Jul 2022 at 12:40, Markus Armbruster wrote:
>
> Cc'ing QOM maintainers.
>
> Peter Maydell writes:
>
> > On Mon, 4 Jul 2022 at 05:50, Markus Armbruster wrote:
> >> My initial (knee-jerk) reaction to breaking array properties: Faster,
> >> Pussycat! Kill! Kill!
> >
> > In an ideal world,
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
---
hw/arm/Kconfig | 1 +
hw/arm/virt-acpi-build.c | 7 +++
2 files changed, 8 in
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/FACP.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4
5 files chan
This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.
Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_E
* Expected ACPI Data Table [HMAT]
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010
Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from
the first glance, but it has changed things a lot. 'libvirt' uses it to
detect that it should follow new initialization way and this changes
things considerably. With this procedure followed, blockdev_init() is
not called anym
On Mon, Jul 11, 2022 at 11:32:35AM +0100, Peter Maydell wrote:
> On Fri, 8 Jul 2022 at 12:01, Daniel P. Berrangé wrote:
> > What alternative options do we have for addressing this scenario.
> >
> > I can think of
> >
> > - Auto-create array elements, if seeing an element set before length.
> >
>
On Mon, 11 Jul 2022 at 12:09, Daniel P. Berrangé wrote:
>
> On Mon, Jul 11, 2022 at 11:32:35AM +0100, Peter Maydell wrote:
> > I'm pretty sure that nothing needs sparse array elements like
> > that. The major reason for the len-PROP field is an implementation
> > one: because there is currently no
On Wed, 22 Jun 2022 at 17:06, Daniel P. Berrangé wrote:
>
> On Wed, Jun 22, 2022 at 03:43:54PM +0100, Alex Bennée wrote:
> >
> > Peter Maydell writes:
> >
> > > On Wed, 22 Jun 2022 at 13:33, Alex Bennée wrote:
> > >>
> > >> There have been requests from other projects such LKFT to have
> > >> "o
On 08/07/2022 05:57, Kito Cheng wrote:
Add new option for -d vu to dump the content of vector unit, many target
has vector register, but there is no easy way to dump the content, we
use this on downstream for a while to help debug, and I feel that's
really useful, so I think it would be great to
On Mon, 11 Jul 2022, Mark Cave-Ayland wrote:
On 06/07/2022 08:45, Cédric Le Goater wrote:
I gave KVM a try on a :
cpu : PPC970MP, altivec supported
clock : 2000.00MHz
revision : 1.0 (pvr 0044 0100)
processor : 1
cpu : PPC970MP, altivec support
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
Just as done with job.h, create _locked() functions in blockjob.h
These functions will be later useful when caller has already taken
the lock. All blockjob _locked functions call job _locked functions.
Note: at this stage, job_{lock/unlock} and
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
Both blockdev.c and job-qmp.c have TOC/TOU conditions, because
they first search for the job and then perform an action on it.
Therefore, we need to do the search + action under the same
job mutex critical section.
Note: at this stage, job_{lock
Am 11/07/2022 um 14:04 schrieb Vladimir Sementsov-Ogievskiy:
> On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
>> Just as done with job.h, create _locked() functions in blockjob.h
>>
>> These functions will be later useful when caller has already taken
>> the lock. All blockjob _locked functi
On Thu, 7 Jul 2022, at 17:50, Joel Stanley wrote:
> On Thu, 7 Jul 2022 at 07:17, Peter Delevoryas wrote:
>>
>> It seems that aspeed_gpio_update is allowing the value for input pins to be
>> modified through register writes and QOM property modification.
>>
>> The QOM property modification is fi
Set current_req to NULL to prevent reusing a free'd buffer in case of repeated
SCSI cancel requests. Thanks to Thomas Huth for suggesting the first version of
the patch and Alexander Bulekov for providing a reproducer.
Fixes: CVE-2022-0216
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/97
在 2022/7/11 下午2:41, Alistair Francis 写道:
On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li wrote:
- line over 80 characters will trigger warning when running checkpatch
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 362
On Fri, 1 Jul 2022 14:22:57 +0100
Jonathan Cameron via wrote:
> Three more or less less unrelated fixes for recently added CXL code.
>
> Jonathan Cameron (3):
> hw/machine: Clear out left over CXL related pointer from move of state
> handling to machines.
> hw/i386/pc: Always place CXL M
在 2022/7/11 下午2:46, Alistair Francis 写道:
On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li wrote:
- It seems that there is no explicitly description about whether
the Hypervisor CSRs requires S extension
- Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32
Signed-o
On Tue, 5 Jul 2022 at 16:01, Cédric Le Goater wrote:
>
> Hello,
>
> This replaces the IRQ array 'irq_inputs' with GPIO lines and removes
> 'irq_inputs' when all CPUs have been converted.
>
> Thanks,
>
> C.
>
> Cédric Le Goater (5):
> ppc64: Allocate IRQ lines with qdev_init_gpio_in()
> ppc/40x
On Thu, 7 Jul 2022 16:18:43 +0100
Joao Martins wrote:
> On 7/7/22 14:00, Igor Mammedov wrote:
> > On Fri, 1 Jul 2022 17:10:10 +0100
> > Joao Martins wrote:
> >
> >> Factor out the calculation of the base address of the MR. It will be
> >> used later on for the cxl range end counterpart calcu
On Thu, 7 Jul 2022 at 16:11, Alex Bennée wrote:
>
> How to control the booting of QEMU is often a source of confusion for
> users. Bring the options that control this together in the manual
> pages and add some verbiage to describe when each option is
> appropriate. This attempts to codify some of
On Fri, 8 Jul 2022 at 16:19, Richard Henderson
wrote:
>
> Changes for v6:
> * Some sub-word big-endian addressing fixups (pmm).
> * Logic errors for BFMOPA/FMOPA (pmm).
> * Fix for PR_SME_SET_VL hflags rebuild.
>
Applied to target-arm.next, thanks.
-- PMM
On Fri, 1 Jul 2022 17:10:13 +0100
Joao Martins wrote:
> It is assumed that the whole GPA space is available to be DMA
> addressable, within a given address space limit, except for a
> tiny region before the 4G. Since Linux v5.4, VFIO validates
> whether the selected GPA is indeed valid i.e. not
On Thu, 7 Jul 2022 16:21:07 +0100
Joao Martins wrote:
> On 7/7/22 14:05, Igor Mammedov wrote:
> > On Fri, 1 Jul 2022 17:10:11 +0100
> > Joao Martins wrote:
> >
> >> This in preparation to allow pc_pci_hole64_start() to be called early
> >> in pc_memory_init(), handle CXL memory region end wh
Hi, I'd like to connect to an encrypted QCOW2 file by
nbd_connect_systemd_socket_activation(), but I got ret=-1 with EINTR.
The arg parameter I used is
qemu-nbd --object secret,id=sec0,data=abc123 --image-opts
driver=qcow2,encrypt.format=luks,encrypt.key-secret=sec0,file.filename=/tmp/empty.qcow2
On Fri, 1 Jul 2022 17:10:14 +0100
Joao Martins wrote:
> The added enforcing is only relevant in the case of AMD where the
> range right before the 1TB is restricted and cannot be DMA mapped
> by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
> or possibly other kinds of IOMMU ev
Hello,
I am Vaidehi and I am currently trying to run a code on QEMU emulator using
eclipse IDE. However, I came across some documentation regarding the
deprecation of qemu-system-gnuarmeclipse and I need to know if there is v7.0.0
available for qemu-syetem-gnuarmeclipse.
Please let me know the
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
Add missing job synchronization in the unit tests, with
explicit locks.
We are deliberately using _locked functions wrapped by a guard
instead of a normal call because the normal call will be removed
in future, as the only usage is limited to th
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
Once job lock is used and aiocontext is removed, mirror has
to perform job operations under the same critical section,
using the helpers prepared in previous commit.
Note: at this stage, job_{lock/unlock} and job lock guard macros
are*nop*.
Sig
* Cornelia Huck (coh...@redhat.com) wrote:
> This series makes it possible to enable MTE for kvm guests, if the kernel
> supports it. Again, tested on the simulator via patiently waiting for the
> arm64/mte kselftests to finish successfully.
>
> For tcg, turning on mte on the machine level (to get
On Fri, 8 Jul 2022, at 04:34, Peter Delevoryas wrote:
> On Thu, Jul 07, 2022 at 10:53:57AM -0700, Peter Delevoryas wrote:
>> On Thu, Jul 07, 2022 at 10:56:02AM +0200, Cédric Le Goater wrote:
>> > On 7/7/22 09:17, Peter Delevoryas wrote:
>> > > It seems that aspeed_gpio_update is allowing the val
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
Now that the API offers also _locked() functions, take advantage
of it and give also the caller control to take the lock and call
_locked functions.
This makes sense especially when we have for loops, because it
makes no sense to have:
for(job
On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote:
We are always using the given bs AioContext, so there is no need
to take the job ones (which is identical anyways).
This also reduces the point we need to check when protecting
job.aio_context field.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: E
On Mon, 11 Jul 2022 at 14:24, Dr. David Alan Gilbert
wrote:
> But, ignoring postcopy for a minute, with KVM how do different types of
> backing memory work - e.g. if I back a region of guest memory with
> /dev/shm/something or a hugepage equivalent, where does the MTE memory
> come from, and how d
This patch series implements the 4 instructions added in Power ISA
3.1B:
- hashchk
- hashst
- hashchkp
- hashstp
What do you think about the choice to implement the hash algorithm
from the ground up, following the SIMON-like algorithm presented in
Power ISA? IIUC, this algorithm is not the same a
Implementation for instructions hashst and hashchk, which were added
in Power ISA 3.1B.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo
---
linux-headers/asm-powerpc/kvm.h| 2 +
target/ppc/
Implementation for instructions hashstp and hashchkp, the privileged
versions of hashst and hashchk, which were added in Power ISA 3.1B.
Signed-off-by: Víctor Colombo
---
linux-headers/asm-powerpc/kvm.h| 1 +
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c
* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> * Cornelia Huck (coh...@redhat.com) wrote:
> > This series makes it possible to enable MTE for kvm guests, if the kernel
> > supports it. Again, tested on the simulator via patiently waiting for the
> > arm64/mte kselftests to finish successfu
From: Richard Henderson
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0, th
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 4
target/arm/sme_helper.c| 25 +
ging (2022-07-08
06:17:11 +0530)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220711
for you to fetch changes up to f9982ceaf26df27d15547a3a7990a95019e9e3a8:
linux-user/aarch64: Add SME related hwcap entries (2022-
From: Richard Henderson
Mark ADR as a non-streaming instruction, which should trap
if full a64 support is not enabled in streaming mode.
Removing entries from sme-fa64.decode is an easy way to see
what remains to be done.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
Mark these as non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
-
From: Richard Henderson
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Dump SVCR, plus use the correct access check for Streaming Mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 17 -
1 fil
From: Richard Henderson
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-22-richard.hender...@linaro.org
Signed-off-by: Peter Maydel
From: Richard Henderson
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
The pseudocode for CheckSVEEnabled gains a check for Streaming
SVE mode, and for SME present but SVE absent.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
t
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-26-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
Reviewed-by: Peter Maydell
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c| 56 +++
From: Richard Henderson
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-34-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
linux-user/aarch64/target_cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-u
From: Richard Henderson
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-20-richard.hender...@linaro.or
From: Richard Henderson
These functions will be used to verify that the cpu
is in the correct state for a given instruction.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/ar
From: Richard Henderson
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220708151540.18136-29-richard.hender...@linaro.org
Signed-off-by: Peter Mayd
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