Re: [PATCH V8 12/39] memory: flat section iterator

On 6/15/2022 10:51 PM, Steve Sistare wrote: > Add an iterator over the sections of a flattened address space. > > Signed-off-by: Steve Sistare > Reviewed-by: Marc-André Lureau > --- > include/exec/memory.h | 31 +++ > softmmu/memory.c | 20 +++

Re: [PATCH V8 20/39] cpr: restart mode

On 6/15/2022 10:52 PM, Steve Sistare wrote: > Provide the cpr-save restart mode, which preserves the guest VM across a > restart of the qemu process. After cpr-save, the caller passes qemu > command-line arguments to cpr-exec, which directly exec's the new qemu > binary. The arguments must inc

Re: [PATCH V8 36/39] chardev: cpr for sockets

On 6/15/2022 10:52 PM, Steve Sistare wrote: > Save accepted socket fds before cpr-save, and look for them after cpr-load. > Block cpr-exec if a socket enables the TLS or websocket option. Allow a > monitor socket by closing it on exec. > > Signed-off-by: Mark Kanda > Signed-off-by: Steve Sist

[PATCH 06/62] target/arm: Use PageEntryExtra for BTI

Add a bit to ARMCacheAttrs to hold the guarded bit between get_phys_addr_lpae and arm_cpu_tlb_fill, then put the bit into PageEntryExtra. In is_guarded_page, use probe_access_extra instead of just guessing that the tlb entry is still present. Also handles the FIXME about executing from device mem

[PATCH 00/62] target/arm: Implement FEAT_HAFDBS

This is a major reorg to arm page table walking. While the result here is "merely" Hardware-assited Access Flag and Dirty Bit Setting (HAFDBS), the ultimate goal is the Realm Management Extension (RME). RME "recommends" that HAFDBS be implemented (I_CSLWZ). For HAFDBS, being able to find a host p

[PATCH 01/62] accel/tcg: Introduce PageEntryExtra

Add an optional structure, controlled by TARGET_PAGE_ENTRY_EXTRA, that allows arbitrary extra data to be saved in the TLB for a given page. Set it with tlb_set_page_with_extra() and fetch it with probe_access_extra(). Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 5 +++ includ

[PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page

Fixes a bug in that we were not honoring MTE from user-only SVE. Copy the user-only MTE logic from allocation_tag_mem into sve_probe_page. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/sve_helper.c b/target/arm/sve_

[PATCH 02/62] target/arm: Enable PageEntryExtra

Copy attrs, sharability, and the NS bit into the TLB. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 8 target/arm/internals.h | 5 + target/arm/tlb_helper.c | 14 -- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-param.

[PATCH 05/62] target/arm: Use PageEntryExtra for MTE

Tagged pages are indicated by the page attributes, so we don't need to use a separate bit in MemTxAttrs. Further, we store the PA, so we don't need to recover it by walking the tree of memory regions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/sve_lds

[PATCH 08/62] target/arm: Create GetPhysAddrResult

Combine 5 output pointer argument from get_phys_addr into a single struct. Adjust all callers. Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 - target/arm/helper.c | 27 - target/arm/m_helper.c | 52 + target/arm/ptw.c| 125 ++

[PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 490a57ec5a..f2e429574d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1347,7 +1347,7 @@ do_fault

[PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs

We have now moved all uses to PageEntryExtra. Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 -- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/incl

[PATCH 03/62] target/arm: Fix MTE check in sve_ldnfff1_r

The comment was correct, but the test was not: disable mte if tagged is *not* set. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1654c0bbf9..db15d03ded 10064

[PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup

This can be made redundant with result->page_size, by moving the basic set of page_size from get_phys_addr_pmsav8. We still need to overwrite page_size when v8m_security_lookup signals a subpage. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 3

[PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 25 +++-- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d70c9120fc..490a57ec5a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -410,9 +410,7 @@ static in

[PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr

The starting security state comes with the translation regime, not the current state of arm_is_secure_below_el3(). More use of the local variable, ipa_secure, which does not need to be written back to result->attrs.secure -- we compute that value later, after the S2 walk is complete. Signed-off-b

[PATCH 23/62] target/arm: Add is_secure parameter to pmsav7_use_background_region

Remove the use of regime_is_secure from pmsav7_use_background_region. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f7892a0c48..23cfccce6c 100644 --- a/target/arm/ptw.

[PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup

Remove the use of regime_is_secure from pmsav8_mpu_lookup. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 2 +- target/arm/ptw.c | 7 +++ 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/i

[PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4b69ecb1b9..ef28258d51 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1963,8 +1963,7 @@ void

[PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 69 ++-- 1 file changed, 26 insertions(+), 43 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b78658161f..5e79c9be98 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16

[PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5

Remove the use of regime_is_secure from get_phys_addr_v5. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1a0e708d11..1bef9c6c60 100644 --- a/target/arm/ptw.c +++ b/tar

[PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup

Remove the use of regime_is_secure from v8m_security_lookup. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/m_helper.c | 9 ++--- target/arm/ptw.c | 9 + 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/ta

[PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes

For a-profile, which does not bank system registers, it takes quite a lot of code to switch between security states. In the process, registers such as TCR_EL{1,2} must be swapped, which in itself requires the flushing of softmmu tlbs. Therefore it doesn't buy us anything to separate tlbs by secur

[PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 30 ++ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5e79c9be98..d70c9120fc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -532,8 +532,7 @@ do_f

[PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6

Remove the use of regime_is_secure from get_phys_addr_v6. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1bef9c6c60..d424dec729 100644 --- a/target/arm/ptw.c +++ b/tar

[PATCH 24/62] target/arm: Add is_secure parameter to get_phys_addr_lpae

Remove the use of regime_is_secure from get_phys_addr_lpae. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 23cfccce6c..b883826643 100644 --- a/target/arm/pt

[PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M

The effect of TGE does not only apply to non-secure state, now that Secure EL2 exists. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b80716e38..f76a8e931a 100644 --- a/targe

[PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 36 +--- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f2e429574d..4b69ecb1b9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1509,17 +1509,

[PATCH 22/62] target/arm: Add secure parameter to get_phys_addr_pmsav8

Remove the use of regime_is_secure from get_phys_addr_pmsav8. Since we already had a local variable named secure, use that. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d42

[PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5

Remove the use of regime_is_secure from get_phys_addr_pmsav5. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8313a2d74a..340f73997a 100644 --- a/target/arm/ptw.c +++ b/target

[PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate

For page walking, we may require HCR for a security state that is not "current". Signed-off-by: Richard Henderson --- target/arm/cpu.h| 20 +--- target/arm/helper.c | 11 --- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/ar

[PATCH 25/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav7

Remove the use of regime_is_secure from get_phys_addr_pmsav7 Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b883826643..33fa8f094b 100644 --- a/target/arm/ptw.c +++ b/target/

[PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup

Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 +-- target/arm/m_helper.c | 16 +++- target/arm/ptw.c | 20 +--- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7d08

[PATCH 28/62] target/arm: Split out get_phys_addr_with_secure

Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++ target/arm/ptw.c | 21 +++-- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/arm/intern

[PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb

This value is unused. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 12b6c2c98b..93c533e60d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2168,8 +2168,7 @@ static

[PATCH 26/62] target/arm: Add is_secure parameter to regime_translation_disabled

Remove the use of regime_is_secure from regime_translation_disabled. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Signed-off-by: Richard Henderson --- target/arm/pt

[PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE

Remove the use of regime_is_secure from arm_tr_init_disas_context. Instead, provide the value of v8m_secure directly from tb_flags. Rather than use regime_is_secure, use the env->v7m.secure directly, as per arm_mmu_idx_el. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ targe

[PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn

Remove the use of regime_is_secure from v7m_read_half_insn. As it happens, both callers pass true, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Signed-off-by: Richard Henderson --- target/arm/m_helper.c | 9 - 1 file changed, 4 insertions(+), 5 deletio

[PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write

Use get_phys_addr_with_secure directly. This is the one place where the value of is_secure may not equal arm_is_secure(env). Signed-off-by: Richard Henderson --- target/arm/helper.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/ta

[PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr

This is the last use of regime_is_secure; remove it entirely before changing the layout of ARMMMUIdx. Signed-off-by: Richard Henderson --- target/arm/internals.h | 42 target/arm/ptw.c | 44 -- 2 files changed

[PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS

The MMFR1 field may indicate support for hardware update of access flag alone, or access flag and dirty bit. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5e3084ec9..6484abcf1f 1006

[PATCH 34/62] target/arm: Reorg regime_translation_disabled

Use a switch on mmu_idx for the a-profile indexes, instead of three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 32 +--- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/p

[PATCH 38/62] target/arm: Fix S2 disabled check in S1_ptw_translate

Pass the correct stage2 mmu_idx to regime_translation_disabled, which we computed afterward. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 12288ac365..12b6c2c98b 100644 ---

[PATCH 47/62] target/arm: Hoist check for disabled stage2 translation.

If stage2 translation is disabled, E1&0 translation is just a single stage. Use the complete single stage path rather than breaking out of the middle of the two stage path. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) di

[PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate

Rename the argument to is_secure_ptr, and introduce a local variable is_secure with the value. We only write back to the pointer toward the end of the function. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-

[PATCH 60/62] target/arm: Don't shift attrs in get_phys_addr_lpae

Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Signed-off-by: Richard Henderson --- target/ar

[PATCH 40/62] target/arm: Pass HCR to attribute subroutines.

These subroutines did not need ENV for anything except retrieving the effective value of HCR anyway. We have computed the effective value of HCR in the callers, and this will be especially important for interpreting HCR in a non-current security state. Signed-off-by: Richard Henderson --- targe

[PATCH 48/62] target/arm: Split out get_phys_addr_twostage

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 182 +-- 1 file changed, 96 insertions(+), 86 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 84d72ac249..993f015904 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -24

Re: [PATCH V8 27/39] vfio-pci: cpr part 1 (fd and dma)

On 6/15/2022 10:52 PM, Steve Sistare wrote: > Enable vfio-pci devices to be saved and restored across an exec restart > of qemu. > > At vfio creation time, save the value of vfio container, group, and device > descriptors in cpr state. > > In the container pre_save handler, suspend the use of

[PATCH 43/62] target/arm: Reorg get_phys_addr_disabled

Use a switch. Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 115 +++ 1 file ch

[PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1

This has been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a760ab86c5..43a82c3c7f 100644 --

[PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation

If stage2 is disabled, we do not need to adjust mmu_idx. Below, we'll use get_phys_addr_lpae and not recurse. Adjust regime_is_user so that it can be used for E10_0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/

[PATCH 54/62] target/arm: Split out S1TranslateResult type

Consolidate the results of S1_ptw_translate in one struct. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 60 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6eb61849d3..32937ec7db

[PATCH 42/62] target/arm: Split out get_phys_addr_disabled

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 138 +-- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 43a82c3c7f..0f4b9b0166 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22

[PATCH v21 05/13] linux-user: Add LoongArch cpu_loop support

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-6-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- linux-user/loongarch64/target_cpu.h | 34 ++ linux-user/loongarch64/cpu_loop.c | 96 +++

[PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate

Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_secure and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Pass ptw_idx through get_phys_addr_{v5,v6,lpae} and arm_{ldl,ldq}_ptw. Signed-off

[PATCH v21 10/13] target/loongarch: remove unused include hw/loader.h

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-11-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/loongarch/cpu.c

[PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS}

Not yet used, but add mmu indexes for 1-1 mapping to physical addresses. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 4 target/arm/ptw.c | 9 + 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-param.

[PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters

Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c| 8 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1bbe4d950e..f2a421972e 100644 --- a/target/arm/internals.h +++ b/target/arm/

[PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult

Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 32937ec7db..b5105a2e92 100644 --- a/target/arm/ptw.c +++

[PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw

Separate S1 translation from the actual lookup. Will enable lpae hardware updates. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 83 +--- 1 file changed, 44 insertions(+), 39 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c inde

[PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx

We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb. Flush the tlb when invalidating stage 1+2 translations. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 20 +++- target/arm/helper.c| 4 +++- 3 files changed, 15

Re: [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state

On 7/1/22 15:41, Peter Maydell wrote: On Tue, 28 Jun 2022 at 05:25, Richard Henderson wrote: Dump SVCR, plus use the correct access check for Streaming Mode. Signed-off-by: Richard Henderson --- Reviewed-by: Peter Maydell Dumping the actual ZA storage seems like it would be more annoying

[PATCH 46/62] target/arm: Use softmmu tlbs for page table walking

So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_extra to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* f

[PATCH 61/62] target/arm: Consider GP an attribute in get_phys_addr_lpae

Both GP and DBM are in the upper attribute block. Extend the computation of attrs to include them, then simplify the setting of guarded. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/p

Re: [PATCH 5/5] target/arm: Correctly implement Feat_DoubleLock

On Sat, 2 Jul 2022 at 15:19, Richard Henderson wrote: > > On 7/1/22 01:11, Peter Maydell wrote: > > +static inline bool isar_feature_any_doublelock(const ARMISARegisters *id) > > +{ > > +/* > > + * We can't just OR together the aa32 and aa64 checks, because > > + * if there is no AArch

[PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines

The return type of the functions is already bool, but in a few instances we used an integer type with the return statement. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index

[PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate

This fault type is to be used with FEAT_HAFDBS when the guest enables hw updates, but places the tables in memory where atomic updates are unsupported. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 1 file changed, 4 insertions(+) diff --git a/target/arm/internals.h b/tar

[PATCH v21 02/13] linux-user: Add LoongArch signal support

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Message-Id: <20220624031049.1716097-3-gaos...@loongson.cn> [rth: Rework extctx frame allocation and locking; Properly read/write fcc from signal frame.] Signed-off-by: Richard Henderson --- linux-user/loongarch64/target

[PATCH v21 06/13] scripts: add loongarch64 binfmt config

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-7-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- scripts/qemu-binfmt-conf.sh | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --gi

[PATCH v21 03/13] linux-user: Add LoongArch elf support

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220624031049.1716097-4-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- linux-user/loongarch64/target_elf.h | 12 linux-user/el

[PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae

The unconditional loop was used both to iterate over levels and to control parsing of attributes. Use an explicit goto in both cases. While this appears less clean for iterating over levels, we will need to jump back into the middle of this loop for atomic updates, which is even uglier. Signed-o

[PATCH v21 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception

From: Song Gao Raise EXCCODE_BCE instead of EXCCODE_ADEM for helper_asrtle_d/asrtgt_d. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-10-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.c

[PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae

Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for reporting a translation fault. For other faults, store into fi directly. Signed-off-by: Richard Henderson --- target/a

[PATCH v21 04/13] linux-user: Add LoongArch syscall support

From: Song Gao Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220624031049.1716097-5-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- linux-user/loongarch64/syscall_nr.h | 312 ++

[PATCH v21 12/13] default-configs: Add loongarch linux-user support

From: Song Gao This patch adds loongarch64 linux-user default configs file. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Reviewed-by: WANG Xuerui Message-Id: <20220624031049.1716097-13-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- configs/

[PATCH 62/62] target/arm: Implement FEAT_HAFDBS

Perform the atomic update for hardware management of the access flag and the dirty bit. A limitation of the implementation so far is that the page table must itself be writable. This is allowed because it is CONSTRAINED UNPREDICTABLE whether any atomic update happens at all. Any implementation i

[PATCH v21 08/13] target/loongarch: Fix missing update CSR_BADV

From: Song Gao loongarch_cpu_do_interrupt() should update CSR_BADV for some EXCCODE. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-9-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.c | 1

[PATCH v21 13/13] target/loongarch: Update README

From: Song Gao Add linux-user emulation introduction Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-14-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/README | 39

[PATCH v21 00/13] Add LoongArch linux-user emulation support

Hi. This is Song Gao's v20 [1], with patch 2 extensively rewritten so that it handles lock_user properly. It compiles, but I need to update the docker image we produced last year so that I can properly test this. In the meantime, Song, can you please test this? r~ [1] https://lore.kernel.org

Re: [PATCH 5/5] target/arm: Correctly implement Feat_DoubleLock

On 7/3/22 14:27, Peter Maydell wrote: On Sat, 2 Jul 2022 at 15:19, Richard Henderson wrote: On 7/1/22 01:11, Peter Maydell wrote: +static inline bool isar_feature_any_doublelock(const ARMISARegisters *id) +{ +/* + * We can't just OR together the aa32 and aa64 checks, because + * i

[PATCH v21 01/13] linux-user: Add LoongArch generic header files

From: Song Gao This includes: - sockbits.h - target_errno_defs.h - target_fcntl.h - termbits.h - target_resource.h - target_structs.h Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: WANG Xuerui Message-Id:

[PATCH v21 07/13] target/loongarch: remove badaddr from CPULoongArch

From: Song Gao We can use CSR_BADV to replace badaddr. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-8-gaos...@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 2 -- target/loongarch/gdbs

[PATCH v21 11/13] target/loongarch: Adjust functions and structure to support user-mode

From: Song Gao Some functions and member of the structure are different with softmmu-mode So we need adjust them to support user-mode. Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220624031049.1716097-12-gaos...@loongson.cn> Signed-off-by:

[PATCH] target/ppc: Fix MPC8555 and MPC8560 core type to e500v1

Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2. But both MPC8555 and MPC8560 have just e500v1 cores, there are no features of e500v2 cores. It can be verified by reading NXP documentations: https://www.nx

[PATCH v2 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c

These will be shared with the virt platform. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/boot.c | 117 + hw/openrisc/meson.build| 1 + hw/openrisc/openrisc_sim.c | 106 ++--- include/h

[PATCH v2 02/11] target/openrisc: Fix memory reading in debugger

In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and instruction TLB reads were combined. This, broke debugger reads where we first tried to map using the data tlb then fall back to the instruction tlb. This patch replicates this logic by first requesting a PAGE_READ protection map

[PATCH v2 00/11] OpenRISC Virtual Machine

Hello, This is the OpenRISC Virtual Machine plaform which we are now using for OpenRISC CI such as the wireguard testing that Jason has been working on. The first few patches help get OpenRISC QEMU ready for the virtual machine. There is one bug fix for GDB debugging there too. Next we have the

[PATCH v2 03/11] goldfish_rtc: Add endianness property

Add an endianness property to allow configuring the RTC as either native, little or big endian. Cc: Laurent Vivier Signed-off-by: Stafford Horne --- hw/rtc/goldfish_rtc.c | 46 --- include/hw/rtc/goldfish_rtc.h | 2 ++ 2 files changed, 39 insertions(+),

[PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt

This is mostly borrowed from xtensa and riscv as examples. The create_pcie_irq_map swizzle function is almost and exact copy but here we use a single cell interrupt, possibly we can make this generic. Signed-off-by: Stafford Horne --- hw/openrisc/Kconfig | 3 + hw/openrisc/virt.c | 160 +

[PATCH v2 06/11] hw/openrisc: Initialize timer time at startup

The last_clk time was initialized at zero, this means when we calculate the first delta we will calculate 0 vs current time which could cause unnecessary hops. Initialize last_clk to the qemu clock on initialization. Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 1 + 1 file changed

[PATCH v2 07/11] target/openrisc: Add interrupted CPU to log

When we are tracing it's helpful to know which CPU's are getting interrupted, att that detail to the log line. Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interr

[PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine

This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This platform allows for a convenient CI platform for toolchain, software ports and the OpenRISC linux kernel port. Much of this has been sourced from the m68k and riscv virt platforms. The platform provides: - OpenRISC SMP with

[PATCH v2 08/11] target/openrisc: Enable MTTCG

This patch enables multithread TCG for OpenRISC. Since the or1k shared syncrhonized timer can be updated from each vCPU via helpers we use a mutex to synchronize updates. Signed-off-by: Stafford Horne --- configs/targets/or1k-softmmu.mak | 1 + hw/openrisc/cputimer.c | 17 +++

[PATCH v2 09/11] target/openrisc: Interrupt handling fixes

When running SMP systems we sometimes were seeing lockups where IPI interrupts were being raised by never handled. This looks to be caused by 2 issues in the openrisc interrupt handling logic. 1. After clearing an interrupt the openrisc_cpu_set_irq handler will always clear PICSR. This is n

[PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt

From: "Jason A. Donenfeld" If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is confirmed to successfully initialize the RNG on Linux 5.19-rc2. Cc: Stafford Horne Signed-off-by: Jason

[PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation

Signed-off-by: Stafford Horne --- docs/system/openrisc/cpu-features.rst | 15 ++ docs/system/openrisc/emulation.rst| 17 +++ docs/system/openrisc/or1k-sim.rst | 43 docs/system/openrisc/virt.rst | 50 +++ docs/system/target-openrisc.rst

Re: [RFC 4/8] Fix some direct calls from non-coroutine_fn to coroutine_fn

On Sat, Jul 2, 2022 at 3:13 PM Paolo Bonzini wrote: > These functions should be coroutine_fn (all coroutine entry points > should be). Thanks, I see now that you fixed this in [1]. Alberto [1] https://patchew.org/QEMU/20220509103019.215041-1-pbonz...@redhat.com/

Re: [PATCH 00/18] Make block-backend-io.h API more consistent

On Sat, Jul 2, 2022 at 3:12 PM Paolo Bonzini wrote: > Alberto, does this need a rebase? This applies cleanly on "[PATCH v5 00/10] Implement bdrv_{pread,pwrite,pwrite_sync,pwrite_zeroes}() using generated_co_wrapper" [1], which applies cleanly to master. Alberto [1] https://lore.kernel.org/qemu

Re: [PATCH v5 07/10] block: Implement bdrv_{pread, pwrite, pwrite_zeroes}() using generated_co_wrapper

On Thu, Jun 23, 2022 at 10:47 PM Eric Blake wrote: > I did not get through all of the callers (you are right, there ARE a > lot), but the ones I checked, particularly in block/qcow2-*.c, appear > to handle -EIO just fine. > > I did notice, however, that qcow2-bitmap.c:free_bitmap_clusters() > retu

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