[PATCH v5 1/4] target/riscv: Don't force update priv spec version to latest

The riscv_cpu_realize() sets priv spec version to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv

[PATCH v5 0/4] QEMU RISC-V nested virtualization fixes

This series does fixes and improvements to have nested virtualization on QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v5 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hyperviso

[PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 3 + target/riscv/cpu_helper.c | 231 +

[PATCH v5 4/4] target/riscv: Force disable extensions if priv spec version does not match

We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the

[PATCH v3 1/1] target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- t

[PATCH v3 0/1] target/riscv: Add Zihintpause support

This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode. Added trans_pause for TCG to mainly to break reservation and exit the TB. The change can also be found in: https://github.com/dlu42/qemu/tree/zihintpause_support_v

Re: [PATCH v3] target/riscv: Don't expose the CPU properties on names CPUs

On Wed, Jun 8, 2022 at 4:14 PM Alistair Francis wrote: > > From: Alistair Francis > > There are currently two types of RISC-V CPUs: > - Generic CPUs (base or any) that allow complete custimisation > - "Named" CPUs that match existing hardware > > Users can use the base CPUs to custimise the ext

bios bits acpica upgrade

Hi Josh : I have gone ahead and upgraded the acpica. Changes need to be reviewed and bits need to be tested more. However, here are the changes: In the acpica submodule: https://github.com/biosbits/acpica/pull/1 in the main top level bits repo: https://github.com/ani-sinha/bits/compare/master...

Re: [PATCH v2 2/2] hw: m25p80: add tests for write protect

On 09/06/2022 05.13, Iris Chen wrote: Signed-off-by: Iris Chen --- Include the tests in a separate patch. Using qtest_set_irq_in() as per review. tests/qtest/aspeed_smc-test.c | 60 +++ 1 file changed, 60 insertions(+) diff --git a/tests/qtest/aspeed_smc-test

Re: [PATCH] gitlab: compare CIRRUS_nn vars against 'null' not ""

On 08/06/2022 18.06, Daniel P. Berrangé wrote: The GitLab variable comparisons don't have shell like semantics where an unset variable compares equal to empty string. We need to explicitly test against 'null' to detect an unset variable. Signed-off-by: Daniel P. Berrangé --- .gitlab-ci.d/base

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