On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
>
> On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis wrote:
> >
> > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> > >
> > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > to program the next timer interrupt. This
Am 07/06/2022 um 17:41 schrieb Paolo Bonzini:
> On 6/7/22 15:20, Emanuele Giuseppe Esposito wrote:
>>
>>
>> Am 03/06/2022 um 18:00 schrieb Kevin Wolf:
>>> Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
Categorize the fields in struct Job to understand which ones
nee
On Tue, May 31, 2022 at 1:40 PM Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Qemu-devel > bounces+chen.zhang=intel@nongnu.org> On Behalf Of Haochen Tong
> > Sent: Saturday, May 28, 2022 3:07 AM
> > To: qemu-devel@nongnu.org
> > Cc: qemu-triv...@nongnu.org; Haochen Tong
>
On May 9 16:16, Lukasz Maniak wrote:
> Changes since v7:
> - Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
> - Added description to docs: Add documentation for SR-IOV and
> Virtualization Enhancements
> - Added Reviewed-by and Acked-by tags
> - Rebased on master
>
> Lukasz
> -Original Message-
> From: Qemu-devel bounces+chen.zhang=intel@nongnu.org> On Behalf Of Juan Quintela
> Sent: Tuesday, May 31, 2022 6:43 PM
> To: qemu-devel@nongnu.org
> Cc: Marcel Apfelbaum ; Philippe Mathieu-
> Daudé ; Yanan Wang ; Dr.
> David Alan Gilbert ; Juan Quintela
> ; Ed
> -Original Message-
> From: Qemu-devel bounces+chen.zhang=intel@nongnu.org> On Behalf Of Juan Quintela
> Sent: Tuesday, May 31, 2022 6:43 PM
> To: qemu-devel@nongnu.org
> Cc: Marcel Apfelbaum ; Philippe Mathieu-
> Daudé ; Yanan Wang ; Dr.
> David Alan Gilbert ; Juan Quintela
> ; Ed
On Tue, Jun 07, 2022 at 01:23:20PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The SRIOV series exposed an issued with how CC register writes are
> handled and how CSTS is set in response to that. Specifically, after
> applying the SRIOV series, the controller could end up in a state with
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Reorg m68k_semi_return_* to gdb_syscall_complete_cb.
Use the 32-bit version normally, and the 64-bit version
for HOSTED_LSEEK.
Signed-off-by: Richard Henderson
---
target/m68k/m68k-semi.c | 55 +
1 fil
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
While we had a call to do_m68k_semihosting in linux-user, it
wasn't actually reachable. We don't include DISAS_INSN(halt)
as an instruction unless system mode.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 5 -
targ
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
This separates guest file descriptors from host file descriptors,
and utilizes shared infrastructure for integration with gdbstub.
Signed-off-by: Richard Henderson
---
target/m68k/m68k-semi.c | 306 ++--
1
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes for v4:
* Split out of v2.
* Convert host errno to gdb errno, which for m68k is guest errno.
How do you test semihosting o
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Now the function can remove any child, so give it more common name.
Drop assertions and drop bs argument which becomes unused. Function
would be reused in a further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 22
On Thu, May 12 2022, Cornelia Huck wrote:
> This series enables MTE for kvm guests, if the kernel supports it.
> Lightly tested while running under the simulator (the arm64/mte/
> kselftests pass... if you wait patiently :)
>
> A new cpu property "mte" (defaulting to on if possible) is introduced
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
The only caller is bdrv_root_unref_child(), let's just do the logic
directly in it. It simplifies further convertion of
bdrv_root_unref_child() to transaction action.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 45 ++
On 11.05.22 11:34, Daniel P. Berrangé wrote:
> On Wed, May 11, 2022 at 11:31:23AM +0200, David Hildenbrand wrote:
Long story short, management application has no way of learning
TIDs of allocator threads so it can't make them run NUMA aware.
>>>
>>> This feels like the key issue. The prea
On 5/20/22 11:45, Joao Martins wrote:
> v4[5] -> v5:
> * Fixed the 32-bit build(s) (patch 1, Michael Tsirkin)
> * Fix wrong reference (patch 4) to TCG_PHYS_BITS in code comment and
> commit message;
>
> ---
>
> This series lets Qemu spawn i386 guests with >= 1010G with VFIO,
> particularly when r
On Wed, Jun 08, 2022 at 10:28:55AM +0200, Klaus Jensen wrote:
> On May 9 16:16, Lukasz Maniak wrote:
> > Changes since v7:
> > - Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
> > - Added description to docs: Add documentation for SR-IOV and
> > Virtualization Enhancements
>
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Drop this simple wrapper used only in one place. We have too many graph
modifying functions even without it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
Previously SEMIHOSTING was always selected due to requirements in the
helper files. Since the original fix there has been refactoring in the
mips code to split TCG and KVM code. The recent semihosting
refactoring triggers the inverse build problem for KVM only mips
builds. Instead of selecting it i
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Allow passing external Transaction pointer, stop creating extra
Transaction objects.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
Review
On 07.06.2022 20:06, Richard Henderson wrote:
On 6/7/22 01:59, Pavel Dovgalyuk wrote:
+# Branch on bit set or clear
+# BBIT0 110010 . .
+# BBIT032 110110 . .
+# BBIT1 111010 . .
+# BBIT132 10 . ...
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We are going to increase usage of collecting nodes in a list to then
update, and calling bdrv_topological_dfs() each time is not convenient,
and not correct as we are going to interleave graph modifying with
filling the node list.
So, let's
Recent changes to edk2 switched the x86_64 build from using TPM_ENABLE
to TPM2_ENABLE and TPM1_ENABLE to be similar to the ARM build. Adapt
the QEMU edk2 Makefile to build with TPM2_ENABLE. QEMU v7.0.0 had lost
the TPM 2 support in edk2 and this restores it.
Signed-off-by: Stefan Berger
---
roms
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We'll need them in further commits in blockdev.c for new transaction
block-graph modifying API.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c| 7 +++
include/block/block-global-state.h | 4
On Wed, Jun 08, 2022 at 02:37:28AM -0300, Leonardo Bras Soares Passos wrote:
> (1) is not an option, as the interface currently uses ret=1 to make
> sure MSG_ZEROCOPY is getting used,
> I added that so the user of qio_channel can switch off zero-copy if
> it's not getting used, and save some cpu.
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
To be used in further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 48
1 file changed, 48 insertions(+)
Looking at bdrv_child_try_set_aio_context(), it looks like
b
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> Allow the user to request statistics for a single provider of interest.
> Extracted from a patch by Mark Kanda.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Dr. David Alan Gilbert
> ---
> hmp-commands-info.hx | 7 ---
> monitor/hmp-cmds.c
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> Allow retrieving the statistics from a specific provider only.
> This can be used in the future by HMP commands such as "info
> sync-profile" or "info profile". The next patch also adds
> filter-by-provider capabilities to the HMP equivalent of
> quer
On Tue, 7 Jun 2022 15:37:02 -0700
Davidlohr Bueso wrote:
> On Wed, 01 Jun 2022, Jonathan Cameron wrote:
>
> >Paolo Bonzini requested this change to simplify the ongoing
> >effort to allow machine setup entirely via RPC.
> >
> >Includes shortening the command line form cxl-fixed-memory-window
> >
From: Eric Auger
Imported from https://github.com/luxis1999/iommufd/tree/iommufd-v5.17-rc6
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
---
linux-headers/linux/iommufd.h | 223 ++
linux-headers/linux/vfio.h| 84 +
2 files changed, 307 insert
Abstract the VFIOContainer to be a base object. It is supposed to be
embedded by legacy VFIO container and later on, into the new iommufd
based container.
The base container implements generic code such as code related to
memory_listener and address space management. The VFIOContainerOps
implement
From: Eric Auger
Update the script to import iommufd.h
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index 839a5ec614..a8
With the introduction of iommufd[1], the Linux kernel provides a generic
interface for userspace drivers to propagate their DMA mappings to kernel
for assigned devices. This series does the porting of the VFIO devices
onto the /dev/iommu uapi and let it coexist with the legacy implementation.
Other
From: Eric Auger
Let the vfio-platform device use vfio_attach_device() and
vfio_detach_device(), hence hiding the details of the used
IOMMU backend.
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
---
hw/vfio/platform.c | 42 ++
1 file changed, 2 insert
From: Eric Auger
Reset implementation depends on the container backend. Let's
introduce a VFIOContainer class function and register a generic
reset handler that will be able to call the right reset function
depending on the container type. Also, let's move the
registration/unregistration to a pla
From: Eric Auger
Let the vfio-ccw device use vfio_attach_device() and
vfio_detach_device(), hence hiding the details of the used
IOMMU backend.
Also now all the devices have been migrated to use the new
vfio_attach_device/vfio_detach_device API, let's turn the
legacy functions into static functi
From: Eric Auger
We want the VFIO devices to be able to use two different
IOMMU callbacks, the legacy VFIO one and the new iommufd one.
Introduce vfio_[attach/detach]_device which aim at hiding the
underlying IOMMU backend (IOCTLs, datatypes, ...).
Once vfio_attach_device completes, the device
From: Eric Auger
Let the vfio-ap device use vfio_attach_device() and
vfio_detach_device(), hence hiding the details of the used
IOMMU backend.
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
---
hw/vfio/ap.c | 62
1 file changed, 9 insertio
/dev/vfio/devices/vfioX may not exist. In that case it is still possible
to open /dev/char/$major:$minor instead. Add helper function to abstract
the cdev open.
Suggested-by: Jason Gunthorpe
Signed-off-by: Yi Liu
---
MAINTAINERS | 6 +
include/qemu/char_dev.h | 16
Add the iommufd backend. The IOMMUFD container class is implemented
based on the new /dev/iommu user API. This backend obviously depends
on CONFIG_IOMMUFD.
So far, the iommufd backend doesn't support live migration and
cache coherency yet due to missing support in the host kernel meaning
that only
Compared with legacy vfio container BE, one of the benefits provided by
iommufd is to reduce the redundant page pinning on kernel side through
the usage of IOAS_COPY_DMA. For iommufd containers within the same address
space, IOVA mappings can be copied from a source container to destination
contain
From: Eric Auger
Let's turn attach/detach_device as container callbacks. That way,
their implementation can be easily customized for a given backend.
For the time being, only the legacy container is supported.
Signed-off-by: Eric Auger
Signed-off-by: Yi Liu
---
hw/vfio/as.c
From: Eric Auger
Introduce an iommufd object which allows the interaction
with the host /dev/iommu device.
The /dev/iommu can have been already pre-opened outside of qemu,
in which case the fd can be passed directly along with the
iommufd object:
This allows the iommufd object to be shared accr
From: Eric Auger
Now we support two types of iommu backends, let's add the capability
to select one of them. This depends on whether an iommufd object has
been linked with the vfio-pci device:
if the user wants to use the legacy backend, it shall not
link the vfio-pci device with any iommufd obj
On Mon, Jun 06, 2022 at 05:10:38PM +0100, Alberto Faria wrote:
> Thanks for the feedback, and apologies for the delayed response.
>
> On Mon, May 30, 2022 at 1:49 PM Stefan Hajnoczi wrote:
> > If you find it's safe to change to -EINVAL then that's consistent with
> > how file I/O syscalls work an
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
v4: (Ben Widawsky review responses - thanks!)
- Expand list of matched types for 'skip' usages (
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> Allow retrieving only a subset of statistics. This can be useful
> for example in order to plot a subset of the statistics many times
> a second.
>
> KVM publishes ~40 statistics for each vCPU on x86; retrieving and
> serializing all of them would be
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> Allow the user to request only a specific subset of statistics.
> This can be useful when working on a feature or optimization that is
> known to affect that statistic.
>
> Extracted from a patch by Mark Kanda.
>
> Signed-off-by: Paolo Bonzini
I th
Changelog:
since v1:
* add tis 2.0 clarification to commit message (Ani Sinha)
* rebase on top of pci tree
* pick up acks
Series is excerpt form larger refactoring that does
the same for PCI devices, but it's too large at this
point, so I've split off a relatively self-contained
I
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/block/fdc-isa.c | 16 ++--
hw/i386/acpi-build.c | 1 -
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c
index fa20450747..fee1ca68a8 100644
--- a/hw/block/fdc-isa.c
+
There is already ISADeviceClass::build_aml() callback which
builds device specific AML blob for some ISA devices.
To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF
Interface that will provide a more generic callback which
will be used not only for ISA but other devices. It will
all
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/char/parallel.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index f735a6cd7f..1c9ca47820 100644
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -28,7 +2
basic q35 DSDT with an extra device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resourc
To allow incremental conversion from ISADeviceClass::build_aml
to AcpiDevAmlIf, add support for the later without removing
the former. Once conversion is complete, another commit will
drop ISADeviceClass::build_aml related code.
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd
replaces adhoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached
to its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_q35_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prologu
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/isa/isa.h | 1 -
hw/isa/isa-bus.c | 12 +---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 034d706ba1..5c5a3d43a7 100644
--- a/include/hw/isa/isa.h
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.applesmc | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.applesmc
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b4687d1cc8 100644
--- a/tests/qtest/bios-tables-test-allowe
smbus-ipmi AML description needs to specify a path to its parent
node in _CRS. The rest of IPMI inplementations (ISA based)
do not need path at all. Instead of passing through a full path
use relative path to point to smbus-ipmi's parent node, it will
let follow up patches to create IPMI device AML
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/input/pckbd.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 4efdf75620..45c40fe3f3 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -29,7 +29,7 @@
#i
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/char/serial-isa.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c
index 7a7ed239cd..141a6cb168 100644
--- a/hw/char/serial-isa.c
+++ b/hw/char/serial-isa.c
@
.. which will be used by follow up smbus-ipmi test-case
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.ipmismbus | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.ipmismbus
diff --git a/tests/
expected AML change:
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
- AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+ AddressingMode7Bit, "^",
0x00, Res
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d896840270..7d238218ca 100644
--- a/tests/qtest/bios-tables-test.c
+++ b
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
we can keep this bit if anyone can pro
expected new device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.pvpanic-isa| 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/q35/DSDT.pvpanic-isa
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bi
.. and clean up not longer needed conditionals in DSTD build
code. applesmc AML will be fetched and included when ISA bridge
will build its own AML code (incl. attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
Signed-o
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 31 +
1 file changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..d95f4b25c4 100644
--- a/tests/qtest/
.. and clean up not longer needed conditionals in DSTD build code
pvpanic-isa AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
Expected AML change:
ISA devices under separate _SB.PCI0.ISA scope are moved
directly under Device(ISA) node.
Example from PC machine, and q35 have similar changes:
{
Name (_ADR, 0x0001) // _ADR: Address
OperationRegion (P40C, PCI_Config, 0x60, 0x04)
-
wire AcpiDevAmlIf interface to build ich9-smb and its slave
devices AML. It will be used by followup patches to switch
from creating AML in ad-hoc way to a more systematic one
that will scan present devices and ask them to provide
their AML code like it's done with ISA devices.
This patch is a par
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 7d238218ca..56498bbcc8 100644
--- a/tests/qtest/bios-tables-test.c
+++ b
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
include/hw/acpi/ipmi.h | 9 ++--
hw/acpi/ipmi-stu
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6b496480d2..1204b6da05 100644
--- a/hw/i386/acpi-build.c
+++ b/hw
@@ -145,6 +145,37 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (PEVT)
+{
+Name (_HID, "QEMU0001") /
Signed-off-by: Igor Mammedov
Acked-by: Ani Sinha
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7b3bf9a207 100644
--- a/tests/qtest/
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/rtc/mc146818rtc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index f235c2ddbe..ef9765bb8f 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@
expected move of tmp-tis device description directly under
Device(ISA) node.
for tpm-tis 2.0:
@@ -145,6 +145,189 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
OperationRegion (PIRQ, PCI_
tpm-tis 2.0, is not a PCI device but ISA one, move it
under ISA scope to fix incorrect placement.
Fixes: 24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 3 +--
1 file changed,
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 1 -
1 f
replaces ad-hoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached to
its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_piix4_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prol
.. and clean up not longer needed conditionals in DSTD build code
tpm-tis AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.
ben.widaw...@intel.com will stop working on 2022-06-20, change it to my
personal email address.
Update .mailmap to handle previously authored commits.
Acked-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
---
v2:
Fix typo in commit message
change author to b...@bwidawsk.net from @intel.co
@@ -145,6 +145,23 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (SMC)
+{
+Name (_HID, EisaId ("APP000
The move from tests/tcg/configure.sh started enabling the container image
for xtensa-linux-user, which fails because the compiler does not have
the full set of headers. The cause is the "xtensa*-softmmu)" case
in tests/tcg/configure.sh which became just "xtensa*)" in the new
probe_target_compiler
Hi
On Wed, Jun 8, 2022 at 3:33 PM Stefan Berger wrote:
>
> Recent changes to edk2 switched the x86_64 build from using TPM_ENABLE
You can quote the relevant change: commit 4de8d61bcec ("OvmfPkg:
rework TPM configuration")
> to TPM2_ENABLE and TPM1_ENABLE to be similar to the ARM build. Adapt
>
On 6/7/22 19:44, Dr. David Alan Gilbert wrote:
+return NULL;
+}
+descriptors->kvm_stats_header = kvm_stats_header;
+descriptors->kvm_stats_desc = kvm_stats_desc;
+descriptors->ident = g_strdup(ident);
There's something that confuses me here; you check your set of
descri
On 07/06/2022 07:49, Paolo Bonzini wrote:
> Setting the MAKE variable to a GNU Make executable does not really have
> any effect: if a non-GNU Make is used, the QEMU Makefile will fail to
> parse. Just remove everything related to --make and $make as dead code.
>
> Signed-off-by: Paolo Bonzini
>
On 6/7/22 18:00, Stefan Berger wrote:
Hi!
The patches in this PR resolve several Coverity issues and mark a memory
region with TPM response data as dirty so that it does not get lost during
migration.
Stefan
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropria
On 6/7/22 20:35, Dr. David Alan Gilbert wrote:
+monitor_printf(mon, "%s", iec_binary_prefix(value->exponent));
OK that's better; but it's a shame the limits don't come from something
shared; iec_binary_prefix goes upto 60 and si_prefix goes way below -9
Reviewed-by: Dr. David Alan Gilbe
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 6/7/22 19:44, Dr. David Alan Gilbert wrote:
>
> > > +return NULL;
> > > +}
> > > +descriptors->kvm_stats_header = kvm_stats_header;
> > > +descriptors->kvm_stats_desc = kvm_stats_desc;
> > > +descriptors->ident = g_strdup(id
On 6/8/22 02:36, Laurent Vivier wrote:
Le 08/06/2022 à 00:26, Richard Henderson a écrit :
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes for v4:
* Split out of v2.
* Convert host errno to gdb errno, which for m68k is guest
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is needed to ensure that there is
Changes since v2: (reviews from Davidlohr and Ben - thanks!)
- Update qemu-options.hx to reflect that cxl-fmw is now a machine
property. (Davidlohr Bueso)
- Pick up David (patch 1) and Ben's RBs (all).
Changes since v1 (thanks to Paolo Bonzini)
* Update 'description' of cxl-fmw as suggested to m
Paolo Bonzini writes:
> The move from tests/tcg/configure.sh started enabling the container image
> for xtensa-linux-user, which fails because the compiler does not have
> the full set of headers. The cause is the "xtensa*-softmmu)" case
> in tests/tcg/configure.sh which became just "xtensa*)"
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
tests/data/acpi/q35/CEDT.cxl| Bin 184 -> 184 bytes
test
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
hw/i386/pc.c| 1 -
include/hw/boards.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
hw/acpi/cxl.c | 9 -
hw/i386/acpi-build.c | 4 ++--
include/hw/acpi/cxl.h | 5 +++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-
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