We already have some larger ifdef blocks for ARM and RISCV;
split out a boolean test for SYS_SYNCCACHE.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/semi
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall.
Do not modify guest registers until the syscall is complete,
which in the gdbstub case is asynchronous.
In the synchronous non-gdbstub case, use common_semi_set_ret
to set the result. Merge set_swi_errno into common_semi_cb.
Rel
Signed-off-by: Richard Henderson
---
accel/stubs/tcg-stub.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index ea4a0dd2fb..6ce8a34228 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -21,6 +21,13 @@ void tlb_set_dirt
Fixes a minor bug in which a 64-bit guest on a 32-bit host could
truncate the length. This would only ever cause a problem if
there were no bits set in the low 32, so that it truncates to 0.
Signed-off-by: Richard Henderson
---
semihosting/syscalls.c | 16
1 file changed, 16 in
Changes for v4:
* Standarize on host errno in callbacks. So, from gdbstub, convert
back to host errors, mapping GDB_EUNKNOWN to EINVAL.
* Add tcg stub for probe_access_flags, to match existing stubs.
* Misc tweaks per review.
Richard Henderson (53):
semihosting: Move exec/softmmu-semi
Rather that static (and not even inline) functions within a
header, move the functions to semihosting/uaccess.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/semihosting/softmmu-uaccess.h | 42 +++---
semihosting/uaccess.c | 51
We are not currently bounding the search to the 1024 bytes
that we allocated, possibly overrunning the buffer.
Use softmmu_strlen_user to find the length and allocate the
correct size from the beginning.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
semihosting/uaccess.c | 15
Split out the non-ARM specific portions of SYS_WRITE to a
reusable function. This handles all GuestFD. This removes
the last use of common_semi_syscall_len.
Note that gdb_do_syscall %x reads target_ulong, not int.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 6
Mirror the interface of the user-only function of the same name.
Use probe_access_flags for the common case of ram, and
cpu_memory_rw_debug for the uncommon case of mmio.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Use probe_access_flags (pmm)
---
include/semihosting/sof
There were 3 copies of these flags. Place them in the
file with gdb_do_syscall, with which they belong.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/gdbstub.h| 9 +
semihosting/arm-compat-semi.c | 7 ---
target/m68k/
We were reporting unconditional success for these functions;
pass on any failure from cpu_memory_rw_debug.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/semihosting/softmmu-uaccess.h | 91 ---
1 file changed, 39 insertions(+), 52 deletions(-)
d
Do not store 'err' into errno only to read it back immediately.
Use 'ret' for the return value, not 'reg0'.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/semi
We already have some larger ifdef blocks for ARM and RISCV;
split the function into multiple implementations per arch.
Reviewed-by: Peter Maydell
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 19 ---
1 file changed, 8 inserti
Split out the non-ARM specific portions of SYS_REMOVE to a
reusable function.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 3 +++
semihosting/arm-compat-semi.c | 13 +--
semihosting/syscalls.c | 40 ++
3 files changed, 44
Load the entire 64-bit size value. While we're at it,
use offsetof instead of an integer constant.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/semihosting/arm-co
This header is not private to the top-level semihosting directory,
so place it in the public include directory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
{semihosting => include/semihosting}/common-semi.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename {semiho
We already have some larger ifdef blocks for ARM and RISCV;
split out common_semi_stack_bottom per target.
Reviewed-by: Peter Maydell
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 44 +--
1 file changed, 21 in
Provide the callback with consistent state -- always use
host error numbers. The individual callback can then
decide if the errno requires conversion for the guest.
Signed-off-by: Richard Henderson
---
gdbstub.c | 31 +++
1 file changed, 31 insertions(+)
diff --git
Split out the non-ARM specific portions of SYS_RENAME to a
reusable function.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 4 +++
semihosting/arm-compat-semi.c | 21 +
semihosting/syscalls.c | 57 ++
3 files changed,
Change 'ret' to uint64_t. This resolves a FIXME in the
m68k and nios2 semihosting that we've lost data.
Change 'err' to int. There is nothing target-specific
about the width of the errno value.
Signed-off-by: Richard Henderson
---
include/exec/gdbstub.h| 3 +--
gdbstub.c
We have two copies of these structures, and require them
in semihosting/ going forward.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/gdbstub.h| 25 +
target/m68k/m68k-semi.c | 32 +---
Split out the non-ARM specific portions of SYS_OPEN to a
reusable function. This handles gdb and host file i/o.
Add helpers to validate the length of the filename string.
Prepare for usage by other semihosting by allowing the
filename length parameter to be 0, and calling strlen.
Signed-off-by:
We've already loaded cs->env_ptr into a local variable; use it.
Since env is unconditionally used, we don't need a dummy use.
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/semihosting/arm-compat-semi.
Define constants for the errno values defined by the
gdb remote fileio protocol.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/gdbstub.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
ind
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 4c8932ad54..dea5b2de8d 100644
--- a/semihosting/arm-compat-semi.c
+++ b/
Split out the non-ARM specific portions of SYS_CLOSE to a
reusable function. This handles all GuestFD.
Note that gdb_do_syscall %x reads target_ulong, not int.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 3 +++
semihosting/arm-compat-semi.c | 41 +---
Move the ARM and RISCV specific helpers into
their own header file.
Signed-off-by: Richard Henderson
---
target/arm/common-semi-target.h | 62
target/riscv/common-semi-target.h | 50
semihosting/arm-compat-semi.c | 94 +--
3
Split out the non-ARM specific portions of SYS_ISTTY to a
reusable function. This handles all GuestFD.
Add a common_semi_istty_cb helper to translate the Posix
error return, 0+ENOTTY, to the Arm semihosting not-a-file
success result.
Signed-off-by: Richard Henderson
---
include/semihosting/sys
Split out the non-ARM specific portions of SYS_SEEK to a
reusable function. This handles all GuestFD. Isolate the
curious ARM-specific return value processing to a new
callback, common_semi_seek_cb.
Expand the internal type of the offset to int64_t, and
provide the whence argument, which will be
The ARM-specific SYS_FLEN isn't really something that can be
reused by other semihosting apis, but there are parts that can
reused for the implementation of semihost_sys_fstat.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 4 ++
semihosting/arm-compat-semi.c | 74 ++
This will be used for implementing the xtensa select_one
system call. Choose "poll" over "select" so that we can
reuse Glib's g_poll constants and to avoid struct timeval.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 16
include/semihosting/syscalls.h | 3 ++
Moving this to be useful for another function
besides do_common_semihosting.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 48 +--
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/semihosting/arm-co
Rename qemu_semihosting_connect_chardevs to
qemu_semihosting_chardev_init; pass the result
directly to qemu_semihosting_console_init.
Store the chardev in SemihostingConsole instead
of SemihostingConfig, which lets us drop
semihosting_get_chardev.
Signed-off-by: Richard Henderson
---
include/se
The implementation of qemu_semihosting_console_inc does not
defer to gdbstub, but only reads from the fifo in console.c.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/semihosting/console.h b
These syscalls will be used by m68k and nios2 semihosting.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 7 ++
semihosting/syscalls.c | 137 +
2 files changed, 144 insertions(+)
diff --git a/include/semihosting/syscalls.h b/inclu
Split out the non-ARM specific portions of SYS_READ to a
reusable function. This handles all GuestFD. Isolate the
curious ARM-specific return value processing to a new
callback, common_semi_rw_cb.
Note that gdb_do_syscall %x reads target_ulong, not int.
Signed-off-by: Richard Henderson
---
in
Will replace qemu_semihosting_console_{outs,outc},
but we need more plumbing first.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 12
linux-user/semihost.c | 5 +
semihosting/console.c | 9 +
3 files changed, 26 insertions(+)
dif
On Tue, 7 Jun 2022 20:44:23 +0300
Avihai Horon wrote:
> On 5/30/2022 8:07 PM, Avihai Horon wrote:
> > Hello,
> >
> > Following VFIO migration protocol v2 acceptance in kernel, this series
> > implements VFIO migration according to the new v2 protocol and replaces
> > the now deprecated v1 impleme
This syscall will be used by m68k and nios2 semihosting.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 3 +++
semihosting/syscalls.c | 42 ++
2 files changed, 45 insertions(+)
diff --git a/include/semihosting/syscalls.h b/include/
Split out the non-ARM specific portions of SYS_SYSTEM to a
reusable function.
Signed-off-by: Richard Henderson
---
include/semihosting/syscalls.h | 3 +++
semihosting/arm-compat-semi.c | 12 +-
semihosting/syscalls.c | 40 ++
3 files changed, 44
Allow more than one character to be read at one time.
Will be used by m68k and nios2 semihosting for stdio.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 12 +++-
linux-user/semihost.c | 10 ++
semihosting/arm-compat-semi.c | 11 +--
semihos
Add a GuestFDType for connecting to the semihosting console.
Hook up to read, write, isatty, and fstat syscalls.
Note that the arm-specific syscall flen cannot be applied
to the console, because the console is not a descriptor
exposed to the guest.
Signed-off-by: Richard Henderson
---
include/s
On 6/7/22 13:14, Warner Losh wrote:
+static abi_long freebsd_syscall(void *cpu_env, int num, abi_long arg1,
+abi_long arg2, abi_long arg3, abi_long arg4,
+abi_long arg5, abi_long arg6, abi_long arg7,
+
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 20e99cdcc0..4c8932ad54 100644
--- a/semihosting/arm-compat-semi.c
We don't need CPUArchState, and we do want the CPUState of the
thread performing the operation -- use this instead of current_cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 4 ++--
linux-user/semihost.c | 2 +-
semihosting/arm-comp
Signed-off-by: Richard Henderson
---
semihosting/arm-compat-semi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index dea5b2de8d..21b6bc3a0f 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihostin
Hi Cole,
On Sun, Jun 5, 2022 at 6:46 PM Cole Robinson wrote:
>
> Hi Marc-André,
>
> dbus-display-test seems flakey. I'm occasionally seeing:
>
> ▶ 692/746
> ERROR:../tests/qtest/dbus-display-test.c:68:test_dbus_display_vm:
> assertion failed
> (qemu_dbus_display1_vm_get_name(QEMU_DBUS_DISPLAY1_V
On Tue, Jun 7, 2022 at 2:28 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/7/22 13:14, Warner Losh wrote:
> > +void unlock_iovec(struct iovec *vec, abi_ulong target_addr,
> > +int count, int copy)
> > +{
> > +struct target_iovec *target_vec;
> > +
> > +target_ve
For arm-compat, initialize console_{in,out}_gf;
otherwise, initialize stdio file descriptors.
This will go some way to cleaning up arm-compat, and
will allow other semihosting to use normal stdio.
Signed-off-by: Richard Henderson
---
include/semihosting/guestfd.h | 7 +
include/semihostin
This function has been replaced by *_write.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 13 -
linux-user/semihost.c | 16
semihosting/console.c | 18 --
3 files changed, 47 deletions(-)
diff --git a/include/se
This function has been replaced by *_write.
Signed-off-by: Richard Henderson
---
include/semihosting/console.h | 13 --
linux-user/semihost.c | 17
semihosting/console.c | 49 ---
3 files changed, 79 deletions(-)
diff --git a/
Ping
On Tue, May 24, 2022 at 1:36 PM Dao Lu wrote:
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++-
> target/riscv/insn_trans/
On 6/7/22 13:14, Warner Losh wrote:
+static void helper_unlock_iovec(struct target_iovec *target_vec,
+abi_ulong target_addr, struct iovec *vec,
+int count, int copy)
+{
+for (int i = 0; i < count; i++) {
+abi_ulong base
On 6/7/22 13:14, Warner Losh wrote:
+void unlock_iovec(struct iovec *vec, abi_ulong target_addr,
+int count, int copy)
+{
+struct target_iovec *target_vec;
+
+target_vec = lock_user(VERIFY_READ, target_addr,
+ count * sizeof(struct target_iovec), 1);
+
On Tue, Jun 7, 2022 at 2:01 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/7/22 13:14, Warner Losh wrote:
> > +static void helper_unlock_iovec(struct target_iovec *target_vec,
> > +abi_ulong target_addr, struct iovec
> *vec,
> > +
Reorg m68k_semi_return_* to gdb_syscall_complete_cb.
Use the 32-bit version normally, and the 64-bit version
for HOSTED_LSEEK.
Signed-off-by: Richard Henderson
---
target/m68k/m68k-semi.c | 55 +
1 file changed, 23 insertions(+), 32 deletions(-)
diff --gi
This separates guest file descriptors from host file descriptors,
and utilizes shared infrastructure for integration with gdbstub.
Signed-off-by: Richard Henderson
---
target/m68k/m68k-semi.c | 306 ++--
1 file changed, 76 insertions(+), 230 deletions(-)
diff
On 6/7/22 13:14, Warner Losh wrote:
+/* read(2) */
+static inline abi_long do_bsd_read(abi_long arg1, abi_long arg2, abi_long arg3)
Why the inline markers? Best to drop them.
+/*
+ * File system calls.
+ */
+case TARGET_FREEBSD_NR_read: /* read(2) */
+ret
On Mon, Jun 6, 2022 at 4:22 PM ~eopxd wrote:
>
> According to v-spec, tail agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of tail policies, QEMU should be able to simulate the tail
> agnostic behavior as "set tail elements' bi
On 6/7/22 13:14, Warner Losh wrote:
+/* write(2) */
+static inline abi_long do_bsd_write(abi_long arg1, abi_long arg2, abi_long
arg3)
Likewise drop the inline markers.
r~
On Tue, Jun 7, 2022 at 2:34 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/7/22 13:14, Warner Losh wrote:
> > +static abi_long freebsd_syscall(void *cpu_env, int num, abi_long arg1,
> > +abi_long arg2, abi_long arg3, abi_long
> arg4,
> > +
On Wed, Jun 1, 2022 at 11:37 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> There are currently two types of RISC-V CPUs:
> - Generic CPUs (base or any) that allow complete custimisation
> - "Named" CPUs that match existing hardware
>
> Users can use the base CPUs to custimise the ex
It allows accel->synchronize_post_init() hook to return an error upwards.
Add a new cpu_synchronize_post_init_full() for it, then let the existing
cpu_synchronize_post_init() to call it with errp==NULL.
Signed-off-by: Peter Xu
---
accel/hvf/hvf-accel-ops.c | 2 +-
accel/kvm/kvm-all.c
On 6/7/22 14:51, Warner Losh wrote:
void unlock_iovec(IOVecMap *map, bool copy_out)
{
for (int i = 0, count = map->count; i < count; ++i) {
if (map->host[i].iov_base) {
abi_ulong target_base = tswapal(map->target[i].iov_base);
un
On Wed, Jun 8, 2022 at 8:59 AM Dao Lu wrote:
>
> Ping
The latest version of this patch on the mailing list has comments that
need to be addressed
Alistair
>
> On Tue, May 24, 2022 at 1:36 PM Dao Lu wrote:
> >
> > Tested-by: Heiko Stuebner
> > Signed-off-by: Dao Lu
> > ---
> > target/riscv/c
While we had a call to do_m68k_semihosting in linux-user, it
wasn't actually reachable. We don't include DISAS_INSN(halt)
as an instruction unless system mode.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 5 -
target/m68k/m68k-semi.c| 36 ---
Hi Alistair,
Thanks for the response. I don't think I can find any comments
on this patch though, could you help point me to them?
Thanks,
Dao
On Tue, Jun 7, 2022 at 4:04 PM Alistair Francis wrote:
>
> On Wed, Jun 8, 2022 at 8:59 AM Dao Lu wrote:
> >
> > Ping
>
> The latest version of this pat
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes for v4:
* Split out of v2.
* Convert host errno to gdb errno, which for m68k is guest errno.
r~
Richard Henderson (3):
target/m68k: Eliminate m68k_semi_is_fseek
target/m68k
Allow cpu_synchronize_all_post_init() to fail with an errp when it's set.
Modify both precopy and postcopy to try to detect such error.
Signed-off-by: Peter Xu
---
hw/core/machine.c | 2 +-
include/sysemu/cpus.h | 2 +-
migration/savevm.c| 20 +---
softmmu/cpus.c
On Wed, Jun 1, 2022 at 9:37 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> There are currently two types of RISC-V CPUs:
> - Generic CPUs (base or any) that allow complete custimisation
> - "Named" CPUs that match existing hardware
>
> Users can use the base CPUs to custimise the ext
run_on_cpu API does not yet support any way to pass over an error message
to above. Add a new run_on_cpu_func2 hook to grant possibility of that.
Note that this only changes the cpus-common core, no API is yet introduced
for v2 of the run_on_cpu_func function.
Signed-off-by: Peter Xu
---
cpus-
[Marking this as RFC]
This series teaches QEMU to detect errors when e.g. putting registers from
QEMU to KVM, and fail migrations properly.
For the rational of this series and why it was posted, please refer to the
bug report here:
https://lore.kernel.org/all/YppVupW+IWsm7Osr@xz-m1.local/
But I
> On Jun 7, 2022, at 3:23 PM, Richard Henderson
> wrote:
>
> On 6/7/22 14:51, Warner Losh wrote:
>>void unlock_iovec(IOVecMap *map, bool copy_out)
>>{
>> for (int i = 0, count = map->count; i < count; ++i) {
>> if (map->host[i].iov_base) {
>> abi_
This version of run_on_cpu() allows to take an Error** to detect errors.
Signed-off-by: Peter Xu
---
cpus-common.c | 27 +++
include/hw/core/cpu.h | 26 ++
softmmu/cpus.c| 6 ++
3 files changed, 59 insertions(+)
diff --git a/c
Leverage the new mechanism to pass over errors to upper stack for
kvm_arch_put_registers() when called for the post_init() accel hook.
Signed-off-by: Peter Xu
---
accel/kvm/kvm-all.c | 13 ++---
accel/kvm/kvm-cpus.h | 2 +-
softmmu/cpus.c | 5 -
3 files changed, 15 insertion
On Wed, Jun 8, 2022 at 9:20 AM Dao Lu wrote:
>
> Hi Alistair,
>
> Thanks for the response. I don't think I can find any comments
> on this patch though, could you help point me to them?
I see a PATCH v1 with comments and then your ping to PATCH v2, but I
don't see the original PATCH v2. It might
On Wed, Jun 8, 2022 at 9:27 AM Bin Meng wrote:
>
> On Wed, Jun 1, 2022 at 9:37 AM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > There are currently two types of RISC-V CPUs:
> > - Generic CPUs (base or any) that allow complete custimisation
> > - "Named" CPUs that match exis
On Wed, 01 Jun 2022, Jonathan Cameron wrote:
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
T
From: Peter Maydell
In tpm_tis_mmio_read(), tpm_tis_mmio_write() and
tpm_tis_dump_state(), we calculate a locality index with
tpm_tis_locality_from_addr() and then use it as an index into the
s->loc[] array. In all these cases, the array index can't overflow
because the MemoryRegion is sized to
Hi!
The patches in this PR resolve several Coverity issues and mark a memory
region with TPM response data as dirty so that it does not get lost during
migration.
Stefan
The following changes since commit 7077fcb9b68f058809c9dd9fd1dacae1881e886c:
Merge tag 'vmbus-maint-20220530' of https:
From: Anthony PERARD
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as started could be ignored and not transfered to the
des
Hello there,
considering that Linux v5.19-rc1 is out which includes support for
NVMe TP4084:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/nvme/host/core.c?id=354201c53e61e493017b15327294b0c8ab522d69
I thought that it might be nice to have QEMU support for the
TP4084 adds a new mode, CC.CRIME, that can be used to mark a namespace
as ready independently from the controller.
When CC.CRIME is 0 (default), things behave as before, all namespaces
are ready when CSTS.RDY gets set to 1.
When CC.CRIME is 1, the controller will become ready when CSTS.RDY gets
s
Each NvmeNamespace can be used by serveral controllers,
but a NvmeNamespace can at most belong to a single NvmeSubsystem.
Store a pointer to the NvmeSubsystem, if the namespace was realized
with a NvmeSubsystem.
This will be used by a follow up patch.
Signed-off-by: Niklas Cassel
---
hw/nvme/ns
CRMS.CRWMS bit shall be set to 1 on controllers compliant with versions
later than NVMe 1.4.
The first version later than NVMe 1.4 is NVMe 2.0
Let's claim compliance with NVMe 2.0 such that a follow up patch can
set the CRMS.CRWMS bit.
This is needed since CC.CRIME is only writable when both CRM
Since we verify that "ready_delay" parameter has to be smaller than CRWMT,
we know that the namespace will always become ready.
Therefore the "Namespace Not Ready" status code will never have the DNR
bit set.
Add a new parameter "never_ready" that can be used to emulate a namespace
that never gets
This patch adds shadow doorbell buffer support in NVMe 1.3 to QEMU
NVMe. The Doorbell Buffer Config admin command is implemented for the
guest to enable shadow doobell buffer. When this feature is enabled, each
SQ/CQ is associated with two buffers, i.e., Shadow Doorbell buffer and
EventIdx buffer.
Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3)
and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13
in NVMe Spec 1.3). For queues created before the Doorbell Buffer Config
command, the nvme_dbbuf_config function tries to associate each existing
SQ and CQ
On Tue, Jun 7, 2022 at 12:01 AM Chao Peng wrote:
>
> On Mon, Jun 06, 2022 at 01:09:50PM -0700, Vishal Annapurve wrote:
> > >
> > > Private memory map/unmap and conversion
> > > ---
> > > Userspace's map/unmap operations are done by fallocate() ioctl on the
> > >
When shadow doorbell buffer is enabled, doorbell registers are lazily
updated. The actual queue head and tail pointers are stored in Shadow
Doorbell buffers.
Add trace events for updates on the Shadow Doorbell buffers and EventIdx
buffers. Also add trace event for the Doorbell Buffer Config comman
On 6/7/2022 7:16 PM, Gerd Hoffmann wrote:
Hi,
I guess it could be helpful for the discussion when you can outine the
'big picture' for tdx initialization. How does kvm accel setup look
like without TDX, and what additional actions are needed for TDX? What
ordering requirements and other co
On 6/7/22 16:35, Warner Losh wrote:
On Jun 7, 2022, at 3:23 PM, Richard Henderson
wrote:
On 6/7/22 14:51, Warner Losh wrote:
void unlock_iovec(IOVecMap *map, bool copy_out)
{
for (int i = 0, count = map->count; i < count; ++i) {
if (map->host[i].iov_base) {
On Tue, Jun 7, 2022 at 2:45 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/7/22 13:14, Warner Losh wrote:
> > +/* read(2) */
> > +static inline abi_long do_bsd_read(abi_long arg1, abi_long arg2,
> abi_long arg3)
>
> Why the inline markers? Best to drop them.
>
static inline e
On Tue, Jun 07, 2022 at 05:55:46PM -0700, Marc Orr wrote:
> On Tue, Jun 7, 2022 at 12:01 AM Chao Peng wrote:
> >
> > On Mon, Jun 06, 2022 at 01:09:50PM -0700, Vishal Annapurve wrote:
> > > >
> > > > Private memory map/unmap and conversion
> > > > ---
> > > > Use
This separates guest file descriptors from host file descriptors,
and utilizes shared infrastructure for integration with gdbstub.
Signed-off-by: Richard Henderson
---
target/nios2/nios2-semi.c | 321 +-
1 file changed, 77 insertions(+), 244 deletions(-)
diff
Reorg nios2_semi_return_* to gdb_syscall_complete_cb.
Use the 32-bit version normally, and the 64-bit version
for HOSTED_LSEEK.
Signed-off-by: Richard Henderson
---
target/nios2/nios2-semi.c | 59 +++
1 file changed, 23 insertions(+), 36 deletions(-)
diff --g
Based-on: <20220607204557.658541-1-richard.hender...@linaro.org>
("[PATCH v4 00/53] semihosting cleanup")
Changes for v4:
* Split out of v2.
* Convert host errno to gdb errno, which for nios2 is guest errno.
r~
Richard Henderson (3):
target/nios2: Eliminate nios2_semi_is_lseek
target/n
Semihosting is not enabled for nios2-linux-user.
Signed-off-by: Richard Henderson
---
target/nios2/nios2-semi.c | 5 -
target/nios2/meson.build | 4 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index bdf8849689..55
The new PAPR 2.12 defines a watchdog facility managed via the new
H_WATCHDOG hypercall.
This adds H_WATCHDOG support which a proposed driver for pseries uses:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=303120
This was tested by running QEMU with a debug kernel and command line
This patch adds RISC-V Zihintpause support. The extension is set to be enabled
by default and opcode has been added to insn32.decode.
Added trans_pause for TCG to mainly to break reservation and exit the TB.
The change can also be found in:
https://github.com/dlu42/qemu/tree/zihintpause_support_v
201 - 300 of 329 matches
Mail list logo
