Re: [PATCH] MAINTAINERS: change Ben Widawsky's email address

On Tue, 7 Jun 2022 09:26:28 -0700 Ben Widawsky wrote: > ben@widaw...@intel.com will stop working on 2022-06-20, change it to my > personal email address. > > Update .mailmap to handle previously authored commits. > > Signed-off-by: Ben Widawsky With below question addressed, Acked-by: Jonatha

Re: [PATCH 2/3] target/mips: implement Octeon-specific BBIT instructions

On 6/7/22 01:59, Pavel Dovgalyuk wrote: +# Branch on bit set or clear +# BBIT0 110010 . . +# BBIT032110110 . . +# BBIT1 111010 . . +# BBIT13210 . . + +BBIT 11 set:1 sh

Re: [PATCH 3/3] target/mips: implement Octeon-specific arithmetic instructions

On 6/7/22 01:59, Pavel Dovgalyuk wrote: +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) +{ +TCGv t0, t1; +int p; +TCGLabel *l1; + +if (a->rt == 0) { +/* nop */ +return true; +} + +p = a->p; +if (a->shift) { +p += 32; +} + +t0 = t

Re: about the current status of Multi-process QEMU / out-of-process emulation

Hello Jag, It's quite nice of you to give me so much details about this feature. I tried with this repo by using the python script. The server and client qemu processes are created successfully. I'm interested in it due to the requirement for higher security level in cloud environment. We're taki

Re: [PATCH 02/21] aspeed: i2c: Add ctrl_global_rsvd property

Hello Joe, On 6/7/22 02:05, Joel Stanley wrote: On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote: From: Joe Komlodi The Aspeed I2C controller is used across other SKUs that have different reserved bits for the ctrl_global_rsvd register. I think rsvd stands for reserved? Lets spell out

Re: [PATCH v3 09/49] semihosting: Adjust error checking in common_semi_cb

On 5/23/22 08:35, Richard Henderson wrote: That implies that our current code is right, in that the way to check for "did the call fail" is to look at the retcode, not the errno (in the same way that if you make a native syscall or library call you look first at its return value, not at errno). T

Re: [PATCH v5 02/10] kvm: Support for querying fd-based stats

* Paolo Bonzini (pbonz...@redhat.com) wrote: > From: Mark Kanda > > Add support for querying fd-based KVM stats - as introduced by Linux kernel > commit: > > cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data") > > This allows the user to analyze the behavior of the VM withou

Re: [PATCH v2 00/11] vfio/migration: Implement VFIO migration protocol v2

On 5/30/2022 8:07 PM, Avihai Horon wrote: Hello, Following VFIO migration protocol v2 acceptance in kernel, this series implements VFIO migration according to the new v2 protocol and replaces the now deprecated v1 implementation. The main differences between v1 and v2 migration protocols are:

Re: [PATCH v2 02/11] vfio/migration: Skip pre-copy if dirty page tracking is not supported

On 5/30/2022 8:12 PM, Avihai Horon wrote: On 5/30/2022 8:07 PM, Avihai Horon wrote: Currently, if IOMMU of a VFIO container doesn't support dirty page tracking, migration is blocked completely. This is because a DMA-able VFIO device can dirty RAM pages without updating QEMU about it, thus bre

Re: [PATCH v3 23/49] semihosting: Split out semihost_sys_open

On 5/23/22 06:30, Peter Maydell wrote: diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c index b6405f5663..7ac2e147a8 100644 --- a/semihosting/guestfd.c +++ b/semihosting/guestfd.c @@ -11,6 +11,11 @@ #include "qemu/osdep.h" #include "exec/gdbstub.h" #include "semihosting/guestfd.h"

Re: [PATCH v5 06/10] hmp: add basic "info stats" implementation

* Paolo Bonzini (pbonz...@redhat.com) wrote: > From: Mark Kanda > > Add an HMP command to retrieve statistics collected at run-time. > The command will retrieve and print either all VM-level statistics, > or all vCPU-level statistics for the currently selected CPU. > > Signed-off-by: Paolo Bonzi

[PATCH 2/6] bsd-user/freebsd/os-syscall.c: unlock_iovec

Releases the references to the iovec created by lock_iovec. Signed-off-by: Warner Losh --- bsd-user/freebsd/os-syscall.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/bsd-user/freebsd/os-syscall.c b/bsd-user/freebsd/os-syscall.c index c41ef0eda40..510307f29d9 100644 --- a/b

[PATCH 3/6] bsd-user/freebsd/os-syscall.c: Tracing and error boilerplate

Add in the tracing and this system call not implemented boilerplate. Do this by moving the guts of do_freebsd_syscall to freebsd_syscall. Put the tracing in the wrapper function. Since freebsd_syscall is a singleton static function, it will almost certainly be inlined. Fix comments that referred to

[PATCH 1/6] bsd-user/freebsd/os-syscall.c: lock_iovec

lock_iovec will lock an I/O vec and the memory to which it refers and create a iovec in the host space that refers to it, with full error unwinding. Add helper_iovec_unlock to unlock the partially locked iovec in case there's an error. The code will be used in iovec_unlock when that is committed.

[PATCH 0/6] bsd-user upstreaming: read, write and exit

This series of patches continues the effort to get system calls working upstream. This series was cleaved off a prior series to give me time to rework based on the feedback from the first time I posted these. These still need review based on comments from Richard Henderson o bsd-user/free

[PATCH 5/6] bsd-user/bsd-file.h: Meat of the write system calls

Implement write, writev, pwrite and pwritev and connect them to the system call dispatch routine. Signed-off-by: Stacey Son Signed-off-by: Kyle Evans Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-file.h | 85 +++ bsd-user/

[PATCH 4/6] bsd-user/bsd-file.h: Add implementations for read, pread, readv and preadv

Implement do_bsd_{read,pread,readv,preadv}. Connect them to the system call table. Signed-off-by: Stacey Son Signed-off-by: Kyle Evans Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-file.h | 79 +++ bsd-user/freebsd/os-sysc

[PATCH 6/6] bsd-user/freebsd/os-syscall.c: Implement exit

Implement the exit system call. Bring in bsd-proc.h to contain all the process system call implementation and helper routines. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/bsd-proc.h | 43 +++

[PATCH] MAINTAINERS: change Ben Widawsky's email address

ben@widaw...@intel.com will stop working on 2022-06-20, change it to my personal email address. Update .mailmap to handle previously authored commits. Signed-off-by: Ben Widawsky --- .mailmap| 1 + MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.mailmap b/

Re: [PATCH] MAINTAINERS: change Ben Widawsky's email address

On 22-06-07 17:50:35, Jonathan Cameron wrote: > On Tue, 7 Jun 2022 09:26:28 -0700 > Ben Widawsky wrote: > > > ben@widaw...@intel.com will stop working on 2022-06-20, change it to my > > personal email address. > > > > Update .mailmap to handle previously authored commits. > > > > Signed-off-by:

[PATCH] qemu: make version available in coredump

Add a variable with QEMU_FULL_VERSION definition. Then the content of the variable is easily searchable: strings /path/to/core | grep QEMU_FULL_VERSION 'volatile' keyword is used to avoid removing the variable by compiler as unused. Signed-off-by: Vladimir Sementsov-Ogievskiy --- Hi all! P

[PATCH v2 00/71] target/arm: Scalable Matrix Extension

Changes for v2: * Incorporate feedback from v1. Richard Henderson (71): target/arm: Rename TBFLAG_A64 ZCR_LEN to VL linux-user/aarch64: Introduce sve_vq target/arm: Remove route_to_el2 check from sve_exception_el target/arm: Remove fp checks from sve_exception_el target/arm: Add el_is

[PATCH v2 01/71] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL

With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Renamed from SVE_LEN to VL. --- target/arm/cpu.h | 3 ++- target/arm/translate-a64.h | 2 +- ta

[PATCH v2 03/71] target/arm: Remove route_to_el2 check from sve_exception_el

We handle this routing in raise_exception. Promoting the value early means that we can't directly compare FPEXC_EL and SVEEXC_EL. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm

[PATCH v2 05/71] target/arm: Add el_is_in_host

This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c| 28 ++

[PATCH v2 04/71] target/arm: Remove fp checks from sve_exception_el

Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/he

[PATCH v2 07/71] target/arm: Use el_is_in_host for sve_exception_el

The ARM pseudocode function CheckNormalSVEEnabled uses this predicate now, and I think it's a bit clearer. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/ar

[PATCH v2 08/71] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el

This check is buried within arm_hcr_el2_eff(), but since we have to have the explicit check for CPTR_EL2.TZ, we might as well just check it once at the beginning of the block. Once this is done, we can test HCR_EL2.{E2H,TGE} directly, rather than going through arm_hcr_el2_eff(). Reviewed-by: Pete

[PATCH v2 06/71] target/arm: Use el_is_in_host for sve_zcr_len_for_el

The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+

[PATCH v2 09/71] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset

We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index

[PATCH v2 10/71] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller

This function is used only once, and will need modification for Streaming SVE mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 --- target/arm/helper.c| 30 +++--- 2 files changed, 11 insertions(+), 30 deletion

[PATCH v2 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h

Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 127 + target/arm/sve_helper.c| 107 +-

[PATCH v2 12/71] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el

This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g'

[PATCH v2 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags

These are required to determine if various insns are allowed to issue. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 target/arm/helper.c| 4 target/arm/translate-a64.c | 2 ++ 4 files changed,

[PATCH v2 15/71] target/arm: Move expand_pred_b to vec_internal.h

Put the inline function near the array declaration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 8 +++- target/arm/sve_helper.c | 9 - 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/vec_internal.h b/target

[PATCH v2 11/71] target/arm: Use uint32_t instead of bitmap for sve vq's

The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing

[PATCH v2 02/71] linux-user/aarch64: Introduce sve_vq

Add an interface function to extract the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

[PATCH v2 31/71] target/arm: Move error for sve%d property to arm_cpu_sve_finalize

Keep all of the error messages together. This does mean that when setting many sve length properties we'll only generate one error, but we only really need one. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --

[PATCH v2 14/71] target/arm: Export sve contiguous ldst support functions

Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 94 ++ target/arm/sve_h

[PATCH v2 16/71] target/arm: Use expand_pred_b in mve_helper.c

Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to do nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses t

[PATCH v2 18/71] target/arm: Export bfdotadd from vec_helper.c

We will need this over in sme_helper.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 13 + target/arm/vec_helper.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_inte

[PATCH v2 17/71] target/arm: Move expand_pred_h to vec_internal.h

Move the data to vec_helper.c and the inline to vec_internal.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 7 +++ target/arm/sve_helper.c | 29 - target/arm/vec_helper.c | 26 ++ 3 file

[PATCH v2 33/71] target/arm: Generalize cpu_arm_{get,set}_vq

Rename from cpu_arm_{get,set}_sve_vq, and take the ARMVQMap as the opaque parameter. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0a2f4f317

[PATCH v2 20/71] target/arm: Add ID_AA64SMFR0_EL1

This register is allocated from the existing block of id registers, so it is already RES0 for cpus that do not implement SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h| 25 + target/arm/helper.c | 4 ++-- target/arm/kvm64.c |

[PATCH v2 21/71] target/arm: Implement TPIDR2_EL0

This register is part of SME, but isn't closely related to the rest of the extension. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 + target/arm/helper.c | 32 2 files changed, 33 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h in

[PATCH v2 19/71] target/arm: Add isar_feature_aa64_sme

This will be used for implementing FEAT_SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2cc28f9e59..ce89ef5dc2 100644 --- a/target/arm/cpu.h +++ b/target/arm/

[PATCH v2 23/71] target/arm: Add syn_smetrap

This will be used for raising various traps for SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 0cb26dde7d..4002766302 100644 --- a/

[PATCH v2 25/71] target/arm: Add SVCR

This cpreg is used to access two new bits of PSTATE that are not visible via any other mechanism. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 6 ++ target/arm/helper.c | 13 + 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h inde

[PATCH v2 22/71] target/arm: Add SMEEXC_EL to TB flags

This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c| 52 +

[PATCH v2 26/71] target/arm: Add SMCR_ELx

These cpregs control the streaming vector length and whether the full a64 instruction set is allowed while in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h| 8 ++-- target/arm/helper.c | 41 + 2

[PATCH v2 24/71] target/arm: Add ARM_CP_SME

This will be used for controlling access to SME cpregs. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h| 5 + target/arm/translate-a64.c | 18 ++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpr

[PATCH v2 39/71] target/arm: Add SVL to TB flags

We need SVL separate from VL for RDSVL at al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 target/arm/translate.h | 1 + target/arm/helper.c| 8 +++- target/arm/transla

[PATCH v2 30/71] target/arm: Implement SMSTART, SMSTOP

These two instructions are aliases of MSR (immediate). Use the two helpers to properly implement svcr_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper-sme.h| 21 + target/arm/helper.h| 1 + targe

[PATCH v2 27/71] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2

Implement the streaming mode identification register, and the two streaming priority registers. For QEMU, they are all RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 33 + 1 file changed, 33 insertions(+) diff --git

[PATCH v2 43/71] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 15 +++ target/arm/translate-sve.c | 38 +++

[PATCH v2 32/71] target/arm: Create ARMVQMap

Pull the three sve_vq_* values into a structure. This will be reused for SME. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 29 ++--- target/arm/cpu64.c | 22 +++--- target/arm/helper.c | 2 +- target/arm/kvm64.c | 2 +- 4 files changed, 2

[PATCH v2 29/71] target/arm: Add the SME ZA storage to CPUARMState

Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 target/arm/machine.c | 34 ++ 2 files changed, 42 insertions(+) diff --g

[PATCH v2 47/71] target/arm: Export unpredicated ld/st from translate-sve.c

Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 -- 2 files changed, 39 insertions(+

[PATCH v2 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len

Rename from cpu_arm_{get,set}_sve_default_vec_len, and take the pointer to default_vq from opaque. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c ind

[PATCH v2 38/71] target/arm: Introduce sve_vqm1_for_el_sm

When Streaming SVE mode is enabled, the size is taken from SMCR_ELx instead of ZCR_ELx. The format is shared, but the set of vector lengths is not. Further, Streaming SVE does not require any particular length to be supported. Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM to the

[PATCH v2 44/71] target/arm: Implement SME ZERO

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/translate-a64.h | 1 + target/arm/sme_helper.c| 25 + target/arm/translate-a64.c | 15 +++ target/arm/translate-sme.c | 13 + target/arm/sme.decode | 4 ++

[PATCH v2 46/71] target/arm: Implement SME LD1, ST1

We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 82 + target/arm/sme_helper.c| 615 +++

[PATCH v2 35/71] target/arm: Move arm_cpu_*_finalize to internals.h

Drop the aa32-only inline fallbacks, and just use a couple of ifdefs. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 -- target/arm/internals.h | 3 +++ target/arm/cpu.c | 2 ++ 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/ar

[PATCH v2 41/71] target/arm: Add infrastructure for disas_sme

This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 7 ++- target/arm/translate-sme.c | 35 +++ ta

[PATCH v2 36/71] target/arm: Unexport aarch64_add_*_properties

These functions are not used outside cpu64.c, so make them static. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 --- target/arm/cpu64.c | 4 ++-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25a77ec676..8a89548cb9 100644

[PATCH v2 42/71] target/arm: Trap AdvSIMD usage when Streaming SVE is active

This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought

[PATCH v2 50/71] target/arm: Implement FMOPA, FMOPS (non-widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme_helper.c| 67 ++ target/arm/translate-sme.c | 33 +++ target/arm/sme.decode | 9 + 4 files changed, 114 insertions(+) diff --git a/target/arm

[PATCH v2 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h

We will need these functions in translate-sme.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 38 ++ target/arm/translate-sve.c | 36 2 files changed, 38 insertions(+), 36 deletions(-) diff --git a/tar

[PATCH v2 37/71] target/arm: Add cpu properties for SME

Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point fo

[PATCH v2 58/71] target/arm: Enable SME for -cpu max

Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Signed-off-by: Richard Henderson --- target/arm/cpu64.c| 11 +++ docs/system/arm/emulation.rst | 4 2 files chang

[PATCH v2 48/71] target/arm: Implement SME LDR, STR

We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Signed-off-by: Richard Henderson --- target/arm/translate-sme.c | 23 +++ target/arm/sme.decode | 7 +++ 2 files changed, 30 insertions(+) diff --git a/target/ar

[PATCH v2 45/71] target/arm: Implement SME MOVA

We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 11 target/arm/helper-sve.h| 2 + target/arm/translate-a64.h | 9 +++

[PATCH v2 54/71] target/arm: Implement PSEL

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 57 ++ target/arm/sve.decode | 20 + 2 files changed, 77 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index adf0cd3e68..58d0894e15 100644 -

[PATCH v2 49/71] target/arm: Implement SME ADDHA, ADDVA

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme_helper.c| 90 ++ target/arm/translate-sme.c | 30 + target/arm/sme.decode | 11 + 4 files changed, 136 insertions(+) diff --git a/target/arm/helpe

[PATCH v2 51/71] target/arm: Implement BFMOPA, BFMOPS

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme_helper.c| 52 ++ target/arm/translate-sme.c | 29 + target/arm/sme.decode | 2 ++ 4 files changed, 85 insertions(+) diff --git a/target/arm/he

[PATCH v2 65/71] linux-user/aarch64: Move sve record checks into restore

Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51

[PATCH v2 55/71] target/arm: Implement REVD

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve_helper.c| 16 target/arm/translate-sve.c | 2 ++ target/arm/sve.decode | 1 + 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index

[PATCH v2 62/71] linux-user/aarch64: Tidy target_restore_sigframe error return

Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch

[PATCH v2 56/71] target/arm: Implement SCLAMP, UCLAMP

Signed-off-by: Richard Henderson --- target/arm/helper.h| 18 +++ target/arm/translate-sve.c | 102 + target/arm/vec_helper.c| 24 + target/arm/sve.decode | 5 ++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helpe

[PATCH v2 70/71] target/arm: Enable SME for user-only

Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cb9f9f02c..13b008547e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @

[PATCH v2 59/71] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user

[PATCH v2 63/71] linux-user/aarch64: Do not allow duplicate or short sve records

In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 - 1 file changed, 4 insertions(+), 1 delet

[PATCH v2 52/71] target/arm: Implement FMOPA, FMOPS (widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme_helper.c| 74 ++ target/arm/translate-sme.c | 2 ++ target/arm/sme.decode | 1 + 4 files changed, 79 insertions(+) diff --git a/target/arm/helper-sme.h b/target/

[PATCH v2 71/71] linux-user/aarch64: Add SME related hwcap entries

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f7eae357f4..8135960305 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -601,6 +601,18 @@ enum {

[PATCH v2 68/71] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL

These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++ linux-user/syscall.c | 16 +++ 2 files changed,

[PATCH v2 61/71] linux-user/aarch64: Add SM bit to SVE signal context

Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-

[PATCH v4 11/53] semihosting: Clean up common_semi_flen_cb

Do not read from the gdb struct stat buffer if the callback is reporting an error. Use common_semi_cb to finish returning results. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions

[PATCH v2 57/71] target/arm: Reset streaming sve state on exception boundaries

We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3e0326af58.

[PATCH v2 64/71] linux-user/aarch64: Verify extra record lock succeeded

Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,

[PATCH v2 53/71] target/arm: Implement SME integer outer product

This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 16 target/arm/sme_helper.c| 82 ++ target/arm/translate-sme.c | 14 +++ target/arm/sme.decode | 10 +

[PATCH v4 10/53] semihosting: Adjust error checking in common_semi_cb

The err parameter is non-zero if and only if an error occured. Use this instead of ret == -1 for determining if we need to update the saved errno. This fixes the errno setting of SYS_ISTTY, which returns 0 on error, not -1. Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 2

[PATCH v4 01/53] semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.h

We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- .../{exec/softmmu-semi.h => semihosting/softmmu-uaccess.h}

[PATCH v4 12/53] semihosting: Clean up common_semi_open_cb

Use common_semi_cb to return results instead of calling set_swi_errno and common_semi_set_ret directly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/semihosting/arm-compat-se

[PATCH v4 03/53] semihosting: Improve condition for config.c and console.c

While CONFIG_SEMIHOSTING is currently only set for softmmu, this will not continue to be true. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- semihosting/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/semihosting/meson.build b/semihosting/meson.

[PATCH v2 60/71] linux-user/aarch64: Reset PSTATE.SM on syscalls

Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 + 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c

[PATCH v2 66/71] linux-user/aarch64: Implement SME signal handling

Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 162 +--- 1 file changed, 151 insertions(+), 11 deleti

[PATCH v4 15/53] semihosting: Remove GDB_O_BINARY

The value is zero, and gdb always opens files in binary mode. Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index cebbad2355..92c13

[PATCH v4 08/53] semihosting: Split out guestfd.c

In arm-compat-semi.c, we have more advanced treatment of guest file descriptors than we do in other implementations. Split out GuestFD and related functions to a new file so that they can be shared. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- configs/targets/aarch64-linux-us

[PATCH v2 67/71] linux-user: Rename sve prctls

Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 linux-user/syscall.c | 12 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)

[PATCH v2 69/71] target/arm: Only set ZEN in reset if SVE present

There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 75295a14a3..5cb9f9f02c 100644 --- a/target/arm/cpu.c +++ b/target/arm

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