On Mon, Jun 06, 2022 at 01:09:50PM -0700, Vishal Annapurve wrote:
> >
> > Private memory map/unmap and conversion
> > ---
> > Userspace's map/unmap operations are done by fallocate() ioctl on the
> > backing store fd.
> > - map: default fallocate() with mode=0.
On 6/7/22 03:19, Joel Stanley wrote:
Update the test_arm_ast2600_debian test to
- the latest Debian kernel
- use the Rainier machine instead of Tacoma
Both of which contains support for more hardware and thus exercises more
of the hardware Qemu models.
Signed-off-by: Joel Stanley
Review
CC arnd
On Sun, Jun 5, 2022 at 9:32 AM Stafford Horne wrote:
> On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote:
> > On Fri, Jun 03, 2022 at 09:05:09AM +0200, Geert Uytterhoeven wrote:
> > > On Thu, Jun 2, 2022 at 9:59 PM Stafford Horne wrote:
> > > > On Thu, Jun 02, 2022 at 09:08:
> -Original Message-
> From: Peter Maydell
> Sent: 06 June 2022 11:20
> To: Frederic Konrad
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> edgar.igles...@gmail.com; alist...@alistair23.me; Sai Pavan Boddu
> ; Edgar Iglesias ;
> fkon...@amd.com
> Subject: Re: [PATCH v3 0/4] xlnx-zcu
On 03/06/2022 23:00, Daniel Henrique Barboza wrote:
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
XiveSource *xsrc =
Thanks Philippe.
Hi Igor,
Any comments about this patch?
On Wed, Jun 1, 2022 at 2:28 PM Philippe Mathieu-Daudé via
wrote:
>
> Cc'ing Igor
>
> On Fri, May 20, 2022 at 11:56 AM Li Zhang wrote:
> >
> > When no memory backend is specified in machine options,
> > a default memory device will be adde
On Tue, Jun 7, 2022 at 10:11 AM Geert Uytterhoeven wrote:
> On Sun, Jun 5, 2022 at 9:32 AM Stafford Horne wrote:
> > On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote:
> > It might be a good idea to revisit the qemu implementation and make
> > sure that the extra byteswap is
On Thu, 2 Jun 2022 at 23:21, Richard Henderson
wrote:
>
> Pull the three sve_vq_* values into a structure.
> This will be reused for SME.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 07/06/2022 08:42, Cédric Le Goater wrote:
On 6/2/22 18:16, Frederic Barrat wrote:
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely
On Thu, 2 Jun 2022 at 23:10, Richard Henderson
wrote:
>
> Rename from cpu_arm_{get,set}_sve_default_vec_len,
> and take the pointer to default_vq from opaque.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 27 ++-
> 1 file changed, 14 insertions(+), 13
On Thu, 2 Jun 2022 at 23:10, Richard Henderson
wrote:
>
> Keep all of the error messages together. This does mean that
> when setting many sve length properties we'll only generate
> one error, but we only really need one.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 15 +++
On Thu, 2 Jun 2022 at 23:29, Richard Henderson
wrote:
>
> Rename from cpu_arm_{get,set}_sve_vq, and take the
> ARMVQMap as the opaque parameter.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 2 Jun 2022 at 23:17, Richard Henderson
wrote:
>
> These functions are not used outside cpu64.c,
> so make them static.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 3 ---
> target/arm/cpu64.c | 4 ++--
> 2 files changed, 2 insertions(+), 5 deletions(-)
Reviewed-by:
On Thu, 2 Jun 2022 at 23:12, Richard Henderson
wrote:
>
> Drop the aa32-only inline fallbacks,
> and just use a couple of ifdefs.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On 07/06/2022 08:35, Cédric Le Goater wrote:
Also, the comment seems wrong to me. The qom parenting doesn't matter
when building the device tree.
it does. See pnv_dt_xscom()
Yeah, what I meant is that on P9, there's no "dt_scom" method for the
PHB. The PHBs are added by the dt_scom()
Richard Henderson writes:
> Do not read from the gdb struct stat buffer if the callback is
> reporting an error. Use common_semi_cb to finish returning results.
>
> Signed-off-by: Richard Henderson
> ---
> semihosting/arm-compat-semi.c | 20 +++-
> 1 file changed, 11 insertion
The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions
---
Pavel Dovgalyuk (3):
target/mips: introduce generic Cavium Octe
This patch adds generic Octeon vCPU for providing
Octeon-specific instructions.
Signed-off-by: Pavel Dovgalyuk
---
target/mips/cpu-defs.c.inc | 30 ++
target/mips/mips-defs.h|1 +
2 files changed, 31 insertions(+)
diff --git a/target/mips/cpu-defs.c.inc b/t
This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.
Signed-off-by: Pavel Dovgalyuk
---
target/mips/tcg/meson.build|2 +
target/mips/tcg/octeon.decode | 14 ++
target/mips/tcg/octeon_translate.c | 53 ++
This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI
Signed-off-by: Pavel Dovgalyuk
---
target/mips/helper.h|1
target/mips/tcg/meson.build |1
target/mips/tcg/octeon.decode
Building on the introduction of config-$target.mak, make tests/tcg a
"regular" subdirectory that is entered simply with "make -C", like the
ROMs or the plugins.
The next step could be to unify all the sub-make rules; this series
stops short of that.
Paolo
Paolo Bonzini (7):
meson: put cross co
The tests/tcg Makefile invocation contains the paths to DOCKER_SCRIPT
and TARGET.
One can just resolve the path to docker.py in configure so that submakes
do not need the DOCKER_SCRIPT variable. In order to remove the TARGET
variable, create a config-target.mak file in tests/tcg/$TARGET. For now
Include the full path in TARGET_DIR, so that messages from sub-Makefiles
are clearer. Also, prepare for possibly building firmware outside
pc-bios/ from the Makefile,
Signed-off-by: Paolo Bonzini
---
Makefile | 12 +---
configure | 6 +++---
2 files changed, 8 insertions(+), 10 deleti
Do not require a cross-compiler prefix for e.g. i386 on x86_64, or
big endian on little endian.
Signed-off-by: Paolo Bonzini
---
configure | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/configure b/configure
index b1aa97e470..28f8c6188b 1
It will not be specific to tests/tcg anymore once it will be possible to
build firmware using container-based cross compilers too. Prepare for that
already, after all Makefile.prereqs is not _used_ by tests/tcg.
Signed-off-by: Paolo Bonzini
---
Makefile | 5 -
configure
In preparation for removing $(DOCKER_SCRIPT) from the tests/tcg configuration
files, have Make use the same container engine that had been probed at
configure time.
Signed-off-by: Paolo Bonzini
---
configure | 11 ---
tests/docker/Makefile.include | 2 +-
2 files cha
On Thu, 2 Jun 2022 at 23:28, Richard Henderson
wrote:
>
> When Streaming SVE mode is enabled, the size is taken from
> SMCR_ELx instead of ZCR_ELx. The format is shared, but the
> set of vector lengths is not. Further, Streaming SVE does
> not require any particular length to be supported.
>
> A
While at it, remove a dead assignment and simply inline the value of the
"target" variable, which is used just once.
Signed-off-by: Paolo Bonzini
---
meson.build | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/meson.build b/meson.build
index 21cd949082..3f38b3
+ Arnd
On Sun, Jun 5, 2022 at 10:19 AM Jason A. Donenfeld wrote:
>
> Hi folks,
>
> On Sun, Jun 05, 2022 at 04:32:13PM +0900, Stafford Horne wrote:
> > Why can't m68k switch to little-endian in qemu and the kernel? The m68k
> > virt
> > platform is not that old, 1 year? Are there a lot of users
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Unfortunately not all filters use .file child as filtered child. Two
exclusions are mirror_top and commit_top. Happily they both are private
filters. Bad thing is that this inconsistency is observable through qmp
commands query-block / query-
Name the symbolic link "Makefile" and place it in the target subdirectory.
Signed-off-by: Paolo Bonzini
---
configure | 3 ++-
tests/Makefile.include | 7 +++
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index 9d49ea4c5b..f35847c3cd 100755
On Tue, Jun 07, 2022 at 10:42:08AM +0200, Arnd Bergmann wrote:
> On Tue, Jun 7, 2022 at 10:11 AM Geert Uytterhoeven
> wrote:
> > On Sun, Jun 5, 2022 at 9:32 AM Stafford Horne wrote:
> > > On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote:
> > > It might be a good idea to revisit
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We don't need to remove bs->file, generic layer takes care of it. No
other driver cares to remove bs->file on failure by hand.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/blklogwrites.c | 4
1 file changed, 4 deletions(-)
On 6/7/22 01:49, Joel Stanley wrote:
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
From: Joe Komlodi
Using a register array will allow us to represent old-mode and new-mode
I2C registers by using the same underlying register array, instead of
adding an entire new set of variables to r
On Thu, 2 Jun 2022 at 23:33, Richard Henderson
wrote:
>
> Mirror the properties for SVE. The main difference is
> that any arbitrary set of powers of 2 may be supported,
> and not the stricter constraints that apply to SVE.
>
> Include a property to control FEAT_SME_FA64, as failing
> to restrict
On Mon, 6 Jun 2022 13:11:36 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 4:35 PM Igor Mammedov wrote:
> >
> > On Thu, 2 Jun 2022 16:31:25 +0200
> > Igor Mammedov wrote:
> >
> > > On Tue, 31 May 2022 14:40:15 +0200
> > > Julia Suvorova wrote:
> > >
> > > > On Sat, May 28, 2022 at 6:
On 7/6/22 00:23, Taylor Simpson wrote:
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, 2 Jun 2022 at 23:18, Richard Henderson
wrote:
>
> We need SVL separate from VL for RDSVL at al, as well as
"et al"
> ZA storage loads and stores, which do not require PSTATE.SM.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 12
> target/arm/tran
On Mon, 6 Jun 2022 12:52:00 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 5:04 PM Igor Mammedov wrote:
> >
> > On Fri, 27 May 2022 18:56:48 +0200
> > Julia Suvorova wrote:
> >
> > > Introduce the 64-bit entry point. Since we no longer have a total
> > > number of structures, stop check
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Almost all drivers call bdrv_open_child() similarly. Let's create a
helper for this.
The only not updated driver that call bdrv_open_child() to set
bs->file is raw-format, as it sometimes want to have filtered child but
don't set drv->is_fil
On 6/7/22 11:40, Paolo Bonzini wrote:
Building on the introduction of config-$target.mak
Brain fart, or perhaps selective amnesia: building on the removal of
Makefile.qemu.
Paolo
, make tests/tcg a
"regular" subdirectory that is entered simply with "make -C", like the
ROMs or the plugins.
On Thu, 2 Jun 2022 at 23:21, Richard Henderson
wrote:
>
> We will need these functions in translate-sme.c.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 Jun 2022 10:24:43 -0700
Ben Widawsky wrote:
> On 22-05-31 09:26:27, Paolo Bonzini wrote:
> > On 5/30/22 15:45, Jonathan Cameron via wrote:
> > > +object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
> > > +machine_get_cfmw, machine_set_cfmw,
> > > +
On Thu, 2 Jun 2022 at 23:41, Richard Henderson
wrote:
>
> This includes the build rules for the decoder, and the
> new file for translation, but excludes any instructions.
>
> Signed-off-by: Richard Henderson
> @@ -14814,7 +14814,12 @@ static void
> aarch64_tr_translate_insn(DisasContextBase *d
On Tue, Jun 7, 2022 at 11:47 AM Stafford Horne wrote:
> On Tue, Jun 07, 2022 at 10:42:08AM +0200, Arnd Bergmann wrote:
> > Goldfish is a very old platform, as far as I know only the kernel port is
> > new.
> > I don't know when qemu started shipping goldfish, but changing it now would
> > surely
On 7/6/22 00:23, Taylor Simpson wrote:
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonS
On 7/6/22 03:19, Joel Stanley wrote:
Update the test_arm_ast2600_debian test to
- the latest Debian kernel
- use the Rainier machine instead of Tacoma
Why can't we keep both?
Both of which contains support for more hardware and thus exercises more
of the hardware Qemu models.
"QEMU"
On Mon, 6 Jun 2022 13:38:57 +0200
Julia Suvorova wrote:
> On Thu, Jun 2, 2022 at 5:20 PM Igor Mammedov wrote:
> >
> > On Fri, 27 May 2022 18:56:50 +0200
> > Julia Suvorova wrote:
> >
> > > The new test is run with a large number of cpus and checks if the
> > > core_count field in smbios_cpu_t
On Mon, 6 Jun 2022 10:39:52 -0700
Ben Widawsky wrote:
> On 22-05-31 13:39:53, Jonathan Cameron wrote:
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> >
> > Signed-off-by: Jonathan Cameron
> > ---
On 6/7/22 01:16, Joel Stanley wrote:
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
Add a RTC device on bus 15 and check that the ouput of the hwclock
spelling: output
command matches the current year.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
tests/avoca
INSTALL and LIBTOOL are not used anymore, but OBJCFLAGS is new and
was not listed.
Signed-off-by: Paolo Bonzini
---
configure | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/configure b/configure
index f35847c3cd..ce81419629 100755
--- a/configure
+++ b/configure
@@ -2737,1
Setting the MAKE variable to a GNU Make executable does not really have
any effect: if a non-GNU Make is used, the QEMU Makefile will fail to
parse. Just remove everything related to --make and $make as dead code.
Signed-off-by: Paolo Bonzini
---
configure | 16 +---
1 file changed,
On Mon, 6 Jun 2022 10:33:38 -0700
Ben Widawsky wrote:
> On 22-06-01 17:42:27, Jonathan Cameron wrote:
> > Changes since v1 (thanks to Paolo Bonzini)
> > * Update 'description' of cxl-fmw as suggested to mention it's an array.
> > * Add a wrapper cxl_hook_up_pxb_registers() to cxl-host.c as it'll
On 6/7/22 01:49, Joel Stanley wrote:
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
From: Joe Komlodi
Using a register array will allow us to represent old-mode and new-mode
I2C registers by using the same underlying register array, instead of
adding an entire new set of variables to r
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron
---
v2: (Ben Widawsky)
- Correctly set a tighter write mask for the endpoint devices where this
register has a different use.
On Tue, 7 Jun 2022 at 11:12, Stafford Horne wrote:
>
> On Tue, Jun 07, 2022 at 10:42:08AM +0200, Arnd Bergmann wrote:
> > Goldfish is a very old platform, as far as I know only the kernel port is
> > new.
> > I don't know when qemu started shipping goldfish, but changing it now would
> > surely b
On Mon, May 16, 2022 at 11:25:51AM -0400, Igor Mammedov wrote:
> convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
> to a generic approach (i.e. make devices provide its own AML blobs
> like it is done with other ISA devices (ex. KBD))
>
> Signed-off-by: Igor Mammedov
could not
On 6/7/22 01:18, Joel Stanley wrote:
On Mon, 6 Jun 2022 at 15:09, Cédric Le Goater wrote:
From: Troy Lee
Instantiate the I2C buses in AST1030 model and create two slave device
for ast1030-evb.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Signed-off-by: Steven Lee
[ clg : - adapted to
Hello,
Sorry about that, I had the same issue with the patch for some reason, I think
it is the git send email that
messed up the patch (couldn’t directly send via smtp so I created a draft via
IMAP before sending).
Anyway, below is the patch, it was created on the master branch (commit
81c7ed41
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We do add COW child to the node. In future we are going to forbid
adding COW child to the node that doesn't support backing. So, fix it
here now.
Don't worry about setting bs->backing itself: it further commit we'll
s/it/in/
update the
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
test_parallel_perm_update() does two things that we are going to
restrict in the near future:
1. It updates bs->file field by hand. bs->file will be managed
automatically by generic code (together with bs->children list).
Let's bett
On Jun 7 13:06, Łukasz Gieryk wrote:
> On Fri, Jun 03, 2022 at 10:24:51PM +0200, Klaus Jensen wrote:
> > On Jun 1 15:28, Lukasz Maniak wrote:
> > > On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
> > > >
> > > > +stl_le_p(&n->bar.intms, 0);
> > > > +stl_le_p(&n->bar
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
bdrv_pass_through is used as filter, even all node variables has
corresponding names. We want to append it, so it should be
backing-child-based filter like mirror_top.
So, in test_update_perm_tree, first child should be DATA, as we don't
want
On Tue, 7 Jun 2022 11:56:17 +0100
Jonathan Cameron wrote:
> Without being able to write these registers, no interleaving is possible.
> More refined checks of HDM register state on commit to follow.
>
> Signed-off-by: Jonathan Cameron
+Cc Ben on current address.
Which reminds me - Ben, when y
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Make the informal rules formal. In further commit we'll add
corresponding assertions.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-common.h | 42
1 file changed, 42 insertions(+
On Fri, Jun 03, 2022 at 10:24:51PM +0200, Klaus Jensen wrote:
> On Jun 1 15:28, Lukasz Maniak wrote:
> > On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
> > >
> > > +stl_le_p(&n->bar.intms, 0);
> > > +stl_le_p(&n->bar.intmc, 0);
> > > +stl_le_p(&n->bar.cc, 0)
Hi,
> > I guess it could be helpful for the discussion when you can outine the
> > 'big picture' for tdx initialization. How does kvm accel setup look
> > like without TDX, and what additional actions are needed for TDX? What
> > ordering requirements and other constrains exist?
>
> To boot a
Hi,
So it seems the patch is messed up, I forked QEMU applied the patch to the
current master.
Here it is : https://gitlab.com/rwe-reds/qemu/-/tree/master
I rebuilt QEMU to check that everything builds and runs.
Sorry for the inconvenience, I don’t know why the patch gets corrupted…
Best regards
On Tue, Jun 07, 2022 at 11:43:08AM +0100, Peter Maydell wrote:
> So I don't have a strong view on whether these devices should
> be DEVICE_NATIVE_ENDIAN or DEVICE_LITTLE_ENDIAN (except that
> my impression is that a DEVICE_LITTLE_ENDIAN device on a
> big-endian system is a bit weird, because it mea
From: Klaus Jensen
The SRIOV series exposed an issued with how CC register writes are
handled and how CSTS is set in response to that. Specifically, after
applying the SRIOV series, the controller could end up in a state with
CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to
e
Richard Henderson writes:
> Use common_semi_cb to return results instead of calling
> set_swi_errno and common_semi_set_ret directly.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
On Tue, Jun 07, 2022 at 01:23:20PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The SRIOV series exposed an issued with how CC register writes are
> handled and how CSTS is set in response to that. Specifically, after
> applying the SRIOV series, the controller could end up in a state with
Am 03/06/2022 um 18:40 schrieb Kevin Wolf:
> Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
>> Introduce the job locking mechanism through the whole job API,
>> following the comments in job.h and requirements of job-monitor
>> (like the functions in job-qmp.c, assume lock i
Am 03/06/2022 um 18:17 schrieb Kevin Wolf:
> Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
>> In preparation to the job_lock/unlock usage, create _locked
>> duplicates of some functions, since they will be sometimes called with
>> job_mutex held (mostly within job.c),
>> and
Am 03/06/2022 um 18:00 schrieb Kevin Wolf:
> Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
>> Categorize the fields in struct Job to understand which ones
>> need to be protected by the job mutex and which don't.
>>
>> Signed-off-by: Emanuele Giuseppe Esposito
>
> I suppos
Am 03/06/2022 um 18:59 schrieb Kevin Wolf:
> Am 14.03.2022 um 14:37 hat Emanuele Giuseppe Esposito geschrieben:
>> From: Paolo Bonzini
>>
>> We want to make sure access of job->aio_context is always done
>> under either BQL or job_mutex. The problem is that using
>> aio_co_enter(job->aiocontext
On Mon, Jun 06, 2022 at 03:57:47PM +0100, Stefan Hajnoczi wrote:
> Hi,
> During Elena Afanasova's Outreachy project we discussed whether
> ioregionfd should be a custom struct file_operations (anon inode) or a
> userspace-provided file (socketpair, UNIX domain socket, etc).
>
Hello Stefan,
> Back
On 6/7/22 05:44, Frederic Barrat wrote:
On 07/06/2022 08:42, Cédric Le Goater wrote:
On 6/2/22 18:16, Frederic Barrat wrote:
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Actually what we chose is a primary child. Let's stress it in the code.
We are going to drop indirect pointer logic here in future. Actually
this commit simplifies the future work: we drop use of indirection in
the assertion now.
Signed-off
Richard Henderson writes:
> There were 3 copies of these flags. Place them in the
> file with gdb_do_syscall, with which they belong.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Hi Richard and Philippe,
I was finally able to test the patch.
As expected, the fences generated by TCG with your patch are the same
ones as in mine.
However, I was not able to reproduce the failure with the ahci-test on
my ARM system (2x 28-core Thunder X2, 4 threads per core). I ran 500
tests
Richard Henderson writes:
> We have two copies of these structures, and require them
> in semihosting/ going forward.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/gdbstub.h| 25 +
> target/m68k/m68k-semi.c | 30 +++---
> targe
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We are going to reimplement this behavior (clear bs->file / bs->backing
pointers automatically when child->bs is cleared) in a nicer way.
This reverts commit b0a9f6fed3d80de610dcd04a7e66f9f30a04174f.
This doesn’t really explain why it’s fi
On Tue, 7 Jun 2022 at 14:32, Elena wrote:
> On Mon, Jun 06, 2022 at 03:57:47PM +0100, Stefan Hajnoczi wrote:
> > The downside is it requires more code than general purpose I/O. In
> > addition to ->uring_cmd(), it's also worth implementing struct
> > file_operations read/write/poll so traditional
On Tue, Jun 7, 2022 at 2:12 PM Stafford Horne wrote:
> On Tue, Jun 07, 2022 at 11:43:08AM +0100, Peter Maydell wrote:
>
> However, in a followup mail from Laurent we see:
>
> https://lore.kernel.org/lkml/cb884368-0226-e913-80d2-62d2b7b2e...@vivier.eu/
>
> The reference document[1] doesn't defi
On 6/7/22 02:47, Peter Maydell wrote:
+void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
+{
+uint32_t vq_map = cpu->sme_vq.map;
+uint32_t vq_init = cpu->sme_vq.init;
+uint32_t vq_supported = cpu->sme_vq.supported;
+uint32_t vq;
+
+if (vq_map == 0) {
+if (!cpu_isar_f
On 6/7/22 02:58, Peter Maydell wrote:
@@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
+FIELD(TBFLAG_A64, SVL, 24, 4)
Given that both SVE and SME start with an 'S', maybe
On 6/7/22 03:03, Peter Maydell wrote:
On Thu, 2 Jun 2022 at 23:41, Richard Henderson
wrote:
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Signed-off-by: Richard Henderson
@@ -14814,7 +14814,12 @@ static void aarch64_tr_tran
On 6/7/22 17:03, Hanna Reitz wrote:
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
We are going to reimplement this behavior (clear bs->file / bs->backing
pointers automatically when child->bs is cleared) in a nicer way.
This reverts commit b0a9f6fed3d80de610dcd04a7e66f9f30a04174f.
Th
On 6/7/22 15:20, Emanuele Giuseppe Esposito wrote:
Am 03/06/2022 um 18:00 schrieb Kevin Wolf:
Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
Categorize the fields in struct Job to understand which ones
need to be protected by the job mutex and which don't.
Signed-off-by:
On Sat, 4 Jun 2022 at 05:09, Richard Henderson
wrote:
>
> The object here is to move 2500 lines out of helper.c. Yay!
>
Applied to target-arm.next, thanks.
-- PMM
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
bs->file and bs->backing are a kind of duplication of part of
bs->children. But very useful diplication, so let's not drop them at
all:)
We should manage bs->file and bs->backing in same place, where we
manage bs->children, to keep them in s
On 22/05/2022 19:17, Mark Cave-Ayland wrote:
This series came about when looking at improving the LASI PS2 device for
the HPPA machine: there were improvements that I was keen to make, but
was restricted because the PS2 device(s) weren't QOMified.
Trying to do everything in a single patchset wo
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Now the indirection is not actually used, we can safely reduce it to
simple pointer.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/snapshot.c | 39 +--
1 file changed, 17 insertions(+), 22 dele
On Tue, 7 Jun 2022 12:06:12 +0100
Jonathan Cameron wrote:
> On Tue, 7 Jun 2022 11:56:17 +0100
> Jonathan Cameron wrote:
>
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> >
> > Signed-off-by: Jona
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron
---
v3: Actually pass the parameter to the call...
v2: (Ben Widawsky)
- Correctly set a tighter write mask for the endpoint devi
On 22-06-07 17:07:47, Jonathan Cameron wrote:
> Without being able to write these registers, no interleaving is possible.
> More refined checks of HDM register state on commit to follow.
>
> Signed-off-by: Jonathan Cameron
> ---
> v3: Actually pass the parameter to the call...
> v2: (Ben Widawsky
On Tue, 7 Jun 2022 09:19:28 -0700
Ben Widawsky wrote:
> On 22-06-07 17:07:47, Jonathan Cameron wrote:
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> >
> > Signed-off-by: Jonathan Cameron
> > ---
On 6/7/22 01:59, Pavel Dovgalyuk wrote:
+{
+/*
+ * A generic CPU providing MIPS64 Cavium Octeon features.
+ * PRid is taken from Octeon 68xx CPUs
+ * FIXME: Eventually this should be replaced by a real CPU model.
+ */
You should just add the real cpu
On 22-06-07 17:37:02, Jonathan Cameron wrote:
> On Tue, 7 Jun 2022 09:19:28 -0700
> Ben Widawsky wrote:
>
> > On 22-06-07 17:07:47, Jonathan Cameron wrote:
> > > Without being able to write these registers, no interleaving is possible.
> > > More refined checks of HDM register state on commit to
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