Use the associated kvm ioctl operation to enable adapter event notification
and forwarding for devices when requested. This feature will be set up
with or without firmware assist based upon the 'forwarding_assist' setting.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 20 +
Let's use the reserved pool of simulated PCI groups to allow intercept
devices to have separate groups from interpreted devices as some group
values may be different. If we run out of simulated PCI groups, subsequent
intercept devices just get the default group.
Furthermore, if we encounter any PCI
In order to interface with the underlying host zPCI device, we need
to know it's function handle. Add a routine to grab this from the
vfio CLP capabilities chain.
Reviewed-by: Pierre Morel
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c | 83 ++--
If the ZPCI_OP ioctl reports that is is available and usable, then the
underlying KVM host will enable load/store intepretation for any guest
device without a SHM bit in the guest function handle. For a device that
will be using interpretation support, ensure the guest function handle
matches the
The maximum supported store block length might be different depending
on whether the instruction is interpretively executed (firmware-reported
maximum) or handled via userspace intercept (host kernel API maximum).
Choose the best available value during group creation.
Reviewed-by: Pierre Morel
Si
The zpcii-disable machine property can be used to force-disable the use
of zPCI interpretation facilities for a VM. By default, this setting
will be off for machine 7.1 and newer.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-kvm.c| 4 +++-
hw/s390x/s390-virtio-ccw.c
Lack of MSI-X support is not an issue for interpreted passthrough
devices, so let's let these in. This will allow, for example, ISM
devices to be passed through -- but only when interpretation is
available and being used.
Reviewed-by: Thomas Huth
Reviewed-by: Pierre Morel
Signed-off-by: Matthew
On Mon, Jun 6, 2022 at 12:29 PM Jag Raman wrote:
>
>
>
> > On Jun 6, 2022, at 2:32 PM, Alexander Duyck
> > wrote:
> >
> > On Tue, May 24, 2022 at 9:11 AM Jagannathan Raman
> > wrote:
> >>
> >> Forward remote device's interrupts to the guest
> >>
> >> Signed-off-by: Elena Ufimtseva
> >> Signed
On Tue, Jun 7, 2022 at 2:46 AM Kashyap Chamarthy wrote:
>
> This document is referred to from the GettingStartedDevelopers wiki
> which will be rSTified in a follow-up commit.
>
> Converted from Mediawiki to rST using:
>
> $> pandoc -f Mediawiki -t rst MailingLists.wiki
> -o mailing-li
Call the CHECK_NOSHUF macro multiple times: once in the
fGEN_TCG_PRED_LOAD() and again in fLOAD().
Before this commit, a packet with a store and a predicated
load with mem_noshuf that gets encoded like this:
{ P0 = cmp.eq(R17,#0x0)
memw(R18+#0x0) = R2
if (!P0.new) R3 = memw(R17+#0
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonState.
Test case added in tests/tcg/hexag
The test is in tests/tcg/multiarch/float_convd.c
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/float_convd.ref | 988 ++
1 file changed, 988 insertions(+)
create mode 100644 tests/tcg/hexagon/float_convd.ref
diff --git a/tests/tcg/hexagon/float_convd.ref
b/te
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/hexagon/imported/encode_pp.def
b/target/hexagon/imported/encode_pp.def
index 939c6fc55
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/hexagon/genptr.c | 147 +++
tests/tcg/hexagon/usr.
The increment used in :brev tests was causing unaligned addresses
Change the increment and the relevant expected values
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/load_unpack.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/hexagon/load_unpa
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.
Th
om/rth7680/qemu.git tags/pull-la-20220606
for you to fetch changes up to 34bb43b074906a7cd642ccf03e2b7bea63b53d95:
target/loongarch: 'make check-tcg' support (2022-06-06 18:14:13 +)
Initi
From: Song Gao
This patch gives an introduction to the LoongArch target.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-2-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 6
From: Song Gao
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id
From: Song Gao
This patch adds main translation routines and
basic functions for translation.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-4-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loong
From: Song Gao
This patch adds target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220606124333.2060567-3-yangxiaoj...@loongson.cn>
Signed-o
From: Song Gao
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-10-yangxiaoj...@loongson.cn>
Signed-off-by: Richard
From: Song Gao
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-12-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/helper.h| 9 +++
ta
From: Song Gao
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
M
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-19-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
docs/system/loongarch/loongson3.rst | 41 ++
MAINTAINERS
From: Song Gao
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-6-yangxiaoj...@
From: Song Gao
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-16-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
targ
From: Song Gao
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI,
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-20-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu-csr.h | 208 +
target/loongar
From: Song Gao
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-13-yangxiaoj...@loongson.cn>
Signed
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-21-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/internals.h | 2 +
target/loongarch/cpu.c | 1 +
target/loong
From: Song Gao
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-9-yangxiaoj...@loongson.cn>
Signed-off-by: Richard
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220606124333.2060567-18-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/meson.build | 19 +++
From: Song Gao
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-15-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Hender
From: Xiaojuan Yang
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-28-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
targe
From: Song Gao
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Rich
From: Song Gao
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-17-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
meson.build
From: Xiaojuan Yang
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-39-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
include/hw/pci-host/ls7a.h | 4 +
hw/loonga
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-22-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 26 ++
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-24-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.h | 2 +
target/loongarch/internals.h | 2 +
target/loo
From: Song Gao
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060
From: Xiaojuan Yang
This is a placeholder for missing ACPI, and will eventually be replaced.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Acked-by: Richard Henderson
Message-Id: <20220606124333.2060567-41-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
hw/loongarch/lo
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-23-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.h| 51 ++
ta
From: Xiaojuan Yang
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-29-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/helper.h
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-25-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.h| 4 ++
target/loongarch/internals.h | 6 +++
From: Xiaojuan Yang
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-30-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/helper.h
From: Xiaojuan Yang
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-27-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.h
From: Xiaojuan Yang
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only
From: Xiaojuan Yang
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-36-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
hw/loongarch/loongson3.c | 104 +
From: Xiaojuan Yang
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-32-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
include/hw/intc/loongarch_ipi.h | 5
From: Xiaojuan Yang
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-26-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/helper.h
From: Xiaojuan Yang
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-34-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
include/hw/intc/loongarch_pch_msi.h
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-37-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff -
From: Xiaojuan Yang
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-35-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
include/hw/intc/loongarch_extioi
From: Xiaojuan Yang
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Acked-by: Richar
From: Xiaojuan Yang
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-33-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
include/hw/intc/loongarch_pch_pi
From: Xiaojuan Yang
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <202
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-42-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
configs/targets/loongarch64-softmmu.mak | 1 +
target/loongarch/internals.h
From: Xiaojuan Yang
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20220606124333.2060567-40-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.h | 2 ++
hw/loongarch/loongson3.c | 61 ++
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
>
> From: Joe Komlodi
>
> This cleans up some of the field accessing, setting, and clearing
> bitwise operations, and wraps them in macros instead.
I don't really like this change, as it adds more project-specific
"jargon" to the models.
It's
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
>
> Add a RTC device on bus 15 and check that the ouput of the hwclock
spelling: output
> command matches the current year.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> tests/avocado/machine_aspeed.py | 8
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
>
> From: Joe Komlodi
>
> Using a register array will allow us to represent old-mode and new-mode
> I2C registers by using the same underlying register array, instead of
> adding an entire new set of variables to represent new mode.
The downsi
On Mon, 6 Jun 2022 at 15:09, Cédric Le Goater wrote:
>
> From: Troy Lee
>
> Instantiate the I2C buses in AST1030 model and create two slave device
> for ast1030-evb.
>
> Signed-off-by: Troy Lee
> Signed-off-by: Jamin Lin
> Signed-off-by: Steven Lee
> [ clg : - adapted to current ast1030 upstre
On Mon, 6 Jun 2022 at 15:08, Cédric Le Goater wrote:
>
> From: Joe Komlodi
>
> The Aspeed I2C controller is used across other SKUs that have different
> reserved bits for the ctrl_global_rsvd register.
I think rsvd stands for reserved? Lets spell out the full name in the
variable to keep it clea
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Acked-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220606124333.2060567-44-yangxiaoj...@loongson.cn>
Signed-off-by: Richard Henderson
---
configure | 1 +
1 file changed
On Mon, 6 Jun 2022 at 15:09, Cédric Le Goater wrote:
>
> Based on :
> https://lists.nongnu.org/archive/html/qemu-devel/2022-03/msg06017.html
Perhaps use the link to lore (which also includes the message id):
https://lore.kernel.org/qemu-devel/20220324100439.478317-2-troy_...@aspeedtech.com/
R
Update the test_arm_ast2600_debian test to
- the latest Debian kernel
- use the Rainier machine instead of Tacoma
Both of which contains support for more hardware and thus exercises more
of the hardware Qemu models.
Signed-off-by: Joel Stanley
---
tests/avocado/boot_linux_console.py | 12 +++
in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-la-20220606
for you to fetch changes up to 34bb43b074906a7cd642ccf03e2b7bea63b53d95:
target/loongarch: 'make check-tcg' support (2022-06-06 18:14:13 +)
Use the accessor rather than the raw structure member.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 20a0e4261a..a18a09a0c3
This is mostly code movement at this point, out of headers
and into op_helper.c and debug_helper.c. I have dropped all
the bits that change where route_to_el2 is computed -- it
remains in raise_exception alone.
The last patch has the tiniest of bug fixes, which probably
isn't even visible, becaus
Move the function to op_helper.c, near raise_exception.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 16 +---
target/arm/op_helper.c | 15 +++
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index b1334e0c42..5161cdf73d 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -44,9
Create helper_exception_advsimdfp_access to handle both
the routing and the syndrome contents, depending on the
eventual target EL and mode.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 1 +
target/arm/translate.h | 9 +
target/arm/op_helper.c | 32
Move arm_generate_debug_exceptions and its two subroutines,
{aa32,aa64}_generate_debug_exceptions into debug_helper.c,
and the one interface declaration to internals.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 91 ---
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 31 +++
target/arm/op_helper.c| 29 -
2 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index a18a09a0c
We no longer need this value during translation,
as it is now handled within the helpers.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ++
target/arm/translate.h | 2 --
target/arm/helper.c| 12 ++--
target/arm/translate-a64.c | 1 -
target/arm/t
With ARMv8, this field is always RES0.
With ARMv7, targeting EL2 and TA=0, it is always 0xA.
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 7 ---
target/arm/translate-a64.c | 3 ++-
target/arm/translate-vfp.c | 14 --
3 files changed, 18 insertions(+), 6 del
Move the computation from gen_swstep_exception into a helper.
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 1 +
target/arm/translate.h| 12 +++-
target/arm/debug_helper.c | 16
3 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/targe
This function now now only used in debug_helper.c, so there is
no reason to have a declaration in a header.
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 25 -
target/arm/debug_helper.c | 26 ++
2 files changed, 26 insertions(+),
Move the function to debug_helper.c, and the
declaration to internals.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 --
target/arm/internals.h| 1 +
target/arm/debug_helper.c | 12
3 files changed, 13 insertions(+), 1
This function is not required by any other translation file.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 8
target/arm/translate.c | 7 +++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 4a93cac6
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fc5eafaeeb..edb7d3f394 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1086
Rename to helper_exception_with_syndrome_el, to emphasize
that the target el is a parameter.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 +-
target/arm/translate.h | 6 +++---
target/arm/op_helper.c | 6 +++---
target/arm/translate.c | 6 +++---
4 files changed, 10 insertions
Create a function below gen_exception_insn that takes
the target_el as a TCGv_i32, replacing gen_exception_el.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/ta
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 4 ++--
target/arm/translate-a64.c| 30 +--
target/arm/translate-m-nocp.c | 16 +++---
target/arm/translate-mve.c| 4 ++--
target/arm/translate-vfp.c| 4 ++--
target/arm/translate.c
Create a new wrapper function that passes the default
exception target to gen_exception_insn_el.
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 1 +
target/arm/translate-a64.c| 15 ++-
target/arm/translate-m-nocp.c | 3 +--
target/arm/translate-mve.c|
Not a bug, because arm_is_el2_enabled tests for secure,
and SCR_EL3.EEL2 cannot be set for AArch32, however the
ordering of the tests looks odd. Mirror the structure
over in exception_target_el().
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 30 --
Create a new wrapper function that passes the default
exception target to gen_exception_el.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index edb7d3f394
On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote:
>
> On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis wrote:
> >
> > On Thu, May 26, 2022 at 8:12 PM Anup Patel wrote:
> > >
> > > We should write transformed instruction encoding of the trapped
> > > instruction in [m|h]tinst CSR at time of
Handle the debug vs current el exception test in one place.
Leave EXCP_BKPT alone, since that treats debug < current differently.
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 44 +--
1 file changed, 24 insertions(+), 20 deletions(-)
diff -
Split out a common helper function for gen_exception_el
and gen_exception_insn_el_v.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5a48937ede..fcb
This function is no longer used outside debug_helper.c.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 21 -
target/arm/debug_helper.c | 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/
With the helper we can use exception_target_el at runtime,
instead of default_exception_el at translate time.
While we're at it, remove the DisasContext parameter from
gen_exception, as it is no longer used.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 1 +
target/arm/op_helper
This function is no longer used. At the same time, remove
DisasContext.secure_routed_to_el3, as it in turn becomes unused.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 16
target/arm/translate-a64.c | 5 -
target/arm/translate.c | 5 -
3 files
We were using arm_is_secure and is_a64, which are
tests against the current EL, as opposed to
arm_el_is_aa64 and arm_is_secure_below_el3, which
can be applied to a different EL than current.
Consolidate the two tests.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 23 +---
On Mon, Jun 6, 2022 at 7:25 AM Alistair Francis wrote:
>
> On Thu, May 26, 2022 at 8:09 PM Anup Patel wrote:
> >
> > We should disable extensions in riscv_cpu_realize() if minimum required
> > priv spec version is not satisfied. This also ensures that machines with
> > priv spec v1.11 (or lower)
On Tue, Jun 7, 2022 at 8:31 AM Anup Patel wrote:
>
> On Mon, Jun 6, 2022 at 7:23 AM Alistair Francis wrote:
> >
> > On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, May 26, 2022 at 8:12 PM Anup Patel
> > > wrote:
> > > >
> > > > We should write transformed instr
在 2022/5/20 03:12, Eugenio Pérez 写道:
Introduce the control virtqueue support for vDPA shadow virtqueue. This
is needed for advanced networking features like multiqueue.
To demonstrate command handling, VIRTIO_NET_F_CTRL_MACADDR and
VIRTIO_NET_CTRL_MQ are implemented. If vDPA device is started
在 2022/5/20 03:12, Eugenio Pérez 写道:
The callback allows SVQ users to know the VirtQueue requests and
responses. QEMU can use this to synchronize virtio device model state,
allowing to migrate it with minimum changes to the migration code.
In the case of networking, this will be used to inspec
在 2022/5/20 03:12, Eugenio Pérez 写道:
This allows external vhost-net devices to modify the state of the
VirtIO device model once vhost-vdpa device has acknowledge the control
commands.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio-net.h | 4 ++
hw/net/virtio-net.c|
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