Re: [RFC PATCH 3/3] hw/openrisc: Add the OpenRISC virtual machine

On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote: > On Fri, Jun 03, 2022 at 09:05:09AM +0200, Geert Uytterhoeven wrote: > > Hi Stafford, > > > > On Thu, Jun 2, 2022 at 9:59 PM Stafford Horne wrote: > > > On Thu, Jun 02, 2022 at 09:08:52PM +0200, Geert Uytterhoeven wrote: > > > > On

Re: [RFC PATCH 3/3] hw/openrisc: Add the OpenRISC virtual machine

Hi folks, On Sun, Jun 05, 2022 at 04:32:13PM +0900, Stafford Horne wrote: > Why can't m68k switch to little-endian in qemu and the kernel? The m68k virt > platform is not that old, 1 year? Are there a lot of users that this would be > a big > problem? I also share this perspective. AFAICT, m68k

[PATCH 0/2] Fixes for ui/gtk-gl-area

The first patch fixes a GL context leak. The second patch fixes a black guest screen on Wayland with OpenGL accelerated QEMU graphics devices. This bug doesn't seem to be related to issues #910, #865, #671 or #298. Volker Rümelin (2):   ui/gtk-gl-area: implement GL context destruction   ui/gt

[PATCH 2/2] ui/gtk-gl-area: create the requested GL context version

Since about 2018 virglrenderer (commit fa835b0f88 "vrend: don't hardcode context version") tries to open the highest available GL context version. This is done by creating the known GL context versions from the highest to the lowest until (*create_gl_context) returns a context != NULL. This does n

[PATCH 1/2] ui/gtk-gl-area: implement GL context destruction

The counterpart function for gd_gl_area_create_context() is currently empty. Implement the gd_gl_area_destroy_context() function to avoid GL context leaks. Signed-off-by: Volker Rümelin --- ui/gtk-gl-area.c | 8 +++- ui/trace-events | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) di

Re: [RFC PATCH 1/3] target/openrisc: Add basic support for semihosting

On 6/4/22 17:57, Stafford Horne wrote: I am kind of leaning towards dropping the semi-hosting patches and only moving forward with the virt patches. The reason being that 1. we would not need to expand the architecture spec to support the qemu virt platform, and we would need to document the NOP

dbus-display-test is flakey

Hi Marc-André, dbus-display-test seems flakey. I'm occasionally seeing: ▶ 692/746 ERROR:../tests/qtest/dbus-display-test.c:68:test_dbus_display_vm: assertion failed (qemu_dbus_display1_vm_get_name(QEMU_DBUS_DISPLAY1_VM(vm)) == "dbus-test"): (NULL == "dbus-test") ERROR Examples: fedora rawhide x

[PATCH] qemu-iotests: Discard stderr when probing devices

./configure --enable-modules --enable-smartcard \ --target-list=x86_64-softmmu,s390x-softmmu make cd build QEMU_PROG=`pwd`/s390x-softmmu/qemu-system-s390x \ ../tests/check-block.sh qcow2 ... --- /home/crobinso/src/qemu/tests/qemu-iotests/127.out +++ /home/crobinso/src/qemu/build/tests/qemu-

[PATCH] hw/mips/boston: Initialize g_autofree pointers

Fixes compilation due to false positives with -Werror: In file included from /usr/include/glib-2.0/glib.h:114, from qemu/src/include/glib-compat.h:32, from qemu/src/include/qemu/osdep.h:144, from ../src/hw/mips/boston.c:20: In function ‘

[PATCH 1/2] target/arm: SCR_EL3 bits 4,5 are always res0

These bits do not depend on whether or not el1 supports aa32. Signed-off-by: Richard Henderson --- target/arm/helper.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..c262b00c3c 100644 --- a/target/arm/helper.

[PATCH 0/2] target/arm: SCR_EL3 RES0, RAO/WI tweaks

Adjust RW, fixing #1062, and adjusting bits [4:2]. r~ Richard Henderson (2): target/arm: SCR_EL3 bits 4,5 are always res0 target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] target/arm/cpu.h| 5 + target/arm/helper.c | 11 ++- 2 files changed, 11 insertions(+), 5 deleti

[PATCH 2/2] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]

Since DDI0487F.a, the RW bit is RAO/WI. When specifically targeting such a cpu, e.g. cortex-a76, it is legitimate to ignore the bit within the secure monitor. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062 Signed-off-by: Richard Henderson --- target/arm/cpu.h| 5 + target/

Re: [PATCH] hw/mips/boston: Initialize g_autofree pointers

On 6/5/22 08:19, Bernhard Beschow wrote: Fixes compilation due to false positives with -Werror: In file included from /usr/include/glib-2.0/glib.h:114, from qemu/src/include/glib-compat.h:32, from qemu/src/include/qemu/osdep.h:144, f

Re: [PATCH v5 2/3] target/riscv: Add stimecmp support

On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis wrote: > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote: > > > > stimecmp allows the supervisor mode to update stimecmp CSR directly > > to program the next timer interrupt. This CSR is part of the Sstc > > extension which was ratified recently

Re: [PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions

On Fri, May 13, 2022 at 9:55 PM ~eopxd wrote: > > According to v-spec, tail agnostic behavior can be either kept as > undisturbed or set elements' bits to all 1s. To distinguish the > difference of tail policies, QEMU should be able to simulate the tail > agnostic behavior as "set tail elements' b

Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Thu, May 26, 2022 at 8:12 PM Anup Patel wrote: > > We should write transformed instruction encoding of the trapped > instruction in [m|h]tinst CSR at time of taking trap as defined > by the RISC-V privileged specification v1.12. > > Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Al

Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On Mon, Jun 6, 2022 at 11:48 AM Alistair Francis wrote: > > On Thu, May 26, 2022 at 8:12 PM Anup Patel wrote: > > > > We should write transformed instruction encoding of the trapped > > instruction in [m|h]tinst CSR at time of taking trap as defined > > by the RISC-V privileged specification v1.1

Re: [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Thu, May 26, 2022 at 8:09 PM Anup Patel wrote: > > We should disable extensions in riscv_cpu_realize() if minimum required > priv spec version is not satisfied. This also ensures that machines with > priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter > extensions. > > Fixes

Re: [PATCH] target/riscv: Wake on VS-level external interrupts

On Wed, Jun 1, 2022 at 7:07 AM Andrew Bresticker wrote: > > Whether or not VSEIP is pending isn't reflected in env->mip and must > instead be determined from hstatus.vgein and hgeip. As a result a > CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as > specified in the privileged

Re: [PATCH] microvm: turn off io reservations for pcie root ports

On Fri, Jun 03, 2022 at 10:59:20AM +0200, Gerd Hoffmann wrote: > The pcie host bridge has no io window on microvm, > so io reservations will not work. > > Signed-off-by: Gerd Hoffmann > --- > hw/i386/microvm.c | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Sergio Lopez signature.

Re: [PATCH] target/riscv: Wake on VS-level external interrupts

On Wed, Jun 1, 2022 at 7:07 AM Andrew Bresticker wrote: > > Whether or not VSEIP is pending isn't reflected in env->mip and must > instead be determined from hstatus.vgein and hgeip. As a result a > CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as > specified in the privileged

Re: [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties

On Fri, Jun 3, 2022 at 9:36 PM Tsukasa OI wrote: > > Because many developers introduced new properties in various ways, the > entire riscv_cpu_properties block is getting too complex. > > This commit reorganizes riscv_cpu_properties for clarity on future. > > Signed-off-by: Tsukasa OI Reviewed-b

Re: [PATCH v3 2/3] target/riscv: Make CPU property names lowercase

On Fri, Jun 3, 2022 at 9:37 PM Tsukasa OI wrote: > > Many CPU properties for RISC-V are in lowercase except those with > "capitalized" (or CamelCase) names: > > - Counters > - Zifencei > - Zicsr > - Zfh > - Zfhmin > - Zve32f > - Zve64f > > This commit makes lowercase names primary bu

Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working

On Thu, Jun 2, 2022 at 11:55 PM Frédéric Pétrot wrote: > > Add an MXL_RV128 case in two switches so that no error is triggered when > using the -cpu x-rv128 option. > > Signed-off-by: Frédéric Pétrot > --- > target/riscv/debug.c | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Bin Meng

Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working

On Fri, Jun 3, 2022 at 1:55 AM Frédéric Pétrot wrote: > > Add an MXL_RV128 case in two switches so that no error is triggered when > using the -cpu x-rv128 option. > > Signed-off-by: Frédéric Pétrot Acked-by: Alistair Francis Alistair > --- > target/riscv/debug.c | 2 ++ > 1 file changed, 2

[PATCH qemu v19 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) di

[PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/risc

[PATCH qemu v19 03/16] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff

[PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v19 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8ac7fabb

[PATCH qemu v19 05/16] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PATCH qemu v19 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 11 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target

[PATCH qemu v19 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as tail eleme

[PATCH qemu v19 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v19 04/16] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PATCH qemu v19 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/r

[PATCH qemu v19 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff

[PATCH qemu v19 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions(-) di

[PATCH qemu v19 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PATCH qemu v19 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 13 +- target/riscv/internals.h

RE: [QEMU PATCH v2 0/6] Support ACPI NVDIMM Label Methods

Ping... Best Regards, Robert Hoo > -Original Message- > From: Robert Hoo > Sent: Monday, May 30, 2022 11:41 > To: imamm...@redhat.com; m...@redhat.com; > xiaoguangrong.e...@gmail.com; a...@anisinha.ca; Williams, Dan J > ; Liu, Jingqi > Cc: qemu-devel@nongnu.org; Hu, Robert > Subject: [

[PATCH qemu v19 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 20 2 files changed, 28 insertions(+), 4 deletions(-)