On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c
On 01/06/2022 09:04, Daniel Henrique Barboza wrote:
On 6/1/22 02:56, Cédric Le Goater wrote:
On 5/31/22 23:49, Daniel Henrique Barboza wrote:
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' poin
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Add support for writing and reading the device address register in old
register mode.
Signed-off-by: Klaus Jensen
---
hw/i2c/aspeed_i2c.c | 5 +++--
include/hw/i2c/aspeed_i2c.h | 8
2 files changed, 11 insertions(+),
On 6/2/22 00:05, Corey Minyard wrote:
On Wed, Jun 01, 2022 at 11:08:29PM +0200, Klaus Jensen wrote:
From: Klaus Jensen
Add an asynchronous version of i2c_send() that requires the slave to
explicitly acknowledge on the bus with i2c_ack().
The current master must use the new i2c_start_send_asyn
Le 02/06/2022 à 03:33, Richard Henderson a écrit :
Changes for v6:
* Use exact masks for registering trapcc and ftrapcc.
These insn overlap illegal scc and fscc operands,
so we need to be exact about the registration.
r~
Richard Henderson (17):
target/m68k: Raise the TRAPn exc
On Jun 2 09:30, Cédric Le Goater wrote:
> On 6/1/22 23:08, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Add support for writing and reading the device address register in old
> > register mode.
> >
> > Signed-off-by: Klaus Jensen
> > ---
> > hw/i2c/aspeed_i2c.c | 5 +++--
> >
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Add an example I2C device to demonstrate how a slave may master the bus
and send data asynchronously to another slave.
The device will echo whatever it is sent to the device identified by the
first byte received.
I think this is useful
On Jun 2 09:32, Cédric Le Goater wrote:
> On 6/2/22 00:05, Corey Minyard wrote:
> > On Wed, Jun 01, 2022 at 11:08:29PM +0200, Klaus Jensen wrote:
> > > From: Klaus Jensen
> > >
> > > Add an asynchronous version of i2c_send() that requires the slave to
> > > explicitly acknowledge on the bus with
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the Aspeed I2C
I think you can remove the RFC prefix.
controller as well as the necessary infrastructure in the i2c core to
support this.
v2 changes
~~
I finally got a
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. Ther
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec n
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports
On Thu, 2 Jun 2022 at 06:43, Sam Li wrote:
>
> Hi Stefan,
>
> Stefan Hajnoczi 于2022年6月1日周三 19:43写道：
> >
> > On Wed, 1 Jun 2022 at 06:47, Damien Le Moal
> > wrote:
> > >
> > > On 6/1/22 11:57, Sam Li wrote:
> > > > Hi Stefan,
> > > >
> > > > Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
> > > >
> > > >
On Jun 2 09:52, Cédric Le Goater wrote:
> On 6/1/22 23:08, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Hi all,
> >
> > This RFC series adds I2C "slave mode" support for the Aspeed I2C
>
> I think you can remove the RFC prefix.
>
> > controller as well as the necessary infrastructure in
"Liu, Changpeng" writes:
>> -Original Message-
>> From: Alex Bennée
>> Sent: Tuesday, May 31, 2022 10:46 PM
>> To: Liu, Changpeng
>> Cc: qemu-devel@nongnu.org
>> Subject: Re: [PATCH 1/2] hw/virtio/vhost-user: don't use uninitialized
>> variable
>>
>>
>> Changpeng Liu writes:
>>
>
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
Hi,
This v2 is considerable different from the first version due to the
review provided by Mark Cave-Ayland.
We're now preserving all PnvPHB3/4/5 implementations already in place.
The PnvPHB device now acts as a base/proxy of the existing PHB
On 01/06/2022 15:21, Philippe Mathieu-Daudé via wrote:
+Mark for commit ef96e3ae96.
On 1/6/22 14:53, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian h
>> That's exactly my point:
>>
>> sigpif and pfmfi are actually vsie features. I'd have expected that
>> zpcii would be a vsie feature as well.
>>
>> If interpretation is really more an implementation detail in the
>> hypervisor to implement zpci, than an actual guest feature (meaning, the
>> guest
Hi all,
just a reminder: Please note that gitlab.com introduced limits on the
available CI minutes since yesterday [1]. So if you are using gitlab for
storing your QEMU branches, please make sure that you update your branches
to the very latest version of the qemu-project's master branch -
Colin's address bounces - seems like he left Intel. Thus remove
the entry from MAINTAINERS now.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 00dc4a8ecb..dbf328cc94 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -488,
On 5/24/2022 3:56 PM, Gerd Hoffmann wrote:
Hi,
+static void tdvf_hob_add_mmio_resources(TdvfHob *hob)
+{
+MachineState *ms = MACHINE(qdev_get_machine());
+X86MachineState *x86ms = X86_MACHINE(ms);
+PCIHostState *pci_host;
+uint64_t start, end;
+uint64_t mcfg_base, mcfg_si
On 6/1/22 15:59, David Hildenbrand wrote:
On 01.06.22 04:17, zhenwei pi wrote:
On 5/31/22 12:08, Jue Wang wrote:
On Mon, May 30, 2022 at 8:49 AM Peter Xu wrote:
On Mon, May 30, 2022 at 07:33:35PM +0800, zhenwei pi wrote:
A VM uses RAM of 2M huge page. Once a MCE(@HVAy in [HVAx,HVAz)) occurs
On 02.06.22 11:28, zhenwei pi wrote:
> On 6/1/22 15:59, David Hildenbrand wrote:
>> On 01.06.22 04:17, zhenwei pi wrote:
>>> On 5/31/22 12:08, Jue Wang wrote:
On Mon, May 30, 2022 at 8:49 AM Peter Xu wrote:
>
> On Mon, May 30, 2022 at 07:33:35PM +0800, zhenwei pi wrote:
>> A VM us
Hi, Thomas,
Thanks for your mail. I once submitted the below patch to qemu-devel@nongnu.org
but it has not been merged. I have pasted it as below and attached it in loop.
Thanks.
>From 2257272c08291006bad5e9a44f48e7365f330640 Mon Sep 17 00:00:00 2001
From: Wenchao Wang
On 02/06/2022 11.41, Wang, Wenchao wrote:
Hi, Thomas,
Thanks for your mail. I once submitted the below patch to qemu-devel@nongnu.org
but it has not been merged. I have pasted it as below and attached it in loop.
Thanks.
Ah, great, so there is already a patch - then please disregard mine. An
Hi, Thomas,
That's great. Thanks for your help.
Best Regards,
Wenchao
-Original Message-
From: Thomas Huth
Sent: Thursday, June 2, 2022 17:51
To: Wang, Wenchao ; qemu-devel@nongnu.org
Cc: haxm-team
Subject: Re: [PATCH] Remove Colin Xu's mail address from QEMU's MAINTAINERS
files
On
On Wed, Jun 01, 2022 at 02:11:42PM +0200, Gupta, Pankaj wrote:
>
> > > > Introduce a new memfd_create() flag indicating the content of the
> > > > created memfd is inaccessible from userspace through ordinary MMU
> > > > access (e.g., read/write/mmap). However, the file content can be
> > > > acce
Stefan Hajnoczi 于2022年6月2日周四 16:05写道：
>
> On Thu, 2 Jun 2022 at 06:43, Sam Li wrote:
> >
> > Hi Stefan,
> >
> > Stefan Hajnoczi 于2022年6月1日周三 19:43写道：
> > >
> > > On Wed, 1 Jun 2022 at 06:47, Damien Le Moal
> > > wrote:
> > > >
> > > > On 6/1/22 11:57, Sam Li wrote:
> > > > > Hi Stefan,
> > > >
On 5/30/22 13:39, Denis V. Lunev wrote:
This patch makes in_flight field 'unsigned' for BDRVNBDState and
MirrorBlockJob. This matches the definition of this field on BDS
and is generically correct - we should never get negative value here.
Signed-off-by: Denis V. Lunev
CC: John Snow
CC: Vladimir
On 5/30/22 13:39, Denis V. Lunev wrote:
At the moment there are 2 sources of lengthy operations if configured:
* open connection, which could retry inside and
* reconnect of already opened connection
These operations could be quite lengthy and cumbersome to catch thus
it would be quite natural to
On 30/5/22 12:39, Denis V. Lunev wrote:
This patch makes in_flight field 'unsigned' for BDRVNBDState and
MirrorBlockJob. This matches the definition of this field on BDS
and is generically correct - we should never get negative value here.
Signed-off-by: Denis V. Lunev
CC: John Snow
CC: Vladim
Cc'ing qemu-stable@
Thank you Daniel / Thomas / Alex!
On 1/6/22 20:05, Alex Bennée wrote:
From: Daniel P. Berrangé
To preserve CI shared runner credits we don't want to run
pipelines on every push.
This sets up the config so that pipelines are never created
for contributors by default. To ov
Hi Stafford,
On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
>
> This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
> platform allows for a convenient CI platform for toolchain, software
> ports and the OpenRISC linux kernel port.
>
> Much of this has been sourced from the
Hi, Thomas.
On 6/1/22 04:27, Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrang
From: Richard Henderson
Zero selects all cpu features in disas/m68k.c,
which is really what we want -- not limited to 68040.
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Message-Id: <20220430170225.326447-2-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
targe
From: Richard Henderson
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-5-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
linux-user/m68k/cpu_loop.c | 4
1
r-7.1-pull-request
for you to fetch changes up to 36a0ab595f4e24b987e67faa52d4b174f67144b6:
target/m68k: Mark helper_raise_exception as noreturn (2022-06-02 09:35:03
+0200)
m68k pull request 20220602
- Fixes and cleanup
- Implement TR
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Message-Id: <20220430170225.326447-3-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/m68k/translate.c b/targe
From: Richard Henderson
Replace an if ladder with a switch for clarity.
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-3-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/op_helper
From: Richard Henderson
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Zero Div (and others)
is supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
While the N, Z and V flags are documented to be undefine on DIV0,
From: Richard Henderson
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-2-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
From: Richard Henderson
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), CHK, CHK2 (and others)
are supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
Create a raise_exception_format2 function to centralize recordin
From: Richard Henderson
According to the M68040 Users Manual, section 8.4.1, Four word
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <2022060201
From: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-13-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate
From: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-14-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/translate.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
From: Richard Henderson
The only value this variable holds is now env->pc.
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-6-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/op_hel
From: Richard Henderson
Errors are not all negative numbers: use is_error.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-16-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
linux-user/strace.c | 2 +-
1 file changed, 1
From: Richard Henderson
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-15-richard.hender...@linaro.org>
Signed-off-by
From: Richard Henderson
Also mark raise_exception_ra and raise_exception, lest we
generate a warning about helper_raise_exception returning.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-18-richard.hender...
From: Richard Henderson
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to record the trapping
pc in env->
From: Richard Henderson
TPF stands for "trap false", and is a long-form nop for ColdFire.
Re-use the immediate consumption code from trapcc; the insn will
already expand to a nop because of the TCG_COND_NEVER test
within do_trapcc.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Hi, Greg.
On 6/1/22 05:38, Greg Kurz wrote:
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/q
From: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-11-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
target/m68k/cpu.h | 2 ++
linux-user
From: Richard Henderson
Unlike i386, m68k get_thread_area has no arguments.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <20220602013401.303699-17-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier
---
linux-user/strace.list | 5 +
1 file changed, 5 i
Hi, Cédric.
On 6/1/22 04:44, Cédric Le Goater wrote:
On 6/1/22 09:27, Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-projec
From: Richard Henderson
Add parenthesis around & vs &&.
Remove assignment to sr in function call argument -- note that
sr is unused after the call, so the assignment was never needed,
only the result of the & expression.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Hi, Daniel.
On 6/1/22 06:59, Daniel Henrique Barboza wrote:
On 6/1/22 06:25, Thomas Huth wrote:
On 01/06/2022 10.38, Greg Kurz wrote:
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take adv
Hi, Matheus.
On 5/31/22 15:04, Matheus K. Ferst wrote:
On 31/05/2022 14:27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P.
On Thu, 2 Jun 2022 09:10:57 -0300
Murilo Opsfelder Araújo wrote:
> Hi, Greg.
>
> On 6/1/22 05:38, Greg Kurz wrote:
> > On Wed, 1 Jun 2022 09:27:31 +0200
> > Thomas Huth wrote:
> >
> >> On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
> >>> Update max alias to power10 so users can take advant
From: Christoph Muellner
This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we
On 6/2/22 10:21, Klaus Jensen wrote:
On Jun 2 09:52, Cédric Le Goater wrote:
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the Aspeed I2C
I think you can remove the RFC prefix.
controller as well as the necessary infras
Coverity is not thrilled about the multiply operations being done in
ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "sextract32(a, 4 * i, 4) *
sextract32(b, 4 * i, 4)" with type "int" (32 bits
On Tue, 31 May 2022 14:40:15 +0200
Julia Suvorova wrote:
> On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
> >
> >
> >
> > On Fri, 27 May 2022, Julia Suvorova wrote:
> >
> > > In order to use the increased number of cpus, we need to bring smbios
> > > tables in line with the SMBIOS 3.0 specif
Hi Klaus,
On 6/2/2022 6:50 AM, Cédric Le Goater wrote:
On 6/2/22 10:21, Klaus Jensen wrote:
On Jun 2 09:52, Cédric Le Goater wrote:
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the Aspeed I2C
I think you can remove the
Am Donnerstag, 2. Juni 2022, 15:40:17 CEST schrieb Christoph Muellner:
> From: Christoph Muellner
>
> This patch adds support for the Zawrs ISA extension.
> Given the current (incomplete) implementation of reservation sets
> there seems to be no way to provide a full emulation of the WRS
> instru
On Thu, 2 Jun 2022 16:31:25 +0200
Igor Mammedov wrote:
> On Tue, 31 May 2022 14:40:15 +0200
> Julia Suvorova wrote:
>
> > On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
> > >
> > >
> > >
> > > On Fri, 27 May 2022, Julia Suvorova wrote:
> > >
> > > > In order to use the increased number
com/vivier/qemu-m68k.git tags/m68k-for-7.1-pull-request
for you to fetch changes up to 36a0ab595f4e24b987e67faa52d4b174f67144b6:
target/m68k: Mark helper_raise_exception as noreturn (2022-06-02 09:35:03
+0200)
m68k pull reques
On Fri, 27 May 2022 18:56:48 +0200
Julia Suvorova wrote:
> Introduce the 64-bit entry point. Since we no longer have a total
> number of structures, stop checking for the new ones at the EOF
> structure (type 127).
>
> Signed-off-by: Julia Suvorova
> ---
> tests/qtest/bios-tables-test.c | 101
On 6/2/22 07:14, Daniel Henrique Barboza wrote:
Coverity is not thrilled about the multiply operations being done in
ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "sextract32(a, 4 * i, 4)
On 6/2/22 06:40, Christoph Muellner wrote:
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc
b/target/riscv/insn_trans/trans_rvzawrs.c.inc
new file mode 100644
index 00..38b71d0085
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
Typo in the filename -- s/rvz/rz/.
The masking in tcg_out_shl was incorrect, producing an
illegal instruction, rather than merely unspecified results
for the out-of-range shift.
Tested-by: Joel Stanley
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1051
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc |
s/pull-tcg-20220602
for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:
tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46
-0700)
Add tcg_gen_mov_ptr.
Fix tcg/i386 encoding of avx512 vpsra
Add an interface to perform moves between TCGv_ptr.
Reviewed-by: Matheus Ferst
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index b09b8b4a05..209e168305 100644
--- a/include/tcg/tcg
We wanted the VPSRAQ variant with the scalar vector shift operand,
not the variant with an immediate operand.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1022
Fixes: 47b331b2a8da ("tcg/i386: Implement avx512 scalar shift")
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.in
On Fri, 27 May 2022 18:56:50 +0200
Julia Suvorova wrote:
> The new test is run with a large number of cpus and checks if the
> core_count field in smbios_cpu_test (structure type 4) is correct.
>
> Choose q35 as it allows to run with -smp > 255.
>
> Signed-off-by: Julia Suvorova
> ---
> tests
On 5/27/22 10:27, Stafford Horne wrote:
+void do_or1k_semihosting(CPUOpenRISCState *env, uint32_t k);
...
+DEF_HELPER_FLAGS_2(nop, 0, void, env, i32)
Just call the helper "semihosting" and be done with it.
And the helper wants an ifdef for system mode.
@@ -10,6 +10,7 @@ openrisc_ss.add(file
On 5/27/22 10:27, Stafford Horne wrote:
These will be shared with the virt platform.
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 127 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++-
On 6/2/22 16:29, Jae Hyun Yoo wrote:
Hi Klaus,
On 6/2/2022 6:50 AM, Cédric Le Goater wrote:
On 6/2/22 10:21, Klaus Jensen wrote:
On Jun 2 09:52, Cédric Le Goater wrote:
On 6/1/22 23:08, Klaus Jensen wrote:
From: Klaus Jensen
Hi all,
This RFC series adds I2C "slave mode" support for the A
On 02/06/2022 11:14, Daniel Henrique Barboza wrote:
Coverity is not thrilled about the multiply operations being done in
ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "sextract32(a, 4 * i
On 6/2/22 04:42, Joel Stanley wrote:
Hi Stafford,
On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.
Much of
On Thu, Jun 2, 2022 at 5:07 PM Richard Henderson
wrote:
>
> On 6/2/22 06:40, Christoph Muellner wrote:
> > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > new file mode 100644
> > index 00..38b71d0085
> > --- /dev/null
> > +++
Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.
Signed-off-by: Frédéric Pétrot
---
target/riscv/debug.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 2f2a51c732..fc6e13222f 100644
--
On Thu, 2 Jun 2022 at 17:07, Richard Henderson
wrote:
>
> On 6/2/22 06:40, Christoph Muellner wrote:
> > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > new file mode 100644
> > index 00..38b71d0085
> > --- /dev/null
> > +++ b
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
Hi,
This v2 is considerable different from the first version due to the
review provided by Mark Cave-Ayland.
We're now preserving all PnvPHB3/4/5 implementations already in place.
The PnvPHB device now acts as a base/proxy of the existing P
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' po
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
s/TYPE_PARENT/TYPE_DEVICE
Fred
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via t
I'm trying to set up one guest as a SMB file server, and connect to it from
several other guests. I tried using -device socket listen/connect, but it
appears that only one client can connect at a time to each listener. I don't
want to use mcast for security reasons, ie the other guests shouldn't
On 24/05/2022 17.40, Alex Bennée wrote:
checkpatch.pl warns that non-plain asserts should be avoided so
convert the check to a plain g_assert.
Signed-off-by: Alex Bennée
---
tests/qtest/vhost-user-test.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/qtest/vhost-
Typo. I meant that I've tried -netdev socket, not -device socket
On Thu, Jun 2, 2022, at 10:25 AM, Anders Pitman wrote:
> I'm trying to set up one guest as a SMB file server, and connect to it from
> several other guests. I tried using -device socket listen/connect, but it
> appears that only on
On Thu, Jun 2, 2022 at 8:50 PM Igor Mammedov wrote:
>
> On Fri, 27 May 2022 18:56:50 +0200
> Julia Suvorova wrote:
>
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is correct.
> >
> > Choose q35 as it allows to run
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
To enable user creatable PnvPHB devices for powernv9 we'll revert the
powernv9 related changes made in 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices".
This change alone isn't enough to enable user creatable devices for powernv1
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220602
for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:
tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46
-0700)
Add tcg_gen_mo
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access for node 0 when
computing the PIR. Everyt
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
l
On 26/05/2022 13.07, Daniel P. Berrangé wrote:
This converts the main build and container jobs to use the
base job rules, defining the following new variables
- QEMU_JOB_SKIPPED - jobs that are known to be currently
broken and should not be run. Can still be manually
launched if desire
On Wed, Jun 1, 2022, 6:06 AM Paolo Bonzini wrote:
> On 5/27/22 16:27, John Snow wrote:
> > Paolo: I assume this falls under your jurisdiction...ish, unless Cleber
> > (avocado) or Alex (tests more broadly) have any specific inputs.
> >
> > I'm fine with waiting for reviews, but don't know whose b
On Wed, Jun 1, 2022, 3:29 AM Thomas Huth wrote:
> On 31/05/2022 20.28, John Snow wrote:
> > On Mon, May 30, 2022 at 3:33 AM Thomas Huth wrote:
> >>
> >> On 26/05/2022 02.09, John Snow wrote:
> >>> This is needed to be able to add a venv-building step to 'make check';
> >>> the clang-user job in
On 6/2/22 14:06, Frederic Barrat wrote:
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID regi
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