On 5/25/22 18:06, Daniel P. Berrangé wrote:
On Wed, Mar 16, 2022 at 10:54:55AM +0100, Damien Hedde wrote:
+def raw_load(file: TextIO) -> List[QMPMessage]:
+"""parse a raw qmp command file.
+
+JSON formatted commands can expand on several lines but must
+be separated by an end-of
On 26/05/2022 02.09, John Snow wrote:
This is needed to be able to add a venv-building step to 'make check';
the clang-user job in particular needs this to be able to run
check-unit.
Signed-off-by: John Snow
---
tests/docker/dockerfiles/debian10.docker | 1 +
1 file changed, 1 insertion(+)
On 27/05/2022 17.35, Alex Bennée wrote:
From: Paolo Bonzini
While container-based cross compilers are not supported, this already makes
it possible to build s390-ccw on any machine that has s390x GCC and binutils
installed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Message-
On 27.05.22 08:32, zhenwei pi wrote:
> On 5/27/22 02:37, Peter Xu wrote:
>> On Wed, May 25, 2022 at 01:16:34PM -0700, Jue Wang wrote:
>>> The hypervisor _must_ emulate poisons identified in guest physical
>>> address space (could be transported from the source VM), this is to
>>> prevent silent dat
> +
> struct virtio_balloon {
> struct virtio_device *vdev;
> struct virtqueue *inflate_vq, *deflate_vq, *stats_vq, *free_page_vq;
> @@ -126,6 +133,16 @@ struct virtio_balloon {
> /* Free page reporting device */
> struct virtqueue *reporting_vq;
> struct page_repor
Hi
On Sat, May 28, 2022 at 7:23 PM Stefan Berger wrote:
>
>
>
> On 5/27/22 15:31, Stefan Berger wrote:
> >
> >
> > On 5/27/22 15:24, Marc-André Lureau wrote:
> >> Hi
> >>
> >> On Fri, May 27, 2022 at 7:36 PM Stefan Berger
> >> wrote:
> >>>
> >>> This series of patches resolves an issue with a TP
Hi
On Mon, May 30, 2022 at 8:32 AM Thomas Huth wrote:
>
> On 25/05/2022 19.34, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
>
> Could you please provide a patch description? (What's the benefit of this
> patch? Why is testlog.txt not sufficient?)
It allows the gitlab UI to sho
On 27/05/2022 17.35, Alex Bennée wrote:
From: Daniel P. Berrangé
This folds the Cirrus job rules into the base job
template, introducing two new variables
- QEMU_JOB_CIRRUS - identifies the job as making
use of Cirrus CI via cirrus-run
- QEMU_JOB_OPTIONAL - identifies the job as on
On 27/05/2022 17.35, Alex Bennée wrote:
From: Daniel P. Berrangé
Currently job rules are spread across the various templates
and jobs, making it hard to understand exactly what runs in
what scenario. This leads to inconsistency in the rules and
increased maint burden.
The intent is that we int
On 25.05.22 01:32, zhenwei pi wrote:
>
>
> On 5/25/22 03:35, Sean Christopherson wrote:
>> On Fri, May 20, 2022, zhenwei pi wrote:
>>> @@ -59,6 +60,12 @@ enum virtio_balloon_config_read {
>>> VIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,
>>> };
>>>
>>> +/* the request body to commucate with hos
On 27/05/2022 17.36, Alex Bennée wrote:
From: Daniel P. Berrangé
This folds the static checks into using the base job
template rules, introducing one new variable
- QEMU_JOB_ONLY_FORKS - a job that should never run
on an upstream pipeline. The information it reports
is only applicabl
On 5/27/22 17:35, Alex Bennée wrote:
configure | 49 -
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/configure b/configure
index b8c21e096c..82c2ddc79a 100755
--- a/configure
+++ b/configure
@@ -2187,6 +2187,30 @@ fi
QEMU_G
Gentle ping :-)
@Kevin, can this patch go with your tree?
Ilya already reviewed it.
Thanks,
Stefano
On Tue, May 17, 2022 at 09:10:12AM +0200, Stefano Garzarella wrote:
If the namespace does not exist, rbd_create() fails with -ENOENT and
QEMU reports a generic "error rbd create: No such file or
On 5/27/22 17:35, Alex Bennée wrote:
QEMU_GA_MSI_MINGW_BIN_PATH="$($pkg_config --variable=prefix glib-2.0)/bin"
+###
+# cross-compiled firmware targets
+
# Set up build tree symlinks that point back into the source tree
# (these can be both files an
On Wed, May 25 2022, Eric Farman wrote:
> Commit 7a523d96a0 ("virtio-ccw: move vhost_ccw_scsi to a separate file")
> introduced a new file hw/s390x/vhost-scsi-ccw.c, which received a
> couple comments [1][2] to update MAINTAINERS that were missed.
>
> Fix that by making the vhost CCW entries a wi
On 27/05/2022 17.36, Alex Bennée wrote:
From: Daniel P. Berrangé
This converts the main build and container jobs to use the
base job rules, defining the following new variables
- QEMU_JOB_SKIPPED - jobs that are known to be currently
broken and should not be run. Can still be manually
On 27/05/2022 17.36, Alex Bennée wrote:
From: Daniel P. Berrangé
To preserve CI shared runner credits we don't want to run
pipelines on every push.
This sets up the config so that pipelines are never created
for contributors by default. To override this the QEMU_CI
variable can be set to a non
On 27/05/2022 17.35, Alex Bennée wrote:
From: Marc-André Lureau
Please add the patch description that Marc-André provided here:
https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg05797.html
Signed-off-by: Marc-André Lureau
Message-Id: <20220525173411.612224-1-marcandre.lur...@redhat.
On Wed, 25 May 2022 at 17:19, Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> Fix when building HVF on macOS Aarch64:
>
Applied to target-arm.next, thanks.
-- PMM
On 5/27/22 00:43, Michael S. Tsirkin wrote:
Recent changes to pcie_host corrected size of its internal region to
match what it expects - only the low 28 bits are ever decoded. Previous
code just ignored bit 29 (if size was 1 << 29) in the address which does
not make much sense. We are now assert
[ resend with a reply-all ]
On 5/27/22 00:43, Michael S. Tsirkin wrote:
Recent changes to pcie_host corrected size of its internal region to
match what it expects - only the low 28 bits are ever decoded. Previous
code just ignored bit 29 (if size was 1 << 29) in the address which does
not make m
On 26/05/2022 17.54, BALATON Zoltan wrote:
Hello,
On Thu, 26 May 2022, Daniel Henrique Barboza wrote:
Hi,
This patch broke the boot of the sam460ex ppc machine:
qemu-system-ppc -M sam460ex -kernel
./buildroot/qemu_ppc_sam460ex-latest/vmlinux \
-device virtio-net-pci,netdev=net0 -netdev user
On 27.05.22 12:11, Gautam Agrawal wrote:
> Add a test to check for overflow conditions in s390x.
> This patch is based on the following patches :
> * https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
> * https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
>
> Signed-off-by:
On 5/25/22 21:20, Mark Cave-Ayland wrote:
On 25/05/2022 12:45, Peter Maydell wrote:
On Wed, 25 May 2022 at 10:51, Damien Hedde
wrote:
On 5/24/22 19:44, Mark Cave-Ayland wrote:
Sorry for coming late into this series, however one of the things I've
been thinking about a lot recently is that
Hi Alex,
I don't know this code well enough to be certain, but is a flag
sufficient here given the intent, or should it be using a more
thread-safe method like a rwlock or condition variable?
Maybe the device state structure is already protected at some level
with a mutex - just not obvious to
On 5/30/22 11:42, Thomas Huth wrote:
On 26/05/2022 17.54, BALATON Zoltan wrote:
Hello,
On Thu, 26 May 2022, Daniel Henrique Barboza wrote:
Hi,
This patch broke the boot of the sam460ex ppc machine:
qemu-system-ppc -M sam460ex -kernel
./buildroot/qemu_ppc_sam460ex-latest/vmlinux \
-device vi
On Fri, 27 May 2022 06:18:43 +0800
maobibo wrote:
> On 5/26/22 16:42, Igor Mammedov wrote:
> > On Tue, 24 May 2022 16:18:01 +0800
> > Xiaojuan Yang wrote:
> >
> > commit message needs pointers to specification,
> > + in patch comments that point to specific chapters
> > within the spec for newl
On Mon, 30 May 2022 at 10:50, Damien Hedde wrote:
> TYPE_SYS_BUS_DEVICE also comes with reset support.
> If a device is on not on any bus it is not reached by the root sysbus
> reset which propagates to every device (and other sub-buses).
> Even if we move all the mmio/sysbus-irq logic into TYPE_D
Hi!
On 30/05/2022 11.50, David Hildenbrand wrote:
On 27.05.22 12:11, Gautam Agrawal wrote:
Add a test to check for overflow conditions in s390x.
This patch is based on the following patches :
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
* https://git.qemu.org/?p=qemu.git;a=c
At the moment there are 2 sources of lengthy operations if configured:
* open connection, which could retry inside and
* reconnect of already opened connection
These operations could be quite lengthy and cumbersome to catch thus
it would be quite natural to add trace points for them.
This patch is
This patch makes in_flight field 'unsigned' for BDRVNBDState and
MirrorBlockJob. This matches the definition of this field on BDS
and is generically correct - we should never get negative value here.
Signed-off-by: Denis V. Lunev
CC: John Snow
CC: Vladimir Sementsov-Ogievskiy
CC: Kevin Wolf
CC
On 29/5/22 21:06, Bernhard Beschow wrote:
Am 28. Mai 2022 09:19:29 UTC schrieb Mark Cave-Ayland
:
Use the new piix4_pm_init() instance init function to initialise 2 separate qdev
gpios for the SCI and SMI IRQs.
Signed-off-by: Mark Cave-Ayland
---
hw/acpi/piix4.c | 9 +
1 file changed,
I have gotten past this issue and I was able to successfully build
bits using the latest gcc v9.4.0 available on ubuntu 20.04.2. I have
also tested the generated iso and it seems to work fine.
I am going to clean up my changes and send PRs. Some of the changes
are bug fixes to existing code as well
On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
>
> Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> This flag should be set/checked prior to calling a device's MemoryRegion
> handlers, and set when device code initiates DMA. The purpose of this
> flag is to preve
Am 17.05.2022 um 09:10 hat Stefano Garzarella geschrieben:
> If the namespace does not exist, rbd_create() fails with -ENOENT and
> QEMU reports a generic "error rbd create: No such file or directory":
>
> $ qemu-img create rbd:rbd/namespace/image 1M
> Formatting 'rbd:rbd/namespace/image',
On 30/5/22 06:56, Ani Sinha wrote:
On Sat, May 28, 2022 at 2:49 PM Mark Cave-Ayland
wrote:
This is in preparation for conversion to a qdev property.
Signed-off-by: Mark Cave-Ayland
other than the comment below,
Reviewed-by: Ani Sinha
---
hw/acpi/piix4.c | 2 +-
1 file changed, 1 inse
On Mon, 30 May 2022 at 06:09, Sam Li wrote:
>
> Hi everyone,
> I'm Sam Li, working on the Outreachy project which is to add zoned
> device support to QEMU's virtio-blk emulation.
>
> For the first goal, adding QEMU block layer APIs resembling Linux ZBD
> ioctls, I think the naive approach would be
From: Mark Cave-Ayland
This logic can be included as part of piix4_pm_realize() and does not need to
be handled externally.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20220528091934.15520-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-
On Mon, 30 May 2022 at 06:38, Damien Le Moal wrote:
> On 2022/05/30 14:09, Sam Li wrote:
> Once you have an API working and the ability to execute all zone operations
> from
> a guest, you can then work on adding the more difficult bits: supporting the
> zone append operation will require trackin
On 2022/05/30 20:22, Stefan Hajnoczi wrote:
> On Mon, 30 May 2022 at 06:38, Damien Le Moal wrote:
>> On 2022/05/30 14:09, Sam Li wrote:
>> Once you have an API working and the ability to execute all zone operations
>> from
>> a guest, you can then work on adding the more difficult bits: supportin
From: Mark Cave-Ayland
This is in preparation for conversion to a qdev property.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20220528091934.15520-3-mark.cave-ayl...@ilande.co.uk>
[PMD: Change simm_enabled from int to bool, suggested
From: Philippe Mathieu-Daudé
This series moves the outstanding logic from piix4_pm_init() into
the relevant instance init() and realize() functions, changes the
IRQs to use qdev gpios, and then finally removes the now-unused
piix4_pm_initfn() function.
v2:
- Addressed Ani & Bernhard review comme
From: Mark Cave-Ayland
Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM
device can be instantiated directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-11-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Ph
From: Mark Cave-Ayland
This allows the QOM types in hw/acpi/piix4.c to be used elsewhere by simply
including
hw/acpi/piix4.h.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-5-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe Mathieu-
From: Mark Cave-Ayland
Introduce piix4_pm_init() instance init function and use it to
initialise the separate qdev gpio for the SCI IRQ.
The sci_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().
Signed-off-by: Mark Cave-Ayland
On Mon, 23 May 2022 at 17:40, Icenowy Zheng wrote:
>
> 在 2022-05-23星期一的 15:14 +0100，Peter Maydell写道：
> > On Fri, 20 May 2022 at 13:42, Icenowy Zheng wrote:
> > >
> > > U-Boot queries the FIFO water level to reduce checking status
> > > register
> > > when doing PIO SD card operation.
> > >
> > >
From: Mark Cave-Ayland
This allows the smm_enabled value to be set using a standard qdev property
instead
of being referenced directly in piix4_pm_init().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20220528091934.15520-4-mark.cave-
From: Mark Cave-Ayland
This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
mapped outside of piix4_pm_init().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-6-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe
On 28/5/22 21:20, Bernhard Beschow wrote:
Found-by: Peter Maydell
I suppose you refer to this thread:
https://lore.kernel.org/qemu-devel/CAFEAcA_y69=iXMH75dHeNkxMa038Z7Xk63GW9fdcAFHJSWS=s...@mail.gmail.com/
I'm going to change the tag to "Reported-by".
Reviewed-by: Philippe Mathieu-Daudé
From: Mark Cave-Ayland
Initialize the SMI IRQ in piix4_pm_init().
The smi_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-
Roman Kagan writes:
> On Wed, May 25, 2022 at 12:54:47PM +0200, Markus Armbruster wrote:
>> Konstantin Khlebnikov writes:
>>
>> > This event represents device runtime errors to give time and
>> > reason why device is broken.
>>
>> Can you give an or more examples of the "device runtime errors"
Hi,
> > tdx_add_ram_entry() increments tdx_guest->nr_ram_entries. I think it's
> > worth
> > for comments why this is safe regarding to this for-loop.
>
> The for-loop is to find the valid existing RAM entry (from E820 table).
> It will update the RAM entry and increment tdx_guest->nr_ram_ent
From: Mark Cave-Ayland
Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM
device can be instantiated directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-12-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Ph
From: Mark Cave-Ayland
When QOMifying a device it is typical to use _init() as the suffix for an
instance_init function, however this name is already in use by the legacy
piix4_pm_init() wrapper function. Eventually the wrapper function will be
removed, but for now rename it to piix4_pm_initfn()
On Thu, May 26, 2022 at 10:48:56AM +0800, Xiaoyao Li wrote:
> On 5/24/2022 3:08 PM, Gerd Hoffmann wrote:
> > On Thu, May 12, 2022 at 11:17:45AM +0800, Xiaoyao Li wrote:
> > > TDX guest cannot go to real mode, so just skip the setup of isa-bios.
> >
> > Does isa-bios setup cause any actual problems
From: Mark Cave-Ayland
This function is now unused and so can be completely removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-13-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/acpi/piix4.c
On 27.05.22 18:19, Alexander Bulekov wrote:
> Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> This flag should be set/checked prior to calling a device's MemoryRegion
> handlers, and set when device code initiates DMA. The purpose of this
> flag is to prevent DMA reentra
On 5/30/22 15:41, David Hildenbrand wrote:
On 27.05.22 08:32, zhenwei pi wrote:
On 5/27/22 02:37, Peter Xu wrote:
On Wed, May 25, 2022 at 01:16:34PM -0700, Jue Wang wrote:
The hypervisor _must_ emulate poisons identified in guest physical
address space (could be transported from the source
From: Matheus Ferst
Decodetree generates code with structs named "arg_" for
each argument set. When implementing methods that receive pointers to
these structs, like in [1], checkpatch will sometimes misinterpret them
as variables, resulting in errors like:
ERROR: spaces required around that
Signed-off-by: Paolo Bonzini
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index bf318d9cbb..011cd2ff6b 100644
--- a/meson.build
+++ b/meson.build
@@ -3285,6 +3285,7 @@ foreach m : block_mods + softmmu_mods
install: true,
On Mon, 23 May 2022 at 21:49, Richard Henderson
wrote:
>
> For these cases, the syndrome does not depend on the
> origin or target EL, so we can simply defer selection
> of the target EL to raise_exception.
The commit message says "defer to raise_exception()", but
that would mean passing 0 as the
On Fri, May 20, 2022 at 03:06:47PM +0800, zhenwei pi wrote:
> Origianlly, unpoison_memory() is only used by hwpoison-inject, and
> unpoisons a page which is poisoned by hwpoison-inject too. The kernel PTE
> entry has no change during software poison/unpoison.
>
> On a virtualization platform, it's
On Fri, May 20, 2022 at 03:06:46PM +0800, zhenwei pi wrote:
> Introduce memory failure notifier, once hardware memory failure
> occurs, after the kernel handles the corrupted page successfully,
> someone who registered this chain gets noticed of the corrupted PFN.
>
> Signed-off-by: zhenwei pi
.
On Mon, 23 May 2022 at 21:49, Richard Henderson
wrote:
>
> The work of finding the correct target EL for an exception is
> currently split between raise_exception and target_exception_el.
> Begin merging these by allowing the input to raise_exception
> to be zero and use exception_target_el for th
On Fri, May 27, 2022 at 09:25:06AM -0500, Eric Blake wrote:
> On Thu, May 26, 2022 at 08:23:02PM +0100, Alberto Faria wrote:
> > On Thu, May 26, 2022 at 9:55 AM Stefan Hajnoczi wrote:
> > > The bdrv_pread()/bdrv_pwrite() errno for negative bytes changes from
> > > EINVAL to EIO. Did you audit the
On 5/30/22 15:48, David Hildenbrand wrote:
+
struct virtio_balloon {
struct virtio_device *vdev;
struct virtqueue *inflate_vq, *deflate_vq, *stats_vq, *free_page_vq;
@@ -126,6 +133,16 @@ struct virtio_balloon {
/* Free page reporting device */
struct virtque
On Fri, May 27, 2022 at 09:25:06AM -0500, Eric Blake wrote:
> On Thu, May 26, 2022 at 08:23:02PM +0100, Alberto Faria wrote:
> > On Thu, May 26, 2022 at 9:55 AM Stefan Hajnoczi wrote:
> > > The bdrv_pread()/bdrv_pwrite() errno for negative bytes changes from
> > > EINVAL to EIO. Did you audit the
On Thu, May 26, 2022 at 02:54:32PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
>
> Hi all!
>
> Finally, I'm at Yandex, so that's my new address. I don't think .mailmap
> or contrib/gitdm/aliases really need to be updated.
>
> I send this patch
For completeness, a few more lines from IRC:
13:56 < hreitz> Errr s/E2BIG/ENOSPC/
13:57 < kwolf> Anthony added it like this in 71d0770c4ce, and then we only had
extensions and refactorings
13:58 < kwolf> Yes, ENOSPC actually has a different meaning because of the
werror/rerror stuff
13:58 < kwol
Currently we use 'id' option as the name of VDUSE device.
It's a bit confusing since we use one value for two different
purposes: the ID to identfy the export within QEMU (must be
distinct from any other exports in the same QEMU process, but
can overlap with names used by other processes), and the
On 220530 1219, Peter Maydell wrote:
> On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
> >
> > Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> > This flag should be set/checked prior to calling a device's MemoryRegion
> > handlers, and set when device code initiat
Am 20.05.2022 um 09:59 hat Fabian Ebner geschrieben:
> On 64-bit platforms, assigning SIZE_MAX to the int64_t max_pdiscard
> results in a negative value, and the following assertion would trigger
> down the line (it's not the same max_pdiscard, but computed from the
> other one):
> qemu-system-x86_
Am 24.05.2022 um 19:30 hat Emanuele Giuseppe Esposito geschrieben:
> It seems that aio_wait_kick always required a memory barrier
> or atomic operation in the caller, but nobody actually
> took care of doing it.
>
> Let's put the barrier in the function instead, and pair it
> with another one in A
Hi Bernhard,
On 28/5/22 21:20, Bernhard Beschow wrote:
PCI interrupt wiring and device creation (piix4 only) were performed
in create() functions which are obsolete. Move these tasks into QOM
functions to modernize the code.
In order to avoid duplicate checking for xen_enabled() the piix3 reali
On 29/5/22 20:09, Bernhard Beschow wrote:
On Sun, May 29, 2022 at 11:05 AM Mark Cave-Ayland
mailto:mark.cave-ayl...@ilande.co.uk>>
wrote:
On 28/05/2022 20:20, Bernhard Beschow wrote:
> TYPE_PIIX3_PCI_DEVICE resides there as already, so add the remaining
> ones, too.
>
Am 16.05.2022 um 23:05 hat Eric Blake geschrieben:
> CID 1488362 points out that the second 'rc >= 0' check is now dead
> code.
>
> Reported-by: Peter Maydell
> Fixes: 172f5f1a40(nbd: remove peppering of nbd_client_connected)
> Signed-off-by: Eric Blake
Thanks, applied to the block branch.
Kev
On 13/5/22 20:09, Bernhard Beschow wrote:
This function was declared in a generic and public header, implemented
in a device-specific source file but only used in xen_platform. Given its
'aux' parameter, this function is more xen-specific than piix-specific.
Also, the hardcoded magic constants se
The previous patch used wrong count setting with index value, which got wrong
value from CPUID(EAX=12,ECX=0):EAX. So the SGX1 instruction can't be exposed
to VM and the SGX decice can't work in VM.
Fixes: d19d6ffa0710 ("target/i386: introduce helper to access supported CPUID")
Signed-off-by: Yang
On Mon, 30 May 2022 at 14:10, Alexander Bulekov wrote:
>
> On 220530 1219, Peter Maydell wrote:
> > On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
> > >
> > > Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> > > This flag should be set/checked prior to calling a
On 28/5/22 22:47, Lev Kujawski wrote:
Eliminates the remaining TODOs in hw/ide/piix.c by:
- Using pci_set_{size} functions to write the PIIX PCI configuration
space instead of manipulating it directly as an array; and
- Documenting default register values by reference to the controlling
spe
> -Original Message-
> From: zhenwei pi [mailto:pizhen...@bytedance.com]
> Sent: Friday, May 27, 2022 4:48 PM
> To: m...@redhat.com; Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; virtualizat...@lists.linux-foundation.org;
> helei.si...@bytedance.com; berra...@redhat.com; zhenwei pi
>
> S
On 28/5/22 22:46, Lev Kujawski wrote:
Signed-off-by: Lev Kujawski
---
hw/ide/atapi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Mon, May 23, 2022 at 03:22:32PM +, Sean Christopherson wrote:
> On Mon, May 23, 2022, Chao Peng wrote:
> > On Fri, May 20, 2022 at 06:31:02PM +, Sean Christopherson wrote:
> > > On Fri, May 20, 2022, Andy Lutomirski wrote:
> > > > The alternative would be to have some kind of separate ta
On 28/5/22 22:47, Lev Kujawski wrote:
One method to enable PCI bus mastering for IDE controllers, often used
by x86 firmware, is to write 0x7 to the PCI command register. Neither
the PIIX3 specification nor actual hardware (a Tyan S1686D system)
permit modification of the Memory Space Enable (MS
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index d
Currently only machine with CXL support upstream is i386/pc but arm/virt
patches have been posted and once this is merged an updated series will
follow. Switch support is queued behind this as well because they both
include documentation updates.
Paolo Bonzini highlighted a couple of issues with t
On 30/5/22 15:28, Peter Maydell wrote:
On Mon, 30 May 2022 at 14:10, Alexander Bulekov wrote:
On 220530 1219, Peter Maydell wrote:
On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
This flag should be set/checked
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for mul
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host-stubs.c | 2 +-
hw/cxl/cxl-host.c | 8 +++-
hw/i386/pc.c | 5 +
include/hw/cxl/cxl.h | 2 --
include/hw/cxl/cxl_host.h | 1 +
softmmu/vl.c
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| Bin 184 -> 184 bytes
tests/qtest/bios-tables-test-al
On 220530 1428, Peter Maydell wrote:
> On Mon, 30 May 2022 at 14:10, Alexander Bulekov wrote:
> >
> > On 220530 1219, Peter Maydell wrote:
> > > On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
> > > >
> > > > Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> > > >
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c| 1 -
include/hw/boards.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 19420b043b..d530
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Signed-off-by: Jonathan Cameron
---
hw/core/machine.c| 6 --
hw/
On 28/5/22 11:41, Helge Deller wrote:
This fixes the serial ports in the emulation to behave as on original
hardware.
On the real hardware, the LASI UART is serial port #0 and the DINO UART
is serial port #1. This is fixed in SeaBIOS-hppa firmware v6, which is
why at least this firmware version
On 3/5/22 17:11, Richard Henderson wrote:
On 5/3/22 06:07, nihui wrote:
From: Ni Hui
Fix the SAT_S and SAT_U trans helper confusion.
Signed-off-by: Ni Hui
---
target/mips/tcg/msa_translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/msa_translate.
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is needed to ensure that there is
On 3/5/22 17:12, Richard Henderson wrote:
On 5/3/22 06:07, nihui wrote:
From: Ni Hui
Actually look into dfe structure data so that df_extract_val() and
df_extract_df() can return immediate and datafield other than BYTE.
Doh my bad again.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT inst
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron
---
hw/acpi/cxl.c | 9 -
hw/i386/acpi-build.c | 4 ++--
include/hw/acpi/cxl.h | 5 +++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/cxl.c b/hw/acpi/c
On 5/5/22 12:18, Peter Maydell wrote:
The sysbus floppy controllers (devices sysbus-fdc and sun-fdtwo)
don't support DMA. The core floppy controller code expects this to
be indicated by setting FDCtrl::dma_chann to -1. This used to be
done in the device instance_init functions sysbus_fdc_initfn
On 220530 1539, Philippe Mathieu-Daudé wrote:
> On 30/5/22 15:28, Peter Maydell wrote:
> > On Mon, 30 May 2022 at 14:10, Alexander Bulekov wrote:
> > >
> > > On 220530 1219, Peter Maydell wrote:
> > > > On Fri, 27 May 2022 at 17:19, Alexander Bulekov wrote:
> > > > >
> > > > > Add a flag to the
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