Hi,
I'm trying to recover hardware corrupted page by virtio balloon, the
workflow of this feature like this:
Guest 5.MF -> 6.RVQ FE10.Unpoison page
/ \/
---+-+--+---
|
Origianlly, unpoison_memory() is only used by hwpoison-inject, and
unpoisons a page which is poisoned by hwpoison-inject too. The kernel PTE
entry has no change during software poison/unpoison.
On a virtualization platform, it's possible to fix hardware corrupted page
by hypervisor, typically the
Introduce memory failure notifier, once hardware memory failure
occurs, after the kernel handles the corrupted page successfully,
someone who registered this chain gets noticed of the corrupted PFN.
Signed-off-by: zhenwei pi
---
include/linux/mm.h | 2 ++
mm/memory-failure.c | 33 +
Introduce a new queue 'recover VQ', this allows guest to recover
hardware corrupted page:
Guest 5.MF -> 6.RVQ FE10.Unpoison page
/ \/
---+-+--+---
| | |
Specify maximum possible APIC ID assigned for current VM session prior to
the creation of vCPUs. KVM need set up VM-scoped data structure indexed by
the APIC ID, e.g. Posted-Interrupt Descriptor table to support Intel IPI
virtualization.
It can be achieved by calling KVM_ENABLE_CAP for KVM_CAP_MAX
On 5/20/22 08:53, Joel Stanley wrote:
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.
There is an upstream Linux kernel driver for this device and support in
various other firmware projects for it.
I see that the mmc
On Fri, May 20, 2022 at 02:39:28PM +0800, Zeng Guang wrote:
>Specify maximum possible APIC ID assigned for current VM session prior to
>the creation of vCPUs. KVM need set up VM-scoped data structure indexed by
>the APIC ID, e.g. Posted-Interrupt Descriptor table to support Intel IPI
>virtualizatio
On 64-bit platforms, assigning SIZE_MAX to the int64_t max_pdiscard
results in a negative value, and the following assertion would trigger
down the line (it's not the same max_pdiscard, but computed from the
other one):
qemu-system-x86_64: ../block/io.c:3166: bdrv_co_pdiscard: Assertion
`max_pdisca
In target/arm/cpu64.c, CPU init function for A64FX is there, add this
CPU to the sbsa-ref board.
Signed-off-by: Itaru Kitayama
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 4bb444684f..a7d27b2e55 100644
--- a/hw/arm/sbsa-ref
Add ELF header checking to prevent processing input file which is not
QEMU x86_64 guest memory dump or even not ELF.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1013
Signed-off-by: Viktor Prutyanov
---
contrib/elf2dmp/qemu_elf.c | 53 ++
1 file ch
In commit 5814d587fe861fe9 we added support for emulating
FEAT_HCX (Support for the HCRX_EL2 register). However we
forgot to add it to the list in emulated.rst. Correct the
omission.
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
Signed-off-by: Peter Maydell
---
Oops, missed
On Mon, 16 May 2022 at 02:58, Itaru Kitayama wrote:
>
> With the latest, manually built TF-A, I was able to boot a72, but not
> max. Since `max` type is supported by TF-A, I think it might be
> a Qemu issue.
How far did boot go? Does '-cpu max,lpa2=off' work? There's a
bug in older Linux kernels
On Fri, 20 May 2022 at 09:46, Itaru Kitayama wrote:
>
> In target/arm/cpu64.c, CPU init function for A64FX is there, add this
> CPU to the sbsa-ref board.
(cc'ing the sbsa-ref maintainers)
This isn't an objection, but I would like to know what the
sbsa-ref maintainers' view is on what CPUs the b
When no memory backend is specified in machine options,
a default memory device will be added with default_ram_id.
However, if a memory backend object is added in QEMU options
and id is the same as default_ram_id, a coredump happens.
Command line:
qemu-system-x86_64 -name guest=vmtest,debug-thread
By calling a57’s CPU init function inside the max’s, I can bring up the
sbsa-ref board with the latest kernel. I’ll try to patch a64’s unit
function with Shuichiro next week.
On Fri, May 20, 2022 at 17:57 Peter Maydell
wrote:
> On Mon, 16 May 2022 at 02:58, Itaru Kitayama
> wrote:
> >
> > With
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes commit: 9951ba94
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 8
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/targ
On Fri, 20 May 2022 at 10:02, Itaru Kitayama wrote:
>
> By calling a57’s CPU init function inside the max’s, I can bring up
> the sbsa-ref board with the latest kernel.
I'm not sure exactly what you're doing, but this sounds like
a workaround for something -- we should find out exactly
what is go
I’ve verified only a57 and a72 boot on sbsa ref board, but not N1 and
‘max’. As I said, I’ll try to figure out how CPU init is done in QEMU for
those not working CPU types.
On Fri, May 20, 2022 at 18:27 Peter Maydell
wrote:
> On Fri, 20 May 2022 at 10:02, Itaru Kitayama
> wrote:
> >
> > By call
If Leif can jump in that’d be great.
On Fri, May 20, 2022 at 18:31 Itaru Kitayama
wrote:
> I’ve verified only a57 and a72 boot on sbsa ref board, but not N1 and
> ‘max’. As I said, I’ll try to figure out how CPU init is done in QEMU for
> those not working CPU types.
>
> On Fri, May 20, 2022 at
When no memory backend is specified in machine options,
a default memory device will be added with default_ram_id.
However, if a memory backend object is added in QEMU options
and id is the same as default_ram_id, a coredump happens.
Command line:
qemu-system-x86_64 -name guest=vmtest,debug-thread
Doesn’t ‘max’ support being there mean we are supposed to support various
types of CPUs on the SBSA board?
On Fri, May 20, 2022 at 18:00 Peter Maydell
wrote:
> On Fri, 20 May 2022 at 09:46, Itaru Kitayama
> wrote:
> >
> > In target/arm/cpu64.c, CPU init function for A64FX is there, add this
> >
On 2022/5/19 下午11:24, Richard Henderson wrote:
On 5/19/22 06:04, yangxiaojuan wrote:
On 2022/5/19 上午3:59, Richard Henderson wrote:
On 5/17/22 04:30, Xiaojuan Yang wrote:
+static void ls7a_stop_toymatch(LS7ARtcState *s)
+{
+ int i;
+ uint64_t now;
+
+ now = qemu_clock_get_ms(rtc_cl
Reviewed-by: Konstantin Kostiuk
On Fri, May 20, 2022 at 5:20 AM luzhipeng wrote:
> Add a new 'guest-get-diskstats' command for report disk io statistics
> for Linux guests. This can be useful for getting io flow or handling
> IO fault, no need to enter guests.
>
> Signed-off-by: luzhipeng
> Re
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState property @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
---
hw/i386/acpi-build.c | 2 +-
hw
v4[5] -> v5:
* Fixed the 32-bit build(s) (patch 1, Michael Tsirkin)
* Fix wrong reference (patch 4) to TCG_PHYS_BITS in code comment and
commit message;
---
This series lets Qemu spawn i386 guests with >= 1010G with VFIO,
particularly when running on AMD systems with an IOMMU.
Since Linux v5.4,
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may mak
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
piix needs a bit of care given all the !pci_enabled()
and that the pci_hole64_size is private to i440fx.
This is in preparation to determine that host-phys-bits are
enough and for pci-ho
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, expect for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or platform-
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make e
On 5/12/22 16:43, Avihai Horon wrote:
> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
> index 21e8f9d4d4..d4b6653026 100644
> --- a/hw/vfio/migration.c
> +++ b/hw/vfio/migration.c
> @@ -863,10 +863,17 @@ int vfio_migration_probe(VFIODevice *vbasedev, Error
> **errp)
> struct vfio_reg
U-Boot queries the FIFO water level to reduce checking status register
when doing PIO SD card operation.
Report a FIFO water level of 1 when data is ready, to prevent the code
from trying to read 0 words from the FIFO each time.
Signed-off-by: Icenowy Zheng
---
hw/sd/allwinner-sdhost.c | 7
submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/zhenwei-pi/recover-hardware-corrupted-page-by-virtio-balloon/20220520-151328
base: https://git.kernel.org/pub/scm/linux/kerne
clang reports this variable as 'set but not used'.
Signed-off-by: Brian Cain
---
tests/tcg/multiarch/linux/linux-test.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tests/tcg/multiarch/linux/linux-test.c
b/tests/tcg/multiarch/linux/linux-test.c
index 019d8175ca..d57
On Fri, 20 May 2022 at 14:16, Brian Cain wrote:
>
> clang reports this variable as 'set but not used'.
>
> Signed-off-by: Brian Cain
> ---
> tests/tcg/multiarch/linux/linux-test.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/tests/tcg/multiarch/linux/linux-test.c
> -Original Message-
> From: Peter Maydell
> Sent: Friday, May 20, 2022 8:21 AM
> To: Brian Cain
> Cc: Daniel P. Berrangé ; qemu-devel@nongnu.org;
> Alex Bennée
> Subject: Re: [PATCH] tests: Remove unused "wcount" from linux-test.c
>
> WARNING: This email originated from outside of Qual
submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/zhenwei-pi/recover-hardware-corrupted-page-by-virtio-balloon/20220520-151328
base: https://git.kernel.org/pub/scm/linux/kernel/git/a
Reviewed-by: Konstantin Kostiuk
On Fri, May 13, 2022 at 9:08 PM wrote:
> From: Marc-André Lureau
>
> qemu_open_old() uses qemu_open_internal() which handles special
> "/dev/fdset/" path for monitor fd sets, set CLOEXEC, and uses Error
> reporting (and some O_DIRECT special error casing).
>
> T
Reviewed-by: Konstantin Kostiuk
On Fri, May 13, 2022 at 9:08 PM wrote:
> From: Marc-André Lureau
>
> This a more accurate way to lookup the test data, and will allow to move
> the test in a subproject.
>
> Signed-off-by: Marc-André Lureau
> ---
> tests/unit/test-qga.c | 11 +--
> 1 f
From: "Lucas Mateus Castro (alqotel)"
Based-on: <20220517161522.36132-1-victor.colo...@eldorado.org.br>
This patch series is a patch series of the Matrix-Multiply Assist (MMA)
instructions implementation from the PowerISA 3.1
These and the VDIV/VMOD implementation are the last new PowerISA 3.1
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4: VSX
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Negative accumulate
xvf16ger2np: VSX Vector 16-bit Float
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating
From: Joel Stanley
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
linux-user/elfload.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero
The PowerISA 3.1 mentions that for the current version of the
architecture, "the hardware implement
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negati
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update)
pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) Positive multiply, Po
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
On Wed, May 18, 2022 at 4:39 PM Mark Cave-Ayland
wrote:
>
> Perform the generation of the VIOT ACPI table in 2 separate passes: the first
> pass
> enumerates all of the PCI host bridges and adds the min_bus and max_bus
> information
> to an array.
>
> Once this is done the VIOT table header is g
On 5/19/22 17:04, Nicholas Piggin wrote:
I'm even more tempted to merge the two files to put all of the machine-specific
cache data
in the same place, then this variable can be static. There's even an existing
TODO
comment in cacheflush.c for aarch64.
That might be nice. Do you want me to lo
submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/zhenwei-pi/recover-hardware-corrupted-page-by-virtio-balloon/20220520-151328
base: https://git.kernel.org/pub/scm/linux/kernel/git/a
On 5/19/22 13:18, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Move xscvspdpn to decodetree, drop helper_xscvspdpn and use
helper_todouble directly.
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 5 -
target/ppc/helper.h | 1 -
targe
On 5/20/22 01:43, Peter Maydell wrote:
In commit 5814d587fe861fe9 we added support for emulating
FEAT_HCX (Support for the HCRX_EL2 register). However we
forgot to add it to the list in emulated.rst. Correct the
omission.
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
Signe
On 5/20/22 01:43, Viktor Prutyanov wrote:
Add ELF header checking to prevent processing input file which is not
QEMU x86_64 guest memory dump or even not ELF.
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1013
Signed-off-by: Viktor Prutyanov
---
contrib/elf2dmp/qemu_elf.c | 53 ++
On 5/20/22 06:51, Lucas Mateus Castro(alqotel) wrote:
+if (acc) {
+aux_acc = at[i].VsrSF(j);
+if (!neg_mul && !neg_acc) {
+r = float32_add(r, aux_acc, excp_ptr);
+} else if (!neg_mul) {
+
The initial CXL support including support on x86/pc has now merged
(thanks Michael!).
This is the first of the two remaining parts of that series, unchanged
since v10. The second is CXL switch support which can be applied
separately to this series and will be sent shortly.
CXL support requires t
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
Signed-off-
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 48 +
tests/qtest/meson.build | 1 +
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl
On 20/05/2022 12:47, Richard Henderson wrote:
On 5/20/22 06:51, Lucas Mateus Castro(alqotel) wrote:
+ if (acc) {
+ aux_acc = at[i].VsrSF(j);
+ if (!neg_mul && !neg_acc) {
+ r = float32_add(r, aux_acc, excp_ptr);
+
A quick PoC to show the feasibility of emulating the CXL 2.0
Fabric Manager API over MCTP over I2C as possible path to standards
based configuration of emulated CXL switches. Lots of missing parts
(such as hooking this up to the upstream ports or making it actually
do anything useful), but it's en
A quick PoC to show the feasibility of emulating the CXL 2.0
Fabric Manager API over MCTP over I2C as possible path to standards
based configuration of emulated CXL switches. Lots of missing parts
(such as hooking this up to the upstream ports or making it actually
do anything useful), but it's en
The Fabric Manager API is used to configure CXL switches and
devices. DMTF has defined an MCTP binding specification to carry
these messages. Then end goal of this work is to hook this
up to an emulated CXL switch and allow control of the switch
configuration. For now it's stand alone to show how
As the only I2C emulation in QEMU that supports being both
a master and a slave, suitable for MCTP over i2c is aspeed-i2c
add this controller to the arm virt model and hook up our new
i2c_mctp_cxl_fmapi device.
The current Linux driver for aspeed-i2c has a hard requirement on
a reset controller.
Add support for ISA 3.00 tlbie/tlbiel instructions, with
RIC, PRS and R operands.
Also, for Radix MMU, add support for the TLB invalidation of a
single page. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation har
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/insn32.decode | 1 +
target/ppc/translate.c | 22
target/ppc/translate/storage-ctrl-impl.c.inc | 16 +-
3 files changed, 12 insertions(+),
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
---
targ
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 7 ++
target/ppc/translate.c | 42 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 81 +
Exposing the io_base offset as a QOM property not only allows it to be
configurable but also to be displayed in HMP:
Before:
(qemu) info qtree
...
dev: mc146818rtc, id ""
gpio-out "" 1
base_year = 0 (0x0)
irq = 8 (0x8)
lost_tick_pol
Since commit 3b004a16540aa41f2aa6a1ceb0bf306716766914 'hw/rtc/
mc146818rtc: QOM'ify IRQ number' mc146818rtc's IRQ number is
configurable. Fix microvm-dt to respect its value.
Signed-off-by: Bernhard Beschow
---
hw/i386/microvm-dt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
This little series enhances QOM support for mc146818rtc:
* makes microvm-dt respect mc146818rtc's IRQ number set by QOM property and
* adds an io_base QOM property similar to other ISA devices
Bernhard Beschow (2):
hw/i386/microvm-dt: Determine mc146818rtc's IRQ number from QOM
property
rt
On 5/19/22 08:37, Chao Peng wrote:
Extend the memslot definition to provide guest private memory through a
file descriptor(fd) instead of userspace_addr(hva). Such guest private
memory(fd) may never be mapped into userspace so no userspace_addr(hva)
can be used. Instead add another two new fields
v2:
* Omit removal of isa_connect_gpio_out() (Mark)
v1:
This patch series contains random cleanups that I made while studying the code.
Bernhard Beschow (10):
hw: Reuse TYPE_I8042 define
hw/audio/cs4231a: Const'ify global tables
hw/i386/pc: Unexport PC_CPU_MODEL_IDS macro
hw/i386/pc: Unex
TYPE_I8042 is exported, so reuse it for consistency.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 4 ++--
hw/sparc64/sun4u.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7c39c91335..c914a
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c | 4 ++--
include/hw/i386/pc.h | 3 ---
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2ffaac52fb..d7583045a0 100644
--- a/
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
---
include/hw/i386/pc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index cb491fc43b..9c1d1c0a7c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -170,9 +170,6 @@ vo
The tables contain spcifically crafted constants for algorithms, so make
them immutable.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/audio/cs4231a.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c
dump_opcount_info() is a one-line wrapper around tcg_dump_op_count()
which is also exported. So use the latter directly.
Signed-off-by: Bernhard Beschow
---
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 5 -
include/exec/cpu-all.h| 1 -
3 files changed, 1 insertion(+), 7
Commit 28290f37e20cda27574f15be9e9499493e3d0fe8 'PPC: E500: Generate
device tree on reset' improved device tree generation and made
BINARY_DEVICE_TREE_FILE obsolete.
Signed-off-by: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
---
hw/ppc/e500.c | 1 -
1 file changed, 1 deletion(-)
diff
The macro seems to be used only internally, so remove it.
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c | 9 +
include/hw/i386/pc.h | 8
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c914
Commit 3a841ab53f165910224dc4bebabf1a8f1d04200c 'qapi: introduce
x-query-jit QMP command' basically moved the only function using
dump_drift_info() to cpu-exec.c. Therefore, dump_drift_info() doesn't
need to be exported any longer.
Signed-off-by: Bernhard Beschow
---
accel/tcg/cpu-exec.c | 2 +
Am 20. Mai 2022 18:01:07 UTC schrieb Bernhard Beschow :
>Commit 3a841ab53f165910224dc4bebabf1a8f1d04200c 'qapi: introduce
>x-query-jit QMP command' basically moved the only function using
>dump_drift_info() to cpu-exec.c. Therefore, dump_drift_info() doesn't
>need to be exported any longer.
>
>Sign
Am 20. Mai 2022 18:01:09 UTC schrieb Bernhard Beschow :
>Ammends commit 9f73de8df0335c9387f4ee39e207a65a1615676f 'docs: rSTify
>the "SubmitAPatch" wiki'.
>
>Cc: qemu-sta...@nongnu.org
>Signed-off-by: Bernhard Beschow
>---
> docs/devel/submitting-a-patch.rst | 6 +++---
> 1 file changed, 3 insertion
Am 20. Mai 2022 18:01:08 UTC schrieb Bernhard Beschow :
>dump_opcount_info() is a one-line wrapper around tcg_dump_op_count()
>which is also exported. So use the latter directly.
>
>Signed-off-by: Bernhard Beschow
>---
> accel/tcg/cpu-exec.c | 2 +-
> accel/tcg/translate-all.c | 5 -
> incl
etsec_create() wraps qdev API which is outdated. It is also unused,
so remove it.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/fsl_etsec/etsec.c | 23 ---
hw/net/fsl_etsec/etsec.h | 7 ---
2 files changed, 30 deletions(-)
diff --git a/
Ammends commit 9f73de8df0335c9387f4ee39e207a65a1615676f 'docs: rSTify
the "SubmitAPatch" wiki'.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bernhard Beschow
---
docs/devel/submitting-a-patch.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/devel/submitting-a-patch
On Fri, May 20, 2022, Andy Lutomirski wrote:
> The alternative would be to have some kind of separate table or bitmap (part
> of the memslot?) that tells KVM whether a GPA should map to the fd.
>
> What do you all think?
My original proposal was to have expolicit shared vs. private memslots, and
From: "Maciej S. Szmigiero"
Since KVM commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when
guest MPX disabled")
it is not possible to disable MPX on a "-cpu host" just by adding "-mpx"
there if the host CPU does indeed support MPX.
QEMU will fail to set MSR_IA32_VMX_TRUE_{EXIT,EN
On 5/19/22 23:22, Thomas Huth wrote:
On 19/05/2022 13.55, Peter Maydell wrote:
On Thu, 19 May 2022 at 07:32, Thomas Huth wrote:
On 18/05/2022 18.12, Richard Henderson wrote:
On 5/18/22 02:04, Thomas Huth wrote:
Hi Richard!
The following changes since commit eec398119fc6911d99412c37af06a
On 5/20/22 09:42, Lucas Mateus Martins Araujo e Castro wrote:
On 20/05/2022 12:47, Richard Henderson wrote:
On 5/20/22 06:51, Lucas Mateus Castro(alqotel) wrote:
+ if (acc) {
+ aux_acc = at[i].VsrSF(j);
+ if (!neg_mul && !neg_acc) {
+
I'm running QEMU on a Windows host with multiple Linux guest VMs. I'm trying to
share a host directory with all the guests.
As I understand it, the way to do this with Linux hosts would be to configure a
9p share[0]. However, it appears that 9p support for Windows hosts is currently
a work in p
From: "Lucas Mateus Castro (alqotel)"
Based-on: <20220517161522.36132-1-victor.colo...@eldorado.org.br>
This patch series is a patch series of the Matrix-Multiply Assist (MMA)
instructions implementation from the PowerISA 3.1
These and the VDIV/VMOD implementation are the last new PowerISA 3.1
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update)
pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) Positive multiply, Po
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4: VSX
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero
The PowerISA 3.1 mentions that for the current version of the
architecture, "the hardware implement
From: Joel Stanley
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
linux-user/elfload.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negati
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Negative accumulate
xvf16ger2np: VSX Vector 16-bit Float
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
Bus type spaces (Indicates a storage spaces bus) is not
supported, so return it as unknown.
Signed-off-by: Konstantin Kostiuk
---
qga/commands-win32.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index d56b5fd2a7..5ca2af9173 100644
--- a/qg
On Fri, May 20, 2022 at 10:15 PM Konstantin Kostiuk
wrote:
> Bus type spaces (Indicates a storage spaces bus) is not
> supported, so return it as unknown.
>
> Signed-off-by: Konstantin Kostiuk
>
Reviewed-by: Marc-André Lureau
> ---
> qga/commands-win32.c | 5 +
> 1 file changed, 5 inser
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