On 05/05/2022 17.09, Daniel P. Berrangé wrote:
On Thu, May 05, 2022 at 04:12:11PM +0200, Thomas Huth wrote:
On 05/05/2022 13.55, Daniel P. Berrangé wrote:
On Thu, May 05, 2022 at 09:14:57AM +0100, Daniel P. Berrangé wrote:
On Thu, May 05, 2022 at 09:48:41AM +0200, Thomas Huth wrote:
Our suppo
Our support statement for Windows currently talks about "Vista / Server
2008" - which is related to the API of Windows, and this is not easy
to understand for the non-technical users. Additionally, glib sets the
_WIN32_WINNT macro to 0x0601 already, which indicates the Windows 7 API,
so QEMU effect
On 5/11/22 18:54, Daniel P. Berrangé wrote:
On Wed, May 11, 2022 at 01:07:47PM +0200, Paolo Bonzini wrote:
On 5/11/22 12:10, Daniel P. Berrangé wrote:
I expect creating/deleting I/O threads is cheap in comparison to
the work done for preallocation. If libvirt is using -preconfig
and object-add
On Wed, May 11, 2022 at 09:43:28AM +0200, Paolo Bonzini wrote:
The vsock callbacks .vhost_vsock_set_guest_cid and
.vhost_vsock_set_running are the only ones to be conditional
on #ifdef CONFIG_VHOST_VSOCK. This is different from any other
device-dependent callbacks like .vhost_scsi_set_endpoint,
From: Stefano Brivio
Other errors are treated as failure by net_stream_client_init(),
but if connect() returns EINVAL, we'll fail silently. Remove the
related exception.
Signed-off-by: Stefano Brivio
[lvivier: applied to net/stream.c]
Signed-off-by: Laurent Vivier
---
net/stream.c | 3 +--
1
It is less complex to manage special cases directly in
net_dgram_mcast_init() and net_dgram_udp_init().
Signed-off-by: Laurent Vivier
---
net/dgram.c | 143 +++-
1 file changed, 73 insertions(+), 70 deletions(-)
diff --git a/net/dgram.c b/net/dgra
Copied from socket netdev file and modified to use SocketAddress
to be able to introduce new features like unix socket.
"udp" and "mcast" are squashed into dgram netdev, multicast is detected
according to the IP address type.
"listen" and "connect" modes are managed by stream netdev. An optional
p
Signed-off-by: Laurent Vivier
---
net/stream.c | 106 +++
1 file changed, 99 insertions(+), 7 deletions(-)
diff --git a/net/stream.c b/net/stream.c
index 12fc26b9f4c7..dca50508ed84 100644
--- a/net/stream.c
+++ b/net/stream.c
@@ -234,7 +234,7 @@ st
As qemu_opts_parse_noisily() flattens the QAPI structures ("type" field
of Netdev structure can collides with "type" field of SocketAddress),
we introduce a way to bypass qemu_opts_parse_noisily() and use directly
visit_type_Netdev() to parse the backend parameters.
Signed-off-by: Laurent Vivier
"-netdev socket" only supports inet sockets.
It's not a complex task to add support for unix sockets, but
the socket netdev parameters are not defined to manage well unix
socket parameters.
As discussed in:
"socket.c added support for unix domain socket datagram transport"
https://lore.kern
Signed-off-by: Laurent Vivier
---
net/dgram.c | 65 ++---
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/net/dgram.c b/net/dgram.c
index c0cf0410792e..9f20bdbc163c 100644
--- a/net/dgram.c
+++ b/net/dgram.c
@@ -85,8 +85,15 @@ static
dgram_dst is a sockaddr_in structure. To be able to use it with
unix socket, use a pointer to a generic sockaddr structure.
Signed-off-by: Laurent Vivier
---
net/dgram.c | 76 +++--
1 file changed, 45 insertions(+), 31 deletions(-)
diff --git a/ne
On Thu, May 12, 2022 at 09:41:29AM +0200, Paolo Bonzini wrote:
> On 5/11/22 18:54, Daniel P. Berrangé wrote:
> > On Wed, May 11, 2022 at 01:07:47PM +0200, Paolo Bonzini wrote:
> > > On 5/11/22 12:10, Daniel P. Berrangé wrote:
> > > > I expect creating/deleting I/O threads is cheap in comparison to
Signed-off-by: Laurent Vivier
---
include/qemu/sockets.h | 2 ++
net/net.c | 62 ++
2 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h
index 038faa157f59..47194b9732f8 100644
--- a/
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
On Wed, May 11, 2022 at 07:51:47PM +0200, Thomas Huth wrote:
> We have "-sdl" and "-curses", but no "-gtk" and no "-cocoa" ...
> these old-style options are rather confusing than helpful nowadays.
> Now that the deprecation period is over, let's remove them, so we
> get a cleaner interface (where "
On Wed, May 11, 2022 at 07:51:45PM +0200, Thomas Huth wrote:
> These parameters are in the way for further refactoring (since they
> use an underscore in the name which is forbidden in QAPI), so let's
> remove these now that their deprecation period is over.
>
> Signed-off-by: Thomas Huth
> ---
>
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c| 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
On Wed, May 11, 2022 at 07:51:46PM +0200, Thomas Huth wrote:
> The "-display sdl" option still uses a hand-crafted parser for its
> parameters since some of them used underscores which is forbidden
> in QAPI. Now that the problematic parameters have been removed, we can
> switch to use the QAPI par
On 5/11/22 20:44, Markus Armbruster wrote:
Paolo Bonzini writes:
Signed-off-by: Paolo Bonzini
---
softmmu/vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/softmmu/vl.c b/softmmu/vl.c
index c2919579fd..fbef0f5c5f 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -3723,
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail eleme
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
---
target/riscv/vector_helper.c | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 85dd611
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 13 +-
target/riscv/internals.h
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
di
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff
From: eopXD
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +
target/riscv/vector_helper.c
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7dcb51b6
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 7 +++--
target/riscv/vector_helper.c| 40 +
2 files changed, 45 insertions(+), 2 deletions(-)
di
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
target/riscv/vector_helper.c| 20
2 files changed, 28 insertions(+), 4 deletions(-)
On Thu, May 12, 2022 at 09:19:30AM +0800, luzhipeng wrote:
> Add a new 'guest-get-diskstats' command for report disk io statistics
> for Linux guests. This can be usefull for getting io flow or handling
> IO fault, no need to enter guests.
>
> Signed-off-by: luzhipeng
> ---
> qga/commands-posix.
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +
target/riscv/vector_helper.c| 4
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/r
On Thu, May 12, 2022 at 10:09:28AM +0200, Laurent Vivier wrote:
> From: Stefano Brivio
>
> Other errors are treated as failure by net_stream_client_init(),
> but if connect() returns EINVAL, we'll fail silently. Remove the
> related exception.
>
> Signed-off-by: Stefano Brivio
> [lvivier: appli
From: Yueh-Ting (eop) Chen
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are m
On Thu, May 12, 2022 at 09:39:29AM +0200, Thomas Huth wrote:
> Our support statement for Windows currently talks about "Vista / Server
> 2008" - which is related to the API of Windows, and this is not easy
> to understand for the non-technical users. Additionally, glib sets the
> _WIN32_WINNT macro
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c| 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/tar
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
inde
On 10/05/2022 15.43, Cornelia Huck wrote:
On Tue, May 10 2022, Janis Schoetterl-Glausch wrote:
On 5/9/22 10:06, Cornelia Huck wrote:
On Fri, May 06 2022, Janis Schoetterl-Glausch wrote:
Make use of the storage key support of the MEMOP ioctl, if available,
in order to support storage key ch
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnos
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibi
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +++
target/riscv/vector_helper.c| 35 +
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 26 +++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target
On Wed, May 11, 2022 at 1:15 PM Thomas Huth wrote:
> On 11/05/2022 13.13, Philippe Mathieu-Daudé wrote:
> > On Wed, May 11, 2022 at 1:03 PM Thomas Huth wrote:
> >> On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
> >>>On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
> >>> wrote:
>
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
target/riscv/vector_helper.c| 26 +
2 files changed, 38 insertions(+)
diff --git a/target/risc
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 10 ++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.i
On Thu, May 12, 2022 at 11:14:45AM +0200, Philippe Mathieu-Daudé wrote:
> On Wed, May 11, 2022 at 1:15 PM Thomas Huth wrote:
> > On 11/05/2022 13.13, Philippe Mathieu-Daudé wrote:
> > > On Wed, May 11, 2022 at 1:03 PM Thomas Huth wrote:
> > >> On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
>
On Sat, 7 May 2022 at 12:35, Richard Henderson
wrote:
>
> On 5/6/22 11:21, Peter Maydell wrote:
> > This patchset fills in an odd inconsistency in our GICv3 emulation
> > that I noticed while I was doing the GICv4 work. At the moment we
> > allow the CPU to specify the number of bits of virtual pr
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.
Paolo Bonzini writes:
> On 5/11/22 20:44, Markus Armbruster wrote:
>> Paolo Bonzini writes:
>>
>>> Signed-off-by: Paolo Bonzini
>>> ---
>>> softmmu/vl.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/softmmu/vl.c b/softmmu/vl.c
>>> index c2919579fd..fbef0f5c5
Hi, Yi
On 2022/5/11 下午10:17, zhangfei@foxmail.com wrote:
On 2022/5/10 下午10:08, Yi Liu wrote:
On 2022/5/10 20:45, Jason Gunthorpe wrote:
On Tue, May 10, 2022 at 08:35:00PM +0800, Zhangfei Gao wrote:
Thanks Yi and Eric,
Then will wait for the updated iommufd kernel for the PCI MMIO regi
On Apr 29 10:33, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The namespace identifiers reported by the controller is kind of a mess.
> See [1,2].
>
> This series should fix this for both the `-device nvme,drive=...` and
> `-device nvme-ns,...` cases.
>
> [1]: https://lore.kernel.org/linux-nv
Am 12.05.2022 um 08:56 hat 成川 弘樹 geschrieben:
> Thank you for your fix.
>
> I confirmed that after applying this patch, my intended performance
> improvement by 4c41c69e is still kept in our environment.
This is good news. Thank you for testing the patch!
Kevin
From: Klaus Jensen
The internally maintained AEN mask is not cleared on reset. Fix this.
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 1e6e0fcad918..4c8200dfb859 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme
On Thu, Apr 28, 2022 at 09:59:41PM +0800, zhenwei pi wrote:
> From: Lei He
>
> Add unit test and benchmark test for crypto akcipher.
>
> Signed-off-by: lei he
> Signed-off-by: zhenwei pi
> Reviewed-by: Daniel P. Berrangé
> ---
> tests/bench/benchmark-crypto-akcipher.c | 157 ++
> tests/b
On Thu, Apr 28, 2022 at 09:59:38PM +0800, zhenwei pi wrote:
> From: Lei He
>
> Add an ANS.1 DER decoder which is used to parse asymmetric
> cipher keys
>
> Signed-off-by: zhenwei pi
> Signed-off-by: lei he
> ---
> crypto/der.c | 190 +++
> crypto/der.h
On Thu, Apr 28, 2022 at 09:59:37PM +0800, zhenwei pi wrote:
> Introduce new akcipher crypto class 'QCryptoAkCIpher', which supports
> basic asymmetric operations: encrypt, decrypt, sign and verify.
>
> Suggested by Daniel P. Berrangé, also add autoptr cleanup for the new
> class. Thanks to Daniel!
From 5de17d5aacb9cf21de4c9736b227b0498c607709 Mon Sep 17 00:00:00 2001
From: CHRIS HOWARD
Date: Thu, 12 May 2022 11:35:17 +0200
Subject: [PATCH] Fix aarch64 debug register names.
Signed-off-by: CHRIS HOWARD
---
target/arm/helper.c | 16
1 file changed, 12 insertions(+), 4 delet
On Thu, Apr 28, 2022 at 09:59:35PM +0800, zhenwei pi wrote:
> Update header from linux, support akcipher service.
>
> Reviewed-by: Gonglei
> Signed-off-by: lei he
> Signed-off-by: zhenwei pi
> ---
> .../standard-headers/linux/virtio_crypto.h| 82 ++-
> 1 file changed, 81 in
On Thu, May 12, 2022 at 11:21 AM Daniel P. Berrangé wrote:
> On Thu, May 12, 2022 at 11:14:45AM +0200, Philippe Mathieu-Daudé wrote:
> > On Wed, May 11, 2022 at 1:15 PM Thomas Huth wrote:
> > > On 11/05/2022 13.13, Philippe Mathieu-Daudé wrote:
> > > > On Wed, May 11, 2022 at 1:03 PM Thomas Huth
Hi!
The following changes since commit ec11dc41eec5142b4776db1296972c6323ba5847:
Merge tag 'pull-misc-2022-05-11' of git://repo.or.cz/qemu/armbru into staging
(2022-05-11 09:00:26 -0700)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2022-05-12
From: Matthew Rosato
The v1 uapi is deprecated and will be replaced by v2 at some point;
this patch just tolerates the renaming of uapi fields to reflect
v1 / deprecated status.
Signed-off-by: Matthew Rosato
Message-Id: <20220404181726.60291-3-mjros...@linux.ibm.com>
Signed-off-by: Thomas Huth
Am 06.05.2022 um 15:42 hat Hanna Reitz geschrieben:
> When stdout is not a terminal, the buffer may not be flushed at each end
> of line, so we should flush after each test is done. This is especially
> apparent when run by check-block, in two ways:
>
> First, when running make check-block -jX wi
On 64-bit platforms, SIZE_MAX is too large for max_pdiscard, which is
int64_t, and the following assertion would be triggered:
qemu-system-x86_64: ../block/io.c:3166: bdrv_co_pdiscard: Assertion
`max_pdiscard >= bs->bl.request_alignment' failed.
Fixes: 0c8022876f ("block: use int64_t instead of in
Am 09.05.2022 um 14:41 hat Daniel P. Berrangé geschrieben:
> Currently with the TAP harness we see essentially no useful information
> about the I/O tests execution. To pick a random job:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/2429330423
>
> All that we get is this:
>
> 184/204 qemu
Together, these two patches fix the performance regression induced by
QemuSemaphore; individually they don't though.
The third patch is a small cleanup on top, that was enabled by the
recent introduction of min_threads/max_threads knobs for the
thread pool.
6.2:
iops: min=58051, max=62
Several other upcoming patch series will need this update.
Signed-off-by: Thomas Huth
---
.../linux/input-event-codes.h | 25 +-
.../standard-headers/linux/virtio_config.h| 6 +
.../standard-headers/linux/virtio_crypto.h| 82 +++-
linux-headers/asm-arm64/kvm.h
The completion bottom half was scheduled within the pool->lock
critical section. That actually results in worse performance,
because the worker thread can run its own small critical section
and go to sleep before the bottom half starts running.
Note that this simple change does not produce an imp
Commit message nitpick: not sure this is "qapi:". The commit that
introduced "Machine type ... is deprecated" (08fe68244eb) used
"hw/i386:". We commonly use "vl:", "softmmu:", and "softmmu/vl:" for
this file.
Just setting the max threads to 0 is enough to stop all workers.
Signed-off-by: Paolo Bonzini
---
util/thread-pool.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/util/thread-pool.c b/util/thread-pool.c
index da189d9338..392c7d7843 100644
--- a/util/thread-pool.c
+++ b
Together, these two patches fix the performance regression induced by
QemuSemaphore; individually they don't though.
The third patch is a small cleanup on top, that was enabled by the
recent introduction of min_threads/max_threads knobs for the
thread pool.
6.2:
iops: min=58051, max=62
Am 03.05.2022 um 18:21 hat Jon Maloy geschrieben:
>
>
> On 5/3/22 05:59, Kevin Wolf wrote:
> > Am 23.03.2022 um 03:25 hat John Snow geschrieben:
> > > On Fri, Mar 18, 2022 at 2:50 PM Thomas Huth wrote:
> > > > On 10/03/2022 18.53, Jon Maloy wrote:
> > > > > On 3/10/22 12:14, Thomas Huth wrote:
>
Since commit f9fc8932b1 ("thread-posix: remove the posix semaphore
support", 2022-04-06) QemuSemaphore has its own mutex and condition
variable; this adds unnecessary overhead on I/O with small block sizes.
Check the QTAILQ directly instead of adding the indirection of a
semaphore's count. Using
Am Dienstag, 10. Mai 2022, 08:42:31 CEST schrieb Dao Lu:
> Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld
> by default.
>
> Signed-off-by: Dao Lu
This patch with your fixup applied to it and of course
a matching kernel:
Tested-by: Heiko Stuebner
> ---
> targe
Am 12.05.2022 um 02:49 hat Eric Blake geschrieben:
> v3 was here:
> https://lists.gnu.org/archive/html/qemu-devel/2022-03/msg03701.html
> with additional review here:
> https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg00166.html
Thanks, applied to the block branch.
Kevin
Eric Blake writes:
> On Tue, May 03, 2022 at 09:37:37AM +0200, Andrea Bolognani wrote:
>> Perfectly aligned things look pretty, but keeping them that
>> way as the schema evolves requires churn, and in some cases
>> newly-added lines are not aligned properly.
>>
>> Overall, trying to align thing
Please review below patch as well. I'd like to include it
in the series when I send a v2 version of the series.
Thanks,
Helge
From: Helge Deller
Date: Thu, 12 May 2022 13:40:39 +0200
Subject: [PATCH] artist: Fix X cursor position calculation in X11
The X cursor postion can be calculated based
Thomas Huth writes:
> The "-display sdl" option still uses a hand-crafted parser for its
> parameters since some of them used underscores which is forbidden
> in QAPI.
Kind of. QAPI indeed requires lower-case-with-hyphens for such names,
but there is an exception mechanism for names with upper
On 5/12/22 12:46, Markus Armbruster wrote:
Commit message nitpick: not sure this is "qapi:". The commit that
introduced "Machine type ... is deprecated" (08fe68244eb) used
"hw/i386:". We commonly use "vl:", "softmmu:", and "softmmu/vl:" for
this file.
Will do.
I wonder if I should already pr
On Wed, May 11, 2022 at 07:11:20PM -0700, Richard Henderson wrote:
> On 5/11/22 15:34, Stafford Horne wrote:
> > In this case I don't see how the tb->flag would be updated, ooh, I guess it
> > would have been set earlier when the TB was generated. Maybe that is what
> > I am
> > missing.
>
> Cor
On 5/12/22 05:10, Alexey Kardashevskiy wrote:
On 5/12/22 06:42, Daniel Henrique Barboza wrote:
On 5/6/22 02:51, Alexey Kardashevskiy wrote:
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Signed-off-by: Alexey Kardashevskiy
Hi Hiroki,
On Thu, May 12, 2022 at 8:57 AM 成川 弘樹 wrote:
>
> Thank you for your fix.
>
> I confirmed that after applying this patch, my intended performance
> improvement by 4c41c69e is still kept in our environment.
Is that equivalent to a formal
Tested-by: Hiroki Narukawa
tag?
> On 2022/05/11
On Thu, May 12, 2022 at 02:24:35PM +0200, Paolo Bonzini wrote:
> On 5/12/22 12:46, Markus Armbruster wrote:
> > Commit message nitpick: not sure this is "qapi:". The commit that
> > introduced "Machine type ... is deprecated" (08fe68244eb) used
> > "hw/i386:". We commonly use "vl:", "softmmu:", a
On Thu, 5 Mar 2020 at 16:52, Eric Auger wrote:
>
> The tests themselves are the same as the ISA device ones.
> Only the main() changes as the "tpm-tis-device" device gets
> instantiated. Also the base address of the device is not
> 0xFED4 anymore but matches the base address of the
> ARM virt
This series enables MTE for kvm guests, if the kernel supports it.
Lightly tested while running under the simulator (the arm64/mte/
kselftests pass... if you wait patiently :)
A new cpu property "mte" (defaulting to on if possible) is introduced;
for tcg, you still need to enable mte at the machin
We need to disable migration, as we do not yet have a way to migrate
the tags as well.
Signed-off-by: Cornelia Huck
---
target/arm/cpu.c | 18 --
target/arm/cpu.h | 4 +++
target/arm/cpu64.c | 78
target/arm/kvm64.c | 5 +++
targ
Signed-off-by: Cornelia Huck
---
tests/qtest/arm-cpu-features.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 5a145273860c..c0be645b1fb0 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/t
On 5/12/22 00:10, Alexey Kardashevskiy wrote:
On 5/12/22 06:42, Daniel Henrique Barboza wrote:
On 5/6/22 02:51, Alexey Kardashevskiy wrote:
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Signed-off-by: Alexey Kardashevski
* Juan Quintela (quint...@redhat.com) wrote:
> In this version:
> - document what protects each field in MultiFDRecv/SendParams
> - calcule page_size once when we start the migration, and store it in
> a field
> - Same for page_count.
> - rebase to latest
> - minor improvements here and there
> -
On 5/12/2022 1:29 PM, Thomas Huth wrote:
External email: Use caution opening links or attachments
From: Matthew Rosato
The v1 uapi is deprecated and will be replaced by v2 at some point;
this patch just tolerates the renaming of uapi fields to reflect
v1 / deprecated status.
Signed-off-by:
On 12/05/2022 12.29, Thomas Huth wrote:
Hi!
The following changes since commit ec11dc41eec5142b4776db1296972c6323ba5847:
Merge tag 'pull-misc-2022-05-11' of git://repo.or.cz/qemu/armbru into
staging (2022-05-11 09:00:26 -0700)
are available in the Git repository at:
https://gitlab.co
On 12/05/2022 15.53, Avihai Horon wrote:
On 5/12/2022 1:29 PM, Thomas Huth wrote:
External email: Use caution opening links or attachments
From: Matthew Rosato
The v1 uapi is deprecated and will be replaced by v2 at some point;
this patch just tolerates the renaming of uapi fields to reflec
Paolo Bonzini writes:
> Signed-off-by: Paolo Bonzini
> ---
> scripts/kvm/vmxcap | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap
> index f140040104..ce27f5e635 100755
> --- a/scripts/kvm/vmxcap
> +++ b/scripts/kvm/vmxcap
> @@ -2
Am 05.05.2022 um 11:47 hat Paolo Bonzini geschrieben:
> common.rc has some complicated logic to find the common.config that
> dates back to xfstests and is completely unnecessary now. Just include
> the contents of the file.
>
> Signed-off-by: Paolo Bonzini
Thanks, applied to the block branch.
On 12/05/2022 10.37, Daniel P. Berrangé wrote:
On Thu, May 12, 2022 at 09:39:29AM +0200, Thomas Huth wrote:
Our support statement for Windows currently talks about "Vista / Server
2008" - which is related to the API of Windows, and this is not easy
to understand for the non-technical users. Addi
On Thu, May 12, 2022 at 02:21:02PM +0800, Longpeng(Mike) wrote:
From: Longpeng
Supports vdpa-dev, we can use the deivce directly:
-M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \
vhost-vdpa-device,vhostdev=/dev/vhost-vdpa-x
Signed-off-by: Longpeng
---
hw/virtio/Kconfig
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