On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
>
>
>
> On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> >
> >
> > On 2/7/2022 7:28 PM, Halil Pasic wrote:
> >> The commit 04ceb61a40 ("virtio: Fail if iommu_platform is requested, but
> >> unsupported") claims to fail the device hotplug when iommu_pl
> From: Alex Williamson
> Sent: Wednesday, April 27, 2022 12:22 AM
> > >
> > > My expectation would be that libvirt uses:
> > >
> > > -object iommufd,id=iommufd0,fd=NNN
> > > -device vfio-pci,fd=MMM,iommufd=iommufd0
> > >
> > > Whereas simple QEMU command line would be:
> > >
> > > -object iomm
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
dif
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++
target/riscv/vector_helper.c| 40 +
2 files changed, 62 insertions(+)
diff --git a/target/riscv/insn_trans/t
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ++
target/riscv/translate.c
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f7
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vect
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 +
target/riscv/vector_helper.c| 20 +++
2 files changed, 64 insertions(+)
diff --git a/target/riscv/insn_trans/tran
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 21e20d47e5..e0fd0e62b3 100644
--- a/t
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 +++
target/riscv/internals.h| 5 +-
target/riscv
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 15 +
target/riscv/vector_helper.c| 443 +---
From: eopXD
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +
target/riscv/vector_helper.c| 30 +++
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
Excerpts from Nicholas Piggin's message of April 21, 2022 12:04 pm:
> Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am:
>> On 4/18/22 17:22, Cédric Le Goater wrote:
>>> On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based
在 2022/3/14 下午3:38, ~eopxd 写道:
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Sorry. My fault. I miss a space when I send Reviewed-by. Maybe you can
update this in the next version with other changes.
Rev
On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
> >
> >
> >
> > On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> > >
> > >
> > > On 2/7/2022 7:28 PM, Halil Pasic wrote:
> > >> The commit 04ceb61a40 ("virtio: Fail if iommu_platform is req
On 4/27/22 17:36, Cédric Le Goater wrote:
Hello Alexey,
On 4/27/22 06:36, Alexey Kardashevskiy wrote:
VFIO-PCI has an "KVM_IRQFD_FLAG_RESAMPLE" optimization for INTx EOI
handling when KVM can unmask PCI INTx (level triggered interrupt) without
switching to the userspace (==QEMU).
Unfortunat
On 4/27/22 10:27, Thomas Huth wrote:
> On 26/04/2022 12.26, Rob Landley wrote:
>> When I cut and paste 80-ish characters of text into the Linux serial
>> console, it
>> reads 16 characters and stops. When I hit space, it reads another 16
>> characters,
>> and if I keep at it will eventually catch
On Thu, Apr 28, 2022 at 12:57 PM Michael S. Tsirkin wrote:
>
> On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> > On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
> > >
> > >
> > >
> > > On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> > > >
> > > >
> > > > On 2/7/2022 7:28 PM, Halil P
On Thu, Apr 28, 2022 at 01:52:46PM +0800, Jason Wang wrote:
> On Thu, Apr 28, 2022 at 12:57 PM Michael S. Tsirkin wrote:
> >
> > On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> > > On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang
> > > wrote:
> > > >
> > > >
> > > >
> > > > On 4/22/202
On 4/28/22 00:41, Rob Landley wrote:
> On 4/27/22 10:27, Thomas Huth wrote:
>> On 26/04/2022 12.26, Rob Landley wrote:
>>> When I cut and paste 80-ish characters of text into the Linux serial
>>> console, it
>>> reads 16 characters and stops. When I hit space, it reads another 16
>>> character
On 4/28/22 07:32, Alexey Kardashevskiy wrote:
On 4/27/22 17:36, Cédric Le Goater wrote:
Hello Alexey,
On 4/27/22 06:36, Alexey Kardashevskiy wrote:
VFIO-PCI has an "KVM_IRQFD_FLAG_RESAMPLE" optimization for INTx EOI
handling when KVM can unmask PCI INTx (level triggered interrupt) without
sw
Queued, thanks. (It only took 30 months; thanks to Ivan Shcherbakov
for bringing it to my attention).
Paolo
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vec
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ++
target/riscv/translate.c
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 15 +
target/riscv/vector_helper.c| 443 +---
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 +
target/riscv/vector_helper.c| 20 +++
2 files changed, 64 insertions(+)
diff --git a/target/riscv/insn_trans/tra
On 4/25/22 00:01, Paul Brook wrote:
The abs1 function in ops_sse.h only works sorrectly when the result fits
in a signed int. This is fine most of the time because we're only dealing
with byte sized values.
However pcmp_elen helper function uses abs1 to calculate the absolute value
of a cpu regi
Hello,
On 4/27/22 08:21, Joel Stanley wrote:
On Tue, 26 Apr 2022 at 12:51, Lucas Mateus Castro(alqotel)
wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch series is an RFC of the Matrix-Multiply Assist (MMA)
instructions implementation from the PowerISA 3.1
These and the VDIV/VMOD imp
On Tue, 12 Apr 2022 14:57:53 +0800
Robert Hoo wrote:
> It should be some typo originally, where in If condition, using bitwise
> and/or, rather than logical and/or.
>
> The resulting change in AML code:
>
> If (((Local6 == Zero) | (Arg0 != Local0)))
> ==>
> If (((Local6 == Zero) || (Arg0 != L
Hello Alexey,
On 4/27/22 06:36, Alexey Kardashevskiy wrote:
VFIO-PCI has an "KVM_IRQFD_FLAG_RESAMPLE" optimization for INTx EOI
handling when KVM can unmask PCI INTx (level triggered interrupt) without
switching to the userspace (==QEMU).
Unfortunately XIVE does not support level interrupts,
Hi
On Wed, Apr 27, 2022 at 12:43 AM Richard Henderson
wrote:
>
> On 4/26/22 02:26, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Signed-off-by: Marc-André Lureau
> > Reviewed-by: Daniel P. Berrangé
> > ---
> > include/qemu/atomic.h| 8 +---
Hi
On Wed, Apr 27, 2022 at 5:08 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 4/26/22 02:27, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Suggested-by: Daniel P. Berrangé
> > Signed-off-by: Marc-André Lureau
> > ---
> > qga/commands-posix.c | 2 +-
On 4/26/2022 9:28 PM, Jason Wang wrote:
在 2022/3/30 14:33, Si-Wei Liu 写道:
Hi,
This patch series attempt to fix a few issues in vhost-vdpa
multiqueue functionality.
Patch #1 is the formal submission for RFC patch in:
https://urldefense.com/v3/__https://lore.kernel.org/qemu-devel/c3e931ee-
Hi,
This patch series attempt to fix a few issues in vhost-vdpa multiqueue
functionality.
Patch #1 and #2 are the formal submission for RFC patch in:
https://lore.kernel.org/qemu-devel/c3e931ee-1a1b-9c2f-2f59-cb4395c23...@oracle.com/
Patch #3 through #5 are obviously small bug fixes. Please fin
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when needed.
Fixes: 22288f
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >=
dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
0 0x7f8ce3ff3387 in
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev's.
To fix it, send
vhost_net_start() missed a corresponding stop_one() upon error from
vhost_set_vring_enable(). While at it, make the error handling for
err_start more robust. No real issue was found due to this though.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
hw/net/vhost_net.c | 4 +++-
1 file change
... such that no memory leaks on dangling net clients in case of
error.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 1e9fe47..df1e69e 100644
--- a/net/vhost-vd
On Wed, Apr 27, 2022 at 4:30 PM Si-Wei Liu wrote:
>
>
>
> On 4/26/2022 9:28 PM, Jason Wang wrote:
> >
> > 在 2022/3/30 14:33, Si-Wei Liu 写道:
> >> Hi,
> >>
> >> This patch series attempt to fix a few issues in vhost-vdpa
> >> multiqueue functionality.
> >>
> >> Patch #1 is the formal submission for
On Mittwoch, 27. April 2022 04:45:45 CEST Akihiko Odaki wrote:
> Signed-off-by: Akihiko Odaki
> ---
> hw/9pfs/9p-local.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/9pfs/9p-local.c b/hw/9pfs/9p-local.c
> index d42ce6d8b82..def8afdb4d6 100644
> --- a/hw/9pfs/9p-loc
On Tue, Apr 26, 2022 at 08:06:56PM -0300, Leonardo Bras wrote:
> Implement zero copy send on nocomp_send_write(), by making use of QIOChannel
> writev + flags & flush interface.
>
> Change multifd_send_sync_main() so flush_zero_copy() can be called
> after each iteration in order to make sure all
On Wed, Apr 27, 2022 at 10:34:24AM +0200, LABBE Corentin wrote:
> Le Mon, Apr 25, 2022 at 03:29:32PM +0100, Daniel P. Berrangé a écrit :
> > On Mon, Apr 25, 2022 at 03:03:11PM +0200, LABBE Corentin wrote:
> > > diff --git a/crypto/hash-nettle.c b/crypto/hash-nettle.c
> > > index 1ca1a41062..b9342b4
Le Mon, Apr 25, 2022 at 03:29:32PM +0100, Daniel P. Berrangé a écrit :
> On Mon, Apr 25, 2022 at 03:03:11PM +0200, LABBE Corentin wrote:
> > diff --git a/crypto/hash-nettle.c b/crypto/hash-nettle.c
> > index 1ca1a41062..b9342b4fe1 100644
> > --- a/crypto/hash-nettle.c
> > +++ b/crypto/hash-nettle.c
On Fri, Apr 1, 2022 at 11:59 AM Zhang Chen wrote:
>
> If the checkpoint occurs when the guest finishes restarting
> but has not started running, the runstate_set() may reject
> the transition from COLO to PRELAUNCH with the crash log:
>
> {"timestamp": {"seconds": 1593484591, "microseconds": 26605
On Tue, Apr 26, 2022 at 08:06:55PM -0300, Leonardo Bras wrote:
> Since d48c3a0445 ("multifd: Use a single writev on the send side"),
> sending the header packet and the memory pages happens in the same
> writev, which can potentially make the migration faster.
>
> Using channel-socket as example,
Hi, all
I just found that when the linux kernel saves the current x29 and x30 at the
new stack bottom, (it usually does that when entering a function)
The stored x30 value (lr register) has it top 16bits altered to some strange
value. So if I fix those top 16bits to 0x in the stack, and
As of now, cryptographic instructions ISAR fields are never cleared so
we can end up with a cpu with cryptographic instructions but no
floating-point/neon instructions which is not a possible configuration
according to ARM specifications.
In QEMU, we have 3 kinds of cpus regarding cryptographic in
On 4/27/2022 1:38 AM, Jason Wang wrote:
On Wed, Apr 27, 2022 at 4:30 PM Si-Wei Liu wrote:
On 4/26/2022 9:28 PM, Jason Wang wrote:
在 2022/3/30 14:33, Si-Wei Liu 写道:
Hi,
This patch series attempt to fix a few issues in vhost-vdpa
multiqueue functionality.
Patch #1 is the formal submissio
On 4/25/22 00:01, Paul Brook wrote:
+/* If a VEX prefix is used then it must have V=b */
+#define CHECK_AVX_V0(s) do { \
+CHECK_AVX(s); \
+if ((s->prefix & PREFIX_VEX) && (s->vex_v != 0)) \
+goto illegal_op; \
+} while (0)
+
What do you think about
#define CHECK_AVX(s,
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> From: Mark Kanda
>
> Introduce QMP support for querying stats. Provide a framework for adding new
> stats and support for the following commands:
>
> - query-stats
> Returns a list of all stats per target type (only VM and vCPU to start), with
> add
Hi
On Wed, Apr 27, 2022 at 5:15 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 4/26/22 02:27, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Suggested-by: Daniel P. Berrangé
> > Signed-off-by: Marc-André Lureau
> > ---
> > net/tap-bsd.c
Hi folks,
Sorry for many emails.
I just found out by turning CONFIG_ARM64_PTR_AUTH off in armv8.3 when building
linux, I can avoid this problem.
(I noticed the instruction ‘pacia’ in the function assembly code)
Thank you.
Chan Kim
From: Chan Kim
Sent: Wednesday, April 27, 2022 6:05 PM
T
> -Original Message-
> From: Jason Wang
> Sent: Wednesday, April 27, 2022 4:57 PM
> To: Zhang, Chen
> Cc: Li Zhijian ; qemu-dev de...@nongnu.org>; Like Xu
> Subject: Re: [PATCH V2 1/4] softmmu/runstate.c: add RunStateTransition
> support form COLO to PRELAUNCH
>
> On Fri, Apr 1, 2022
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