On Fri, Apr 22, 2022 at 01:06:25PM +0200, Paolo Bonzini wrote:
> On 4/22/22 12:56, Chao Peng wrote:
> > /* memfile notifier flags */
> > #define MFN_F_USER_INACCESSIBLE 0x0001 /* memory allocated in
> > the file is inaccessible from userspace (e.g. read/write/mmap) */
> >
On Fri, Apr 22, 2022 at 10:43:50PM -0700, Vishal Annapurve wrote:
> On Thu, Mar 10, 2022 at 6:09 AM Chao Peng wrote:
> >
> > From: "Kirill A. Shutemov"
> >
> > Introduce a new memfd_create() flag indicating the content of the
> > created memfd is inaccessible from userspace through ordinary MMU
>
The 'g_get_real_time' returns the number of microseconds since January
1, 1970 UTC, but 'g_date_time_new_from_unix_utc' needs the number of
seconds, so it will cause the invalid time input:
(process:279642): GLib-CRITICAL (recursed) **: g_date_time_format: assertion
'datetime != NULL' failed
Cal
The 'g_get_real_time' returns the number of microseconds since January
1, 1970 UTC, but 'g_date_time_new_from_unix_utc' needs the number of
seconds, so it will cause the invalid time input:
(process:279642): GLib-CRITICAL (recursed) **: g_date_time_format: assertion
'datetime != NULL' failed
Cal
Hi, I’m new to qemu (and even bug-reporting) so apologies in advance…
The MASK field in DBGWCRx_EL1 is **5** bits wide [28:24].
In target/arm/kvm64.c I found the line:
wp.wcr = deposit32(wp.wcr, 24, 4, bits); // ie **4** bits
instead of **5**
If it’s not copying (or calculating
Sorry, I need to correct my previous post:
If I set
DBGWVR0_EL1 = 1<<23 // ie. 0x0080
and
DBGWCR0_EL1 = 0x17<<24 | 0xFF<<5 | 0b11<<3 | 0b11<<1 | 0b1<<0 // ie.
MASK = 23 = 0b10111
and then access memory [0x0080007F] I get a watchpoint exception. (ie.
watc
On Sun, Apr 24, 2022 at 3:27 PM Haiyue Wang wrote:
> The 'g_get_real_time' returns the number of microseconds since January
> 1, 1970 UTC, but 'g_date_time_new_from_unix_utc' needs the number of
> seconds, so it will cause the invalid time input:
>
> (process:279642): GLib-CRITICAL (recursed) **:
On Sat, Apr 23, 2022 at 5:09 PM Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
>
Reviewed-by: Marc-André Lureau
> ---
> v1->v2: fix get_option('optimization') comparison to use a string
>
> configure | 20
> meson.build | 8
> 2 files changed, 8 inserti
On 21/04/2022 23:00, BALATON Zoltan wrote:
On Thu, 21 Apr 2022, Richard Henderson wrote:
On 4/21/22 08:29, Mark Cave-Ayland wrote:
You need (1 << SCSI_DISK_QUIRK_MODE_PAGE_APPLE) instead.
Doh, you're absolutely right. I believe the current recommendation is to use the
BIT() macro in these c
On 21/04/2022 07:51, Mark Cave-Ayland wrote:
Here are the next set of patches from my ongoing work to allow the q800
machine to boot MacOS related to SCSI devices.
The first patch implements a dummy FORMAT UNIT command which is used by
the Apple HD SC Setup program when preparing an empty disk
Since the MacOS SCSI implementation is quite old (and Apple added some firmware
customisations to their drives for m68k Macs) there is need to add a mechanism
to correctly handle Apple-specific quirks.
Add a new quirks bitmap to SCSIDiskState that can be used to enable these
features as required.
Here are the next set of patches from my ongoing work to allow the q800
machine to boot MacOS related to SCSI devices.
The first patch implements a dummy FORMAT UNIT command which is used by
the Apple HD SC Setup program when preparing an empty disk to install
MacOS.
Patch 2 adds a new quirks bit
When initialising a drive ready to install MacOS, Apple HD SC Setup first
attempts
to format the drive. Add a simple FORMAT UNIT command which simply returns
success
to allow the format to succeed.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/scsi-disk.c | 4
hw/scsi/trace-events | 1 +
2
When A/UX configures the CDROM device it sends a truncated MODE SELECT request
for page 1 (MODE_PAGE_R_W_ERROR) which is only 6 bytes in length rather than
10. This seems to be due to bug in Apple's code which calculates the CDB message
length incorrectly.
According to [1] this truncated request i
By default quirk_mode_sense_rom_force_dbd should be enabled for all scsi-cd
devices
connected to the q800 machine to correctly report the CDROM block descriptor
back
to A/UX.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/m68k/q800.c b
During SCSI bus enumeration A/UX sends a MODE SENSE command to the CDROM and
expects the response to include a block descriptor. As per the latest SCSI
documentation, QEMU currently force-disables the block descriptor for CDROM
devices but the A/UX driver expects the block descriptor to always be
r
One of the mechanisms MacOS uses to identify drives compatible with MacOS is to
send a custom MODE SELECT command for page 0x30 to the drive. The response to
this is a hard-coded manufacturer string which must match in order for the
drive to be usable within MacOS.
Add an implementation of the MOD
By default quirk_mode_page_apple_vendor should be enabled for all scsi-hd
devices
connected to the q800 machine to enable MacOS to detect and use them.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
in
The Apple HD SC Setup program uses a SCSI INQUIRY command to check that any SCSI
hard disks detected match a whitelist of vendors and products before allowing
the "Initialise" button to prepare an empty disk.
Add known-good default vendor and product information using the existing
compat_prop mech
Ping.
Hi, David and Peter, how do you think this patchset?
Is it suitable for queueing ? or is there still something need to be
done ?
Yong
在 2022/4/1 1:49, huang...@chinatelecom.cn 写道:
From: Hyman Huang(黄勇)
This is v22 of dirtylimit series.
The following is the history of the patchset, s
A/UX sends a MODE_PAGE_R_W_ERROR command with the AWRE bit set to 0 when
enumerating
CDROM drives. Since the bit is currently hardcoded to 1 then indicate that the
AWRE
bit can be changed (even though we don't care about the value) so that
the MODE_PAGE_R_W_ERROR page can be set successfully.
Si
Whilst CDROM drives usually have a 2048 byte sector size, older drives have the
ability to switch between 2048 byte and 512 byte sector sizes by specifying a
block descriptor in the MODE SELECT command.
If a MODE SELECT block descriptor is provided, update the scsi-cd device block
size with the pr
On Fri, Apr 22, 2022, at 3:56 AM, Chao Peng wrote:
> On Tue, Apr 05, 2022 at 06:03:21PM +, Sean Christopherson wrote:
>> On Tue, Apr 05, 2022, Quentin Perret wrote:
>> > On Monday 04 Apr 2022 at 15:04:17 (-0700), Andy Lutomirski wrote:
> Only when the register succeeds, the fd is
> c
The MacOS CDROM driver uses a SCSI INQUIRY command to check that any SCSI CDROMs
detected match a whitelist of vendors and products before adding them to the
list of available devices.
Add known-good default vendor and product information using the existing
compat_prop mechanism so the user doesn'
On Samstag, 23. April 2022 06:33:50 CEST Akihiko Odaki wrote:
> On 2022/04/22 23:06, Christian Schoenebeck wrote:
> > On Freitag, 22. April 2022 04:43:40 CEST Akihiko Odaki wrote:
> >> On 2022/04/22 0:07, Christian Schoenebeck wrote:
> >>> mknod() on macOS does not support creating sockets, so dive
Le Thu, Apr 21, 2022 at 01:38:00PM +0100, Peter Maydell a écrit :
> On Sun, 10 Apr 2022 at 20:12, Corentin Labbe wrote:
> >
> > From: Corentin LABBE
> >
> > The Allwinner A10 has a cryptographic offloader device which
> > could be easily emulated.
> > The emulated device is tested with Linux only
Hi, Yong,
On Mon, Apr 25, 2022 at 12:52:45AM +0800, Hyman wrote:
> Ping.
> Hi, David and Peter, how do you think this patchset?
> Is it suitable for queueing ? or is there still something need to be done ?
It keeps looking good to me in general, let's see whether the maintainers
have any commen
Once all the code is in place, 256 bit vector helpers will be generated by
including ops_sse.h a third time with SHIFT=2.
The first bit of support for this is to define a YMM_ONLY macro for code that
only apples to 256 bit vectors. XXM_ONLY code will be executed for both
128 and 256 bit vectors.
The abs1 function in ops_sse.h only works sorrectly when the result fits
in a signed int. This is fine most of the time because we're only dealing
with byte sized values.
However pcmp_elen helper function uses abs1 to calculate the absolute value
of a cpu register. This incorrectly truncates to 32
The DPPS (Dot Product) instruction is defined to first sum pairs of
intermediate results, then sum those values to get the final result.
i.e. (A+B)+(C+D)
We incrementally sum the results, i.e. ((A+B)+C)+D, which can result
in incorrect rouding.
For consistency, also remove the redundant (but harm
Add a flags field each row in sse_op_table1.
Initially this is only used as a replacement for the magic
SSE_SPECIAL and SSE_DUMMY pointers, the other flags will become relevant
as the rest of the AVX implementation is built out.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 316 ++
Reject invalid VEX encodings on MMX instructions.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 5335b86c01..66ba690b7d 100644
--- a/target/i
Add a new hflag bit to determine whether AVX instructions are allowed
Signed-off-by: Paul Brook
---
target/i386/cpu.h| 3 +++
target/i386/helper.c | 12
target/i386/tcg/fpu_helper.c | 1 +
3 files changed, 16 insertions(+)
diff --git a/target/i386/cpu.h b/targ
Add a convenience macro to get the address of an xmm_regs element within
CPUX86State.
This was originally going to be the basis of an implementation that broke
operations into 128 bit chunks. I scrapped that idea, so this is now a purely
cosmetic change. But I think a worthwhile one - it reduces t
Add CHECK_AVX* macros, and use them to validate VEX encoded AVX instructions
All AVX instructions require both CPU and OS support, this is encapsulated
by HF_AVX_EN.
Some also require specific values in the VEX.L and VEX.V fields.
Some (mostly integer operations) also require AVX2
Signed-off-by:
Add a flags field each row in sse_op_table6 and sse_op_table7.
Initially this is only used as a replacement for the magic
SSE41_SPECIAL pointer. The other flags will become relevant
as the rest of the avx implementation is built out.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c |
Rewrite the vector shift helpers in preperation for AVX support (3 operand
form and 256 bit vectors).
For now keep the existing two operand interface.
No functional changes to existing helpers.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 250 ++
The AVX variants of the BLENDV instructions use a different opcode prefix
to support the additional operands. We already modified the helper functions
in anticipation of this.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 18 --
1 file changed, 16 insertions(+), 2 d
Decoding these is a bit messy, but at least the integer and float variants
have the same semantics once decoded.
We don't try and be clever with the load forms, instead load the whole
vector then mask out the elements we want.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 48
Some potentially surprising details when comparing vpermilpd v.s. vpermilps,
but overall pretty straightforward.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 82
target/i386/ops_sse_header.h | 4 ++
target/i386/tcg/translate.c | 4 ++
3 fil
Perpare the horizontal atithmetic vector helpers for AVX
These currently use a dummy Reg typed variable to store the result then
assign the whole register. This will cause 128 bit operations to corrupt
the upper half of the register, so replace it with explicit temporaries
and element assignments.
This is semantically eqivalent to VBLENDPS.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 95ecdea8fe..73f3842c36 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i
Rewrite the "simple" vector integer helpers in preperation for AVX support.
While the current code is able to use the same prototype for unary
(a = F(b)) and binary (a = F(b, c)) operations, future changes will cause
them to diverge.
No functional changes to existing helpers
Signed-off-by: Paul
The catch here is that these are whole vector operations (not independent 128
bit lanes). We abuse the SSE_OPF_SCALAR flag to select the memory operand
width appropriately.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 51
target/i386/ops_sse_h
We don't have any migration concerns for usermode emulation, so we may
as well enable all available CPU features by default.
Signed-off-by: Paul Brook
---
linux-user/x86_64/target_elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/x86_64/target_elf.h b/linux-use
These helpers need to take special care to avoid overwriting source values
before the wole result has been calculated. Currently they use a dummy
Reg typed variable to store the result then assign the whole register.
This will cause 128 bit operations to corrupt the upper half of the register,
so
The use the same opcode as EMMS, which I guess makes some sort of sense.
Fairly strightforward other than that.
If we were wanting to optimize out gen_clear_ymmh then this would be one of
the starting points.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 48 ++
Fixup various vector helpers that either trivially exten to 256 bit,
or don't have 256 bit variants.
No functional changes to existing helpers
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 159 --
1 file changed, 139 insertions(+), 20 deletions(-)
Update ops_sse_helper.h ready for 256 bit AVX helpers
Signed-off-by: Paul Brook
---
target/i386/ops_sse_header.h | 67 +---
1 file changed, 40 insertions(+), 27 deletions(-)
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 203afbb5a1
Handle 3DNOW instructions early to avoid complicating the AVX logic.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 64f0
AVX includes additional a more extensive set of comparison predicates,
some of some of which our softfloat implementation does not expose directly.
Rewrite the helpers in terms of floatN_compare
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 149 ---
Make the dpps and dppd helpers AVX-ready
I can't see any obvious reason why dppd shouldn't work on 256 bit ymm
registers, but both AMD and Intel agree that it's xmm only.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 54 ---
1 file changed, 46 ins
These are scatter load instructions that need introduce a new "Vector SIB"
encoding. Also a bit of hair to handle different index sizes and scaling
factors, but overall the combinatorial explosion doesn't end up too bad.
The other thing of note is probably that these also modify the mask operand.
Include sha512 built with avx[2] in the tcg tests.
Signed-off-by: Paul Brook
---
tests/tcg/i386/Makefile.target | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target
index eb06f7eb89..a0335fff6d 100644
--- a/te
Include AVX and AVX2 in the guest cpuid features supported by TCG
Signed-off-by: Paul Brook
---
target/i386/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 99343be926..bd35233d5b 100644
--- a/target/i386/cpu.c
+++ b/ta
A set of shuffle operations that operate on complete 256 bit registers.
The integer and floating point variants have identical semantics.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 73
target/i386/ops_sse_header.h | 3 ++
target/i386/tcg/tr
Make the AES vector helpers AVX ready
No functional changes to existing helpers
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 63 ++--
target/i386/ops_sse_header.h | 55 ++-
2 files changed, 85 insertions(+), 33 deletion
128-bit vinsert/vextract instructions. The integer and loating point variants
have the same semantics.
This is where we encounter an instruction encoded with VEX.L == 1 and
a 128 bit (xmm) destination operand.
Signed-off-by: Paul Brook
---
target/i386/tcg/translate.c | 78 ++
Enable translation of VEX encoded AVX instructions.
The big change is the addition of an additional register operand in the VEX.V
field. This is usually (but not always!) used to explictly encode the
first source operand.
The changes to ops_sse.h and ops_sse_header.h are purely mechanical, with
VEX encoded instructions that write to a (128 bit) xmm register clear the
rest (upper half) of the corresonding (256 bit) ymm register.
When legacy SSE encodings are used the rest of the ymm register is left
unchanged.
Add a utility fuction so that we don't have to keep duplicating this logic.
Si
Prepare the "easy" floating point vector helpers for AVX
No functional changes to existing helpers.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 144 ++
1 file changed, 119 insertions(+), 25 deletions(-)
diff --git a/target/i386/ops_sse.h b/targ
All the work for the helper functions is already done, we just need to build
them, and a few macro tweaks to poulate the lookup tables.
For sse_op_table6 and sse_op_table7 we use #defines to fill in the entries
where and opcode only supports one vector size, rather than complicating the
main table
For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of
floating point helpers. Add the register type suffix to the existing
*PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors)
No functional changes.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h
Noting special here
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 28
target/i386/ops_sse_header.h | 2 ++
target/i386/tcg/translate.c | 2 ++
3 files changed, 32 insertions(+)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 8f2bd4
Make the pclmulqdq helper AVX ready
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 9f388b02b9..b7100fdce1 100644
--- a/target/i386/ops_sse
More perparatory work for AVX support in various integer vector helpers
No functional changes to existing helpers.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 133 +-
1 file changed, 104 insertions(+), 29 deletions(-)
diff --git a/target/i386/o
These use the W bit to encode the operand width, but otherwise fairly
straightforward.
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h| 17 +
target/i386/ops_sse_header.h | 6 ++
target/i386/tcg/translate.c | 17 +
3 files changed, 40 insertions(
Rewrite the blendv helpers so that they can easily be extended to support
the AVX encodings, which make all 4 arguments explicit.
No functional changes to the existing helpers
Signed-off-by: Paul Brook
---
target/i386/ops_sse.h | 119 +-
1 file changed, 6
ping
https://patchew.org/QEMU/20220321055618.4026-1-lu@verisilicon.com/
Please help review the patch.
Thanks.
B.R.
-邮件原件-
发件人: Gao, Lu
发送时间: Monday, March 21, 2022 1:56 PM
收件人: qemu-devel@nongnu.org
抄送: Gao, Lu; Wen, Jianxian; Philippe Mathieu-Daudé; Bin Meng; open list:SD
(Secure
When the CPU-to-NUMA association isn't provided by user, the default NUMA
node ID for the specific CPU is returned from virt_get_default_cpu_node_id().
Unfortunately, the default NUMA node ID breaks socket boundary and leads to
the broken CPU topology warning message in Linux guest. This series int
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA node.
* hw/core/machine.c::machine_numa_finish_cpu_
The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thrad-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread I
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP configuration when the CPU topology
is populated. The die
When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.
For example, the following wa
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of bui
Nicolas Saenz Julienne writes:
> 'event-loop-base' provides basic property handling for all 'AioContext'
> based event loops. So let's define a new 'MainLoopClass' that inherits
> from it. This will permit tweaking the main loop's properties through
> qapi as well as through the command line usin
Nicolas Saenz Julienne writes:
> As discussed on the previous RFC[1] the thread-pool's dynamic thread
> management doesn't play well with real-time and latency sensitive
> systems. This series introduces a set of controls that'll permit
> achieving more deterministic behaviours, for example by fi
Gautam Agrawal writes:
> This patch is in regards to this
> issue:https://gitlab.com/qemu-project/qemu/-/issues/581#.
> A global boolean variable "vga_interface_created"(declared in
> softmmu/globals.c)
> has been used to track the creation of vga interface. If the vga flag is
> passed in the
The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f:
Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into
staging (2022-04-21 18:48:18 -0700)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/kraxel-20220425-pull-request
fo
From: Kshitij Suri
Libpng is only detected if VNC is enabled currently. This patch adds a
generalised png option in the meson build which is aimed to replace use of
CONFIG_VNC_PNG with CONFIG_PNG.
Signed-off-by: Kshitij Suri
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220408071336.99839-2-
From: Carwyn Ellis
In certain circumstances, typically when there is lots changing on the
screen, updates will be discarded resulting in garbled output.
This change simplifies the traversal of the display update FIFO queue
when applying updates. We just track the queue length and iterate up to
t
From: Vladimir Sementsov-Ogievskiy
Add simple test-case for new display-update qmp command.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220401143936.356460-4-vsement...@openvz.org>
Signed-off-by: Gerd Hoffmann
---
tests/avocado/vnc.py | 63 +
From: Kshitij Suri
Currently screendump only supports PPM format, which is un-compressed. Added
a "format" parameter to QMP and HMP screendump command to support PNG image
capture using libpng.
QMP example usage:
{ "execute": "screendump", "arguments": { "filename": "/tmp/image",
"format":"png"
From: Vladimir Sementsov-Ogievskiy
Add possibility to change addresses where VNC server listens for new
connections. Prior to 6.0 this functionality was available through
'change' qmp command which was deleted.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Daniel P. Berrangé
Message
From: Vladimir Sementsov-Ogievskiy
Let's use SocketAddressList instead of dynamic arrays.
Benefits:
- Automatic cleanup: don't need specific freeing function and drop
some gotos.
- Less indirection: no triple asterix anymore!
- Prepare for the following commit, which will reuse new interfac
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