[PULL 44/53] hyperv: SControl is optional to enable SynIc

From: Jon Doron SynIc can be enabled regardless of the SControl mechanisim which can register a GSI for a given SintRoute. This behaviour can achived by setting enabling SIMP and then the guest will poll on the message slot. Once there is another message pending the host will set the message sl

[PULL 48/53] s390x: follow qdev tree to detect SCSI device on a CCW bus

Do not make assumptions on the parent type of the SCSIDevice, instead use object_dynamic_cast all the way up to the CcwDevice. This is cleaner because there is no guarantee that the bus is on a virtio-scsi device; that is only the case for the default configuration of QEMU's s390x target. Reviewe

[PULL 38/53] build-sys: simplify AF_VSOCK check

From: Marc-André Lureau The current test checks more than AF_VSOCK availability, and doesn't need to be that long. Since its introduction in Linux in 2013, AF_VSOCK came with linux/vm_sockets.h for sockaddr_vm, let's check that. We could even go back to the initial configure-less approach propo

[PULL 33/53] Move CPU softfloat unions to cpu-float.h

From: Marc-André Lureau The types are no longer used in bswap.h since commit f930224fffe ("bswap.h: Remove unused float-access functions"), there isn't much sense in keeping it there and having a dependency on fpu/. Signed-off-by: Marc-André Lureau Message-Id: <20220323155743.1585078-29-marcand

[PULL 50/53] virtio-ccw: move device type declarations to .c files

Signed-off-by: Paolo Bonzini --- hw/s390x/vhost-scsi-ccw.c | 9 +++ hw/s390x/vhost-vsock-ccw.c| 9 +++ hw/s390x/virtio-ccw-9p.c | 9 +++ hw/s390x/virtio-ccw-balloon.c | 9 +++ hw/s390x/virtio-ccw-blk.c | 9 +++ hw/s390x/virtio-ccw-crypto.c | 9 +++ hw/s390x/virtio-cc

[PULL 35/53] qga: remove explicit environ argument from exec/spawn

From: Marc-André Lureau Environment is implicitly inherited from the current process "environ" variable for execl() or g_spawn_sync(), no need to be explicit about it. Signed-off-by: Marc-André Lureau Reviewed-by: Richard Henderson Message-Id: <20220323155743.1585078-31-marcandre.lur...@redhat

[PULL 30/53] include: move qemu_get_vm_name() to sysemu.h

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Message-Id: <20220323155743.1585078-26-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini --- audio/audio.c | 2 +- block/iscsi.c | 2 +- include/qemu-common.h | 2 -- include/sysemu/sysemu.h | 2 ++ stubs/ge

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Tue, Apr 19, 2022 at 1:27 PM Anup Patel wrote: > On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis > wrote: > > > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > > > From: Frank Chang > > > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > > -cpu command line option

[PULL 46/53] hyperv: Add support to process syndbg commands

From: Jon Doron SynDbg commands can come from two different flows: 1. Hypercalls, in this mode the data being sent is fully encapsulated network packets. 2. SynDbg specific MSRs, in this mode only the data that needs to be transfered is passed. Signed-off-by: Jon Doron Reviewed-by: Emanue

[PULL 42/53] thread-posix: implement Semaphore with QemuCond and QemuMutex

From: "Longpeng(Mike)" Now that QemuSemaphore is implemented through pthread_cond_t only, we can use QemuCond and QemuMutex to make the code smaller. Features such as mutex tracing and CLOCK_MONOTONIC timedwait are supported in qemu-sem naturally. Signed-off-by: Longpeng(Mike) Message-Id: <202

[PULL 51/53] virtio-ccw: do not include headers for all virtio devices

Signed-off-by: Paolo Bonzini --- hw/s390x/ipl.c | 3 +++ hw/s390x/s390-virtio-ccw.c | 1 + hw/s390x/virtio-ccw.c | 2 ++ hw/s390x/virtio-ccw.h | 16 4 files changed, 6 insertions(+), 16 deletions(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 2dcc

[PULL 43/53] thread-posix: optimize qemu_sem_timedwait with zero timeout

In this case there is no need to call pthread_cond_timedwait; the function is just a trywait and waiting on the condition variable would always time out. Signed-off-by: Paolo Bonzini --- util/qemu-thread-posix.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/util/qem

[PATCH v3 5/6] hw/riscv: virt: Add device plug support

From: Alistair Francis Add support for plugging in devices, this was tested with the TPM device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/riscv/virt.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/hw/riscv/virt.c b/hw/ris

[PATCH v3 6/6] hw/riscv: Enable TPM backends

From: Alistair Francis Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board. This was tested by first creating an emulated TPM device: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock Then launching QEMU w

[PULL 45/53] hyperv: Add definitions for syndbg

From: Jon Doron Add all required definitions for hyperv synthetic debugger interface. Signed-off-by: Jon Doron Reviewed-by: Emanuele Giuseppe Esposito Message-Id: <20220216102500.692781-3-ari...@gmail.com> Signed-off-by: Paolo Bonzini --- include/hw/hyperv/hyperv-proto.h | 52 +++

[PATCH v3 1/6] hw/riscv: virt: Add a machine done notifier

From: Alistair Francis Move the binary and device tree loading code to the machine done notifier. This allows us to prepare for editing the device tree as part of the notifier. This is based on similar code in the ARM virt machine. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias

[PULL 36/53] Remove qemu-common.h include from most units

From: Marc-André Lureau Signed-off-by: Marc-André Lureau Message-Id: <20220323155743.1585078-33-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini --- accel/hvf/hvf-all.c | 1 - accel/tcg/cpu-exec.c | 1 - accel/tcg/tcg-accel-ops-icount.c

[PATCH v3 2/6] hw/core: Move the ARM sysbus-fdt to core

From: Alistair Francis The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices. The RISC-V virt machine can also benefit from this, so move the code to the core directory. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias

Re: [PULL 01/53] qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities

Thanks Paolo. On 19/04/2022 8:50, Paolo Bonzini wrote: > From: Dov Murik > > Add a new field 'cpu0-id' to the response of query-sev-capabilities QMP > command. The value of the field is the base64-encoded unique ID of CPU0 > (socket 0), which can be used to retrieve the signed CEK of the CPU fr

[PATCH v3 4/6] hw/riscv: virt: Add support for generating platform FDT entries

From: Alistair Francis Similar to the ARM virt machine add support for adding device tree entries for dynamically created devices. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/riscv/virt.c | 25 + 1 file changed, 25 insertions(+) diff --git a/

[PULL 53/53] target/i386: Remove unused XMMReg, YMMReg types and CPUState fields

From: Peter Maydell In commit b7711471f5 in 2014 we refactored the handling of the x86 vector registers so that instead of separate structs XMMReg, YMMReg and ZMMReg for representing the 16-byte, 32-byte and 64-byte width vector registers and multiple fields in the CPU state, we have a single typ

[PATCH v3 3/6] hw/riscv: virt: Create a platform bus

From: Alistair Francis Create a platform bus to allow dynamic devices to be connected. This is based on the ARM implementation. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- include/hw/riscv/virt.h | 7 - hw/riscv/virt.c | 68 +

[PATCH v2] hw/nvme: allow to pass a memory backend object for the CMB

Adds the optional -cmbdev= option that takes a QEMU memory backend -object to be used to for the CMB (Controller Memory Buffer). This option takes precedence over cmb_size_mb= if both used. (The size will be deduced from the memory backend option). Signed-off-by: Rick Wertenbroek --- hw/nvme/ctrl

[PULL 52/53] target/i386: do not access beyond the low 128 bits of SSE registers

The i386 target consolidates all vector registers so that instead of XMMReg, YMMReg and ZMMReg structs there is a single ZMMReg that can fit all of SSE, AVX and AVX512. When TCG copies data from and to the SSE registers, it uses the full 64-byte width. This is not a correctness issue because TCG

Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Tue, Apr 19, 2022 at 2:00 PM Frank Chang wrote: > On Tue, Apr 19, 2022 at 1:27 PM Anup Patel > wrote: > >> On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis >> wrote: >> > >> > On Fri, Apr 15, 2022 at 7:37 PM wrote: >> > > >> > > From: Frank Chang >> > > >> > > Allow user to set core's mar

Re: [PATCH v1 33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

On 2022/4/18 下午10:39, Richard Henderson wrote: On 4/18/22 02:14, yangxiaojuan wrote: Hi, Richard On 2022/4/18 上午11:15, Richard Henderson wrote: On 4/15/22 02:40, Xiaojuan Yang wrote: +static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask, +   int level,

Re: [PATCH 0/4] target/rx: Track PSW.U in tb->flags

On Mon, 18 Apr 2022 01:51:26 +0900, Richard Henderson wrote: > > This is a follow up to Kawada-san's patch for the problem > of a missed update to the stack pointer in CLRPSW/SETPSW. > This fixes the problem without movcond by tracking the > current state of PSW.U within the TB. > > > r~ > > >

[PULL 49/53] virtio-ccw: move vhost_ccw_scsi to a separate file

Remove unecessary use of #ifdef CONFIG_VHOST_SCSI, instead just use a separate file and a separate rule in meson.build. Reviewed-by: Thomas Huth Signed-off-by: Paolo Bonzini --- hw/s390x/meson.build | 1 + hw/s390x/vhost-scsi-ccw.c | 64 ++ hw/s390x/v

Re: [PATCH 2/2] target/riscv: Mark amo insns during translation

On Thu, Apr 7, 2022 at 11:17 PM Alistair Francis wrote: > > On Fri, Apr 1, 2022 at 11:04 PM Richard Henderson > wrote: > > > > Atomic memory operations perform both reads and writes as part > > of their implementation, but always raise write faults. > > > > Use TARGET_INSN_START_EXTRA_WORDS to ma

[PATCH v3 0/6] hw/riscv: Add TPM support to the virt board

From: Alistair Francis This series adds support for connecting TPM devices to the RISC-V virt board. This is similar to how it works for the ARM virt board. This was tested by first creating an emulated TPM device: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unix

RE: Question about direct block chaining

> -Original Message- > From: Richard Henderson > Sent: Monday, April 18, 2022 10:38 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: Philippe Mathieu-Daudé > Subject: Re: Question about direct block chaining > > On 4/18/22 07:54, Taylor Simpson wrote: > > I implemented both approa

Re: [PATCH v1 25/43] target/loongarch: Add LoongArch CSR instruction

On 2022/4/16 上午9:04, Richard Henderson wrote: On 4/15/22 02:40, Xiaojuan Yang wrote: ... +void  helper_csr_update(CPULoongArchState *env, target_ulong new_val, +    target_ulong csr_offset) +{ +    uint64_t *csr = (void *)env + csr_offset; + +    *csr = new_val; +} This f

Re: XIVE VFIO kernel resample failure in INTx mode under heavy load

Tested on POWER9 with a passed through XHCI host and "-append pci=nomsi" and "-machine pseries,ic-mode=xics,kernel_irqchip=on" (and s/xics/xive/). ok. This is deactivating the default XIVE (P9+) mode at the platform level, hence forcing the XICS (P8) mode in a POWER9 guest running on a POWER9 h

[Bug 1795799] Re: Cirrus video, graphical corruption, bad fonts

FWIW, issue has been re-opened here: https://gitlab.com/qemu- project/qemu/-/issues/988 ** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #988 https://gitlab.com/qemu-project/qemu/-/issues/988 -- You received this bug notification because you are a member of qemu- devel-ml, which is s

Re: [PATCH v7 12/17] vfio-user: IOMMU support for remote device

On Wed, 13 Apr 2022 15:08:33 -0400 Peter Xu wrote: > On Wed, Apr 13, 2022 at 04:37:35PM +0200, Igor Mammedov wrote: > > On Thu, 31 Mar 2022 08:41:01 -0400 > > Peter Xu wrote: > > > > > On Thu, Mar 31, 2022 at 10:47:33AM +0100, Stefan Hajnoczi wrote: > > > > On Wed, Mar 30, 2022 at 01:13:03P

Re: [PATCH v5 4/4] hw/acpi/aml-build: Use existing CPU topology to build PPTT table

On Thu, 14 Apr 2022 08:33:29 +0800 Gavin Shan wrote: > Hi Igor, > > On 4/13/22 9:52 PM, Igor Mammedov wrote: > > On Sun, 3 Apr 2022 22:59:53 +0800 > > Gavin Shan wrote: > > > >> When the PPTT table is built, the CPU topology is re-calculated, but > >> it's unecessary because the CPU topolog

[PATCH v3 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT

From: Frank Chang If device's MemoryRegion doesn't have .impl.[min|max]_access_size declaration, the default access_size_min would be 1 byte and access_size_max would be 4 bytes (see: softmmu/memory.c). This will cause a 64-bit memory access to ACLINT to be splitted into two 32-bit memory accesse

[PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable

From: Frank Chang RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time de

[PATCH v1 02/25] docs/devel: add some notes on the binfmt-image-debian targets

We document some of this on the wiki but lets move it into our official developer notes documentation. Signed-off-by: Alex Bennée Cc: Paolo Bonzini --- v2 - fix some trailing ws --- docs/devel/testing.rst | 38 ++ 1 file changed, 38 insertions(+) diff --g

[PATCH v1 05/25] tests/docker: remove test targets

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-3-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 20 +--- tests/docker/dockerfiles/empty.docker | 8 2 files changed, 1 insertion(+), 27 d

[PATCH v1 04/25] tests/docker: remove dead code for linux-user containers

From: Paolo Bonzini debian-powerpc-user-cross was the only linux-user powered cross builder and it was removed in commit 80394ccf21 ("tests/docker: remove debian-powerpc-user-cross", 2019-09-26). Remove all the infrastructure around it since it is now unused. Signed-off-by: Paolo Bonzini Review

[PATCH v1 09/25] tests/docker: remove unnecessary filtering of $(DOCKER_IMAGES)

From: Paolo Bonzini Now that DOCKER_IMAGES is only defined after DOCKER_VIRTUAL_IMAGES is complete, there is no need to re-filter DOCKER_IMAGES against it. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-7-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/docker/Makef

[PATCH v3 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT

From: Frank Chang RISC-V privilege spec defines that: * In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. * For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. It's possible to

[PATCH v1 for 7.1 00/25] testing, docs and gdbstub pre-PR

Hi, As we hope for the release of 7.0 to go without any hitches it is time to a roll a pre-PR for my first 7.1 pull request. This includes: - some doc fixups for devel manual - a -cpu max test for check-avocado - Paolo's cross-compiler cleanups for check-tcg - some check-tcg cleanups and

[PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses

From: Frank Chang This patchset makes ACLINT mtime to be writable as RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. Also, mtimecmp and mtime should be 32/64-bit memory accessible registers. ACLINT reset function is also added, which requir

[PATCH v1 06/25] tests/docker: remove dead variable

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Reviewed-by: Alex Bennée Message-Id: <20220401141326.1244422-4-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Mak

[PATCH v1 17/25] tests/tcg: invoke Makefile.target directly from QEMU's makefile

From: Paolo Bonzini Build the "docker.py cc" invocation directly in tests/tcg/configure.sh, and remove the Makefile.qemu wrapper around Makefile.target. The config-*.mak files now include the actual variables used when building the tests, rather than the CROSS_* variables that Makefile.qemu used

[PATCH v1 01/25] tests/avocado: update aarch64_virt test to exercise -cpu max

The Fedora 29 kernel is quite old and importantly fails when running in LPA2 scenarios. As it's not really exercising much of the CPU space replace it with a custom 5.16.12 kernel with all the architecture options turned on. There is a minimal buildroot initramfs included in the kernel which has a

[PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices

From: Jim Shu This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu Reviewed-by: Frank Chang

[PATCH v1 20/25] tests/tcg: fix non-static build

From: Paolo Bonzini If linking with -static fails at configure time, -static should not be used at build time either. Do not include BUILD_STATIC in $config_target_mak. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-18-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- test

[PATCH v1 07/25] tests/docker: remove unnecessary default definitions

From: Paolo Bonzini The definition of DOCKER_IMAGES and DOCKER_TESTS copes already with an empty value of $(IMAGES) and $(TESTS), no need to force them to "%" if undefined. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-5-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- t

[PATCH v1 19/25] tests/docker: remove SKIP_DOCKER_BUILD

From: Paolo Bonzini It is now unused. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-17-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 12 +--- tests/docker/docker.py| 57 --- 2 files changed, 1

[PATCH v1 03/25] docs/devel: drop :hidden: and :includehidden: tags

This was confusing and in the case of qtest was hiding the details of the qgraph sub-document in the qtest pages. Signed-off-by: Alex Bennée --- docs/devel/index-api.rst | 1 - docs/devel/index-build.rst | 3 +-- docs/devel/index-internals.rst | 1 - docs/devel/index-process.rst | 1

[PATCH v1 14/25] tests/tcg: remove CONFIG_USER_ONLY from config-target.mak

From: Paolo Bonzini Just check the target name instead. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-12-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/tcg/Makefile.target | 8 tests/tcg/configure.sh| 12 +++- 2 files changed, 7 insertions(+

[PATCH v1 16/25] tests/tcg: list test targets in Makefile.prereqs

From: Paolo Bonzini Omit the rules altogether for targets that do not have a compiler. Makefile.qemu now is only invoked if the tests are actually built/run. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-14-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/Makefile.

[PATCH v1 24/25] target/i386: fix byte swap issue with XMM register access

During the conversion to the gdb_get_reg128 helpers the high and low parts of the XMM register where inadvertently swapped. This causes reads of the register to report the incorrect value to gdb. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/971 Fixes: b7b8756a9c (target/i386: use gdb_ge

[PATCH v1 10/25] tests/docker: simplify docker-TEST@IMAGE targets

From: Paolo Bonzini No need to go through the shell when we already have the test and images at the point where the targets are declared. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-8-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 12 +

[PATCH v1 08/25] tests/docker: inline variable definitions or move close to use

From: Paolo Bonzini Variables that are defined with ":=" are handled imperatively, so moving them closer to the first use ensures that all the assignments prior to the first use are taken into account. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-6-pbonz...@redhat.com> Signe

[PATCH v1 13/25] tests/tcg: remove CONFIG_LINUX_USER from config-target.mak

From: Paolo Bonzini Just check the target name instead. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220401141326.1244422-11-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- tests/tcg/configure.sh | 2 -- tests/tcg/multiarch/Makefile.target

[PATCH v1 18/25] tests/tcg: isolate from QEMU's config-host.mak

From: Paolo Bonzini Do not include variables for the QEMU's own compiler, as they are not necessarily related to the cross compiler used for tests/tcg. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-16-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- configure

Re: [PULL for-7.1 00/53] Misc pull request for QEMU 7.1

On Tue, 19 Apr 2022 at 07:09, Paolo Bonzini wrote: > > The following changes since commit f53faa70bb63cc0c8e2fd0752b7ad2c8a79616ba: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2022-04-05 16:14:28 +0100) > > are available in the Git repository at: > > https:

[PATCH v1 12/25] tests/tcg: add compiler test variables when using containers

From: Paolo Bonzini Even for container-based cross compilation use $(CROSS_CC_HAS_*) variables. This makes the TCG test makefiles oblivious of whether the compiler is invoked through a container or not. Signed-off-by: Paolo Bonzini Reviewed-by: Alex Bennée Message-Id: <20220401141326.1244422-1

[PATCH v1 21/25] tests/tcg: remove duplicate sha512-sse case

We already generate the sha512-sse case in the i386 makefile which works for both i386 and x86_64. Signed-off-by: Alex Bennée Fixes: f8a4c6d728 ("tests/tcg: add vectorised sha512 versions") --- tests/tcg/x86_64/Makefile.target | 7 --- 1 file changed, 7 deletions(-) diff --git a/tests/tcg/x

[PATCH v1 11/25] tests/docker: do not duplicate rules for hexagon-cross

From: Paolo Bonzini The commands for docker-image-debian-hexagon-cross are the same as those in debian-toolchain-run, just with a nonstandard path to build-toolchain.sh. Reuse the definition by renaming the debian-hexagon-cross.docker.d directory. Signed-off-by: Paolo Bonzini Message-Id: <20220

Re: [RFC PATCH v3 1/5] ppc64: Add semihosting support

On Mon, 18 Apr 2022 at 20:15, Leandro Lupori wrote: > > Add semihosting support for PPC64. This implementation is > based on the standard for ARM semihosting version 2.0, as > implemented by QEMU and documented in > > https://github.com/ARM-software/abi-aa/releases > > The PPC64 specific diffe

Re: [RFC PATCH 02/18] hw/cpu/cpus: introduce _cpus_ device

On 4/16/22 19:52, Philippe Mathieu-Daudé wrote: On 30/3/22 14:56, Damien Hedde wrote: This object will be a _cpu-cluster_ generalization and is meant to allow create cpus of the same type. The main goal is that this object, on contrary to _cpu-cluster-_, can be used to dynamically create cpu

[PATCH v1 15/25] tests/tcg: prepare Makefile.prereqs at configure time

From: Paolo Bonzini List the dependencies of the build-tcg-tests-* and run-tcg-tests-* targets in a Makefile fragment, without going through Makefile.prereqs's "parsing" of config-*.mak. Signed-off-by: Paolo Bonzini Message-Id: <20220401141326.1244422-13-pbonz...@redhat.com> Signed-off-by: Alex

[PATCH v1 25/25] tests/guest-debug: better handle gdb crashes

There are a number of GDB's on various distros which fail fairly hard when attempting to talk to a cross-arch guest. The previous attempt to catch this was incorrect as the shell will deliver signals as 128+n. Fix the detection and while we are it improve the logging we dump into the test output.

[PATCH v1 23/25] tests/tcg: add missing reference files for float_convs

We might as well include a reference file for i386/x86_64. I was going to include s390x as well but it's broken hence I raised: https://gitlab.com/qemu-project/qemu/-/issues/979. Signed-off-by: Alex Bennée --- tests/tcg/i386/float_convs.ref | 748 +++ tests/tcg/x

Re: [PATCH v4 0/4] util/thread-pool: Expose minimun and maximum size

On Mon, 2022-04-04 at 10:29 +0100, Stefan Hajnoczi wrote: > On Fri, Apr 01, 2022 at 11:35:20AM +0200, Nicolas Saenz Julienne wrote: > > As discussed on the previous RFC[1] the thread-pool's dynamic thread > > management doesn't play well with real-time and latency sensitive > > systems. This series

Re: [PATCH] softmmu/memory: Skip translation size instead of fixed granularity if translate() successfully

On 16.04.22 10:34, chenxiang via wrote: > From: Xiang Chen > > Currently memory_region_iommu_replay() does full page table walk with > fixed granularity (page size) no matter translate() succeeds or not. > Actually if translate() successfully, we can skip translation size > (iotlb.addr_mask + 1)

Re: [PATCH v3 24/39] include/exec/log: Do not reference QemuLogFile directly

Richard Henderson writes: > Use qemu_log_trylock/unlock instead of the raw rcu_read. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: Question about direct block chaining

Taylor Simpson writes: >> -Original Message- >> From: Richard Henderson >> Sent: Monday, April 18, 2022 10:38 AM >> To: Taylor Simpson ; qemu-devel@nongnu.org >> Cc: Philippe Mathieu-Daudé >> Subject: Re: Question about direct block chaining >> >> On 4/18/22 07:54, Taylor Simpson wro

Re: [PATCH v3 01/60] tcg: Add tcg_constant_ptr

Richard Henderson writes: > Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: [RFC PATCH 0/4] 9pfs: Add 9pfs support for Windows host

On 18/04/2022 13:31, Christian Schoenebeck wrote: On Montag, 18. April 2022 11:07:33 CEST Mark Cave-Ayland wrote: On 17/04/2022 13:55, Christian Schoenebeck wrote: On Donnerstag, 14. April 2022 19:25:04 CEST Shi, Guohuai wrote: -Original Message- From: Christian Schoenebeck Sent: 202

Re: [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8

Richard Henderson writes: > Update isar fields per ARM DDI0487 H.a. > > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: [PATCH v1 35/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

On 19/04/2022 02:50, yangxiaojuan wrote: On 2022/4/18 下午4:57, Mark Cave-Ayland wrote: On 18/04/2022 04:48, Richard Henderson wrote: On 4/15/22 02:40, Xiaojuan Yang wrote: + memory_region_init(&s->mmio[cpu], OBJECT(s), +   "loongarch_extioi", EXTIOI_SIZE); + +    m

Re: [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8

Richard Henderson writes: > Update SCR_EL3 fields per ARM DDI0487 H.a. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

RE: [RFC PATCH 0/4] 9pfs: Add 9pfs support for Windows host

Hi All, I just finished a basic PoC for mapped-file. It works! I think I can also support "security_model=map-xattr" by NTFS ADS. However, I got a limitation of MinGW: https://github.com/mirror/mingw-w64/blob/master/mingw-w64-crt/misc/dirent.c#L290 MinGW can not handle seekdir() while the direc

Re: [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8

Richard Henderson writes: > Update SCR_EL3 fields per ARM DDI0487 H.a. > > Signed-off-by: Richard Henderson Aside: I notice you have added FEAT_foo comments to the SCTLR bits next, it might be worth at least flagging the FEAT_RME ones here. > --- > target/arm/cpu.h | 12 > 1 fi

Re: [PATCH v3 04/60] target/arm: Update SCTLR bits to ARMv9.2

Richard Henderson writes: > Update SCTLR_ELx fields per ARM DDI0487 H.a. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: [PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool

Richard Henderson writes: > Bool is a more appropriate type for this value. > Move the member down in the struct to keep the > bool type members together and remove a hole. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re:

Richard Henderson writes: > Bool is a more appropriate type for this value. > Adjust the assignments to use true/false. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

Re: Portable inline asm to get address of TLS variable

* Stefan Hajnoczi: > On Tue, Mar 01, 2022 at 12:54:49PM +0100, Florian Weimer wrote: >> > I took a quick look at C++20 coroutines since they are available in >> > compilers but the primitives look hard to use even from C++, let alone >> > from C. >> >> Could you go into details what makes them ha

Re: [PATCH] remove -writeconfig

On Thu, Apr 14, 2022 at 10:57:21AM -0400, Paolo Bonzini wrote: > Like -set and -readconfig, it would not really be too hard to > extend -writeconfig to parsing mechanisms other than QemuOpts. > However, the uses of -writeconfig are substantially more > limited, as it is generally easier to write th

[PATCH] hw/riscv: boot: Support 64bit fdt address.

The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram address within 3GB, but not all platforms have dram_base within 3GB. This patch adds an exception for dram base not within 3GB, which will place fdt at dram_end align 16MB. riscv_setup_rom_reset_vec() also needs to be modif

[PATCH 1/5] hw/nvme: enforce common serial per subsystem

From: Klaus Jensen The Identify Controller Serial Number (SN) is the serial number for the NVM subsystem and must be the same across all controller in the NVM subsystem. Enforce this. Signed-off-by: Klaus Jensen --- hw/nvme/nvme.h | 1 + hw/nvme/subsys.c | 7 +++ 2 files changed, 8 inse

[PATCH 0/5] hw/nvme: fix namespace identifiers

From: Klaus Jensen The namespace identifiers reported by the controller is kind of a mess. See [1,2]. This series should fix this for both the `-device nvme,drive=...` and `-device nvme-ns,...` cases. [1]: https://lore.kernel.org/linux-nvme/20220224192845.1097602-1-...@lst.de/ [2]: https://

[PATCH 2/5] hw/nvme: always set eui64

From: Klaus Jensen Unconditionally set an EUI64 for namespaces. The nvme-ns device defaults to auto-generating a persistent EUI64 if not specified, but for single namespace setups (-device nvme,drive=...), this does not happen. Since the EUI64 has previously been zeroed it is not considered vali

[PATCH 4/5] hw/nvme: do not auto-generate uuid

From: Klaus Jensen Do not default to generate an UUID for namespaces if it is not explicitly specified. This is a technically a breaking change in behavior. However, since the UUID changes on every VM launch, it is not spec compliant and is of little use since the UUID cannot be used reliably an

[PATCH 3/5] hw/nvme: do not report null uuid

From: Klaus Jensen Do not report the "null uuid" (all zeros) in the namespace identification descriptors. Reported-by: Luis Chamberlain Reported-by: Christoph Hellwig Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff

[PATCH 1/5] 9pfs: fix qemu_mknodat(S_IFREG) on macOS

mknod() on macOS does not support creating regular files, so divert to openat_file() if S_IFREG is passed with mode argument. Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is equivalent to type S_IFREG". Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off

[PATCH 5/5] hw/nvme: bump firmware revision

From: Klaus Jensen The Linux kernel quirks the QEMU NVMe controller pretty heavily because of the namespace identifier mess. Since this is now fixed, bump the firmware revision number to allow the quirk to be disabled for this revision. As of now, bump the firmware revision number to be equal to

[PATCH 2/5] 9pfs: fix qemu_mknodat(S_IFSOCK) on macOS

mknod() on macOS does not support creating sockets, so divert to call sequence socket(), bind() and chmod() respectively if S_IFSOCK was passed with mode argument. Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off-by: Christian Schoenebeck --- hw/9pfs/9p-util-darwin

[PATCH 3/5] 9pfs: fix wrong encoding of rdev field in Rgetattr on macOS

The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t, which is actually a system dependant type and therefore both the size and encoding of dev_t differ between macOS and Linux. So far we have sent 'rdev' to guest in host's dev_t format as-is, which caused devices to appear with wrong device

[PATCH 0/5] 9pfs: macOS host fixes

A bunch of fixes for recently added (QEMU 7.0) 9p support on macOS hosts. Note: there are still issues to address with case-insensitive file systems on macOS hosts. But I'll send a separate RFC on that issue. Christian Schoenebeck (5): 9pfs: fix qemu_mknodat(S_IFREG) on macOS 9pfs: fix qemu_m

[PATCH 4/5] 9pfs: fix wrong errno being sent to Linux client on macOS host

Linux and macOS only share some errno definitions with equal macro name and value. In fact most mappings for errno are completely different on the two systems. This patch converts some important errno values from macOS host to corresponding Linux errno values before eventually sending such error c

[PATCH 5/5] 9pfs: fix removing non-existent POSIX ACL xattr on macOS host

When mapped POSIX ACL is used, we are ignoring errors when trying to remove a POSIX ACL xattr that does not exist. On Linux hosts we would get ENODATA in such cases, on macOS hosts however we get ENOATTR instead, so ignore ENOATTR errors as well. This patch fixes e.g. a command on Linux guest like

Re: [PATCH] migration: Read state once

"Dr. David Alan Gilbert (git)" wrote: > From: "Dr. David Alan Gilbert" > > The 'status' field for the migration is updated normally using > an atomic operation from the migration thread. > Most readers of it aren't that careful, and in most cases it doesn't > matter. > > In query_migrate->fill_so

Re: [ANNOUNCE] QEMU 7.0.0-rc4 is now available

On Mon, 18 Apr 2022 at 19:14, Stefan Weil wrote: > > Am 13.04.22 um 02:44 schrieb Michael Roth: > > A note from the maintainer: > > > >rc4 contains three fixes for late-breaking security bugs. The plan > >is to make the final 7.0 release in a week's time on the 19th April, > >with no f

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