Re: [PATCH 0/2] target/i386: Some mmx/sse instructions don't require

Ping.. And the title is target/i386: Some mmx/sse instructions don't require CR0.TS=0 On Fri, Mar 25, 2022 at 10:55 PM Wei Li wrote: > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/427 > > All instructions decoded by 'gen_see' is assumed to require CRO.TS=0. But > according to SDM

Re: [PATCH v1.1 1/9] qapi: fix example of netdev_add command

Hi, On Mon, Apr 04, 2022 at 08:14:11AM +0200, Markus Armbruster wrote: > Victor Toso writes: > > > Example output has the optional member @dnssearch as string type. It > > should be an array of strings instead. Fix it. > > "of String objects". Happy to fix this in my tree. Sure > > > > > Fo

Re: [PATCH] [PATCH RFC v2] Implements Backend Program conventions for vhost-user-scsi

On Mon, 4 Apr 2022 at 00:16, Sakshi Kaushik wrote: > I have made the suggested changes and submitted v3. > But I am not sure how to check this code by running it? When I try to run the > .c code I get the error message: 'qemu/osdep.h' no such file or directory. > > I have followed the building st

Re: [PATCH] target/s390x: Fix the accumulation of ccm in op_icm

On 01.04.22 21:36, Richard Henderson wrote: > Coverity rightly reports that 0xff << pos can overflow. > This would affect the ICMH instruction. > > Fixes: Coverity CID 1487161 > Signed-off-by: Richard Henderson > --- > target/s390x/tcg/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 dele

Re: [PATCH v5 1/4] qapi/machine.json: Add cluster-id

On Sun, Apr 03, 2022 at 10:59:50PM +0800, Gavin Shan wrote: > This adds cluster-id in CPU instance properties, which will be used > by arm/virt machine. Besides, the cluster-id is also verified or > dumped in various spots: > > * hw/core/machine.c::machine_set_cpu_numa_node() to associate >

Re: [PATCH v5 2/4] hw/arm/virt: Consider SMP configuration in CPU topology

On Sun, Apr 03, 2022 at 10:59:51PM +0800, Gavin Shan wrote: > Currently, the SMP configuration isn't considered when the CPU > topology is populated. In this case, it's impossible to provide > the default CPU-to-NUMA mapping or association based on the socket > ID of the given CPU. > > This takes

Re: [PATCH v5 1/4] qapi/machine.json: Add cluster-id

On Mon, Apr 04, 2022 at 09:37:10AM +0100, Daniel P. Berrangé wrote: > On Sun, Apr 03, 2022 at 10:59:50PM +0800, Gavin Shan wrote: > > This adds cluster-id in CPU instance properties, which will be used > > by arm/virt machine. Besides, the cluster-id is also verified or > > dumped in various spots:

Re: [PATCH] linux-user/ppc: Narrow type of ccr in save_user_regs

On Mon, 4 Apr 2022 at 07:55, Cédric Le Goater wrote: > > On 4/1/22 21:16, Richard Henderson wrote: > > Coverity warns that we shift a 32-bit value by N, and then > > accumulate it into a 64-bit type (target_ulong on ppc64). > > > > The ccr is always 8 * 4-bit fields, and thus is always a > > 32-bi

Re: [PATCH v4 0/4] util/thread-pool: Expose minimun and maximum size

On Fri, 2022-04-01 at 11:35 +0200, Nicolas Saenz Julienne wrote: Subject says 0/4 where is should've been 0/3. > As discussed on the previous RFC[1] the thread-pool's dynamic thread > management doesn't play well with real-time and latency sensitive > systems. This series introduces a set of cont

Re: [PATCH] target/i386: Suppress coverity warning on fsave/frstor

On 4/1/22 20:46, Richard Henderson wrote: Coverity warns that 14 << data32 may overflow with respect to the target_ulong to which it is subsequently added. We know this wasn't true because data32 is in [1,2], but the suggested fix is perfectly fine. Fixes: Coverity CID 1487135, 1487256 Signed-

Re: [PATCH] plugins: Assert mmu_idx in range before use in qemu_plugin_get_hwaddr

Reviewed-by: Damien Hedde On 4/1/22 21:02, Richard Henderson wrote: Coverity reports out-of-bound accesses here. This should be a false positive due to how the index is decoded from MemOpIdx. Fixes: Coverity CID 1487201 Signed-off-by: Richard Henderson --- plugins/api.c | 2 ++ 1 file cha

Re: [PATCH v1 1/9] qmp: Add dump machine type compatible properties

On 3/30/22 14:03, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:15, Maxim Davydov wrote: This patch adds the ability to get all the compat_props of the corresponding supported machines for their comparison. Example: { "execute" : "query-machines", "arguments" : { "is-full" : true } } Sig

Re: [PATCH] linux-user/ppc: Narrow type of ccr in save_user_regs

On 4/4/22 10:41, Peter Maydell wrote: On Mon, 4 Apr 2022 at 07:55, Cédric Le Goater wrote: On 4/1/22 21:16, Richard Henderson wrote: Coverity warns that we shift a 32-bit value by N, and then accumulate it into a 64-bit type (target_ulong on ppc64). The ccr is always 8 * 4-bit fields, and th

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

On Fri, Apr 01, 2022 at 01:01:53PM +0200, Paolo Bonzini wrote: > On 4/1/22 10:05, Emanuele Giuseppe Esposito wrote: > > > The list itself would be used internally to implement the write-side > > > lock and unlock primitives, but it would not be protected by the above > > > functions.  So there woul

Re: [PATCH] linux-user/ppc: Narrow type of ccr in save_user_regs

On Mon, 4 Apr 2022 at 10:09, Cédric Le Goater wrote: > > On 4/4/22 10:41, Peter Maydell wrote: > > On Mon, 4 Apr 2022 at 07:55, Cédric Le Goater wrote: > >> > >> On 4/1/22 21:16, Richard Henderson wrote: > >>> Coverity warns that we shift a 32-bit value by N, and then > >>> accumulate it into a 6

Re: [PATCH v4 0/4] util/thread-pool: Expose minimun and maximum size

On Fri, Apr 01, 2022 at 11:35:20AM +0200, Nicolas Saenz Julienne wrote: > As discussed on the previous RFC[1] the thread-pool's dynamic thread > management doesn't play well with real-time and latency sensitive > systems. This series introduces a set of controls that'll permit > achieving more dete

Re: [PATCH v7 12/12] hw/acpi: Make the PCI hot-plug aware of SR-IOV

On Thu, Mar 31, 2022 at 02:38:41PM +0200, Igor Mammedov wrote: > it's unclear what's bing hotpluged and unplugged, it would be better if > you included QEMU CLI and relevan qmp/monito commands to reproduce it. Qemu CLI: - -device pcie-root-port,slot=0,id=rp0 -device nvme-subsys,id=subsys0

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

On Mon, Apr 4, 2022 at 11:25 AM Stefan Hajnoczi wrote: > - The new API doesn't stop more I/O requests from being submitted, it > just blocks the current coroutine so request processing is deferred. > New I/O requests would not complete until the write-side critical section ends. However they w

Re: [PATCH v6 15/19] vfio-user: handle device interrupts

On Wed, Mar 30, 2022 at 09:40:42AM +, Thanos Makatos wrote: > > -Original Message- > > From: Jag Raman > > Sent: 29 March 2022 20:07 > > To: Stefan Hajnoczi > > Cc: Alex Williamson ; qemu-devel > de...@nongnu.org>; Michael S. Tsirkin ; Philippe Mathieu- > > Daudé ; Paolo Bonzini ; Be

Re: [PATCH v1 0/9] Fix some qapi examples

Victor Toso writes: > Hi, > > I did another iteration of adding the examples in the qapi documentation > as unit tests in another project and found a few that could be updated. > > Feel free to cherry-pick them. Happy to rework it if needed. Queued, thanks!

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

Am 04/04/2022 um 11:41 schrieb Paolo Bonzini: > > > On Mon, Apr 4, 2022 at 11:25 AM Stefan Hajnoczi > wrote: > > - The new API doesn't stop more I/O requests from being submitted, it >   just blocks the current coroutine so request processing is deferred.

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

On 4/4/22 11:51, Emanuele Giuseppe Esposito wrote: >> >> I agree that it doesn't. This new lock is only protecting ->parents and >> ->children. > Side note: it will also be used to protect other fields, like > .aio_context I think. I haven't checked if there is something else we > might want to pr

Re: [PATCH v5 1/4] qapi/machine.json: Add cluster-id

Hi Daniel, On 4/4/22 4:40 PM, Daniel P. Berrangé wrote: On Mon, Apr 04, 2022 at 09:37:10AM +0100, Daniel P. Berrangé wrote: On Sun, Apr 03, 2022 at 10:59:50PM +0800, Gavin Shan wrote: This adds cluster-id in CPU instance properties, which will be used by arm/virt machine. Besides, the cluster-

Re: [PATCH v5 2/4] hw/arm/virt: Consider SMP configuration in CPU topology

Hi Daniel, On 4/4/22 4:39 PM, Daniel P. Berrangé wrote: On Sun, Apr 03, 2022 at 10:59:51PM +0800, Gavin Shan wrote: Currently, the SMP configuration isn't considered when the CPU topology is populated. In this case, it's impossible to provide the default CPU-to-NUMA mapping or association based

Re: [PATCH 1/1] xlnx-bbram: hw/nvram: Fix uninitialized Error *

On [2022 Apr 01] Fri 12:06:31, Tong Ho wrote: > This adds required initialization of Error * variable. > > Signed-off-by: Tong Ho Reviewed-by: Francisco Iglesias > --- > hw/nvram/xlnx-bbram.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/nvram/xlnx-bbram.c b/hw/

Re: [PATCH v1 2/9] pci: add null-pointer check

On 3/30/22 14:07, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:15, Maxim Davydov wrote: Call pci_bus_get_w64_range can fail with the segmentation fault. For example, this can happen during attempt to get pci-hole64-end immediately after initialization. So, immediately after initializa

Re: [PATCH] docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.

On [2022 Apr 02] Sat 22:45:23, Pavel Pisa wrote: > Signed-off-by: Pavel Pisa Reviewed-by: Francisco Iglesias > --- > docs/system/devices/can.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst > index 16d

Re: [PATCH] multifd: Copy pages before compressing them with zlib

* Ilya Leoshkevich (i...@linux.ibm.com) wrote: > zlib_send_prepare() compresses pages of a running VM. zlib does not > make any thread-safety guarantees with respect to changing deflate() > input concurrently with deflate() [1]. > > One can observe problems due to this with the IBM zEnterprise Dat

Re: [PATCH v1 3/9] mem: appropriate handling getting mem region

On 3/30/22 14:27, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:15, Maxim Davydov wrote: Attempt to get memory region if the device doesn't have hostmem may not be an error. This can be happen immediately after initialization (getting value without default one). Signed-off-by: Maxim Davy

Re: [PATCH v5 2/4] hw/arm/virt: Consider SMP configuration in CPU topology

On Mon, 4 Apr 2022 18:48:00 +0800 Gavin Shan wrote: > Hi Daniel, > > On 4/4/22 4:39 PM, Daniel P. Berrangé wrote: > > On Sun, Apr 03, 2022 at 10:59:51PM +0800, Gavin Shan wrote: > >> Currently, the SMP configuration isn't considered when the CPU > >> topology is populated. In this case, it's i

Re: [PATCH] multifd: Copy pages before compressing them with zlib

On Mon, 2022-04-04 at 12:20 +0100, Dr. David Alan Gilbert wrote: > * Ilya Leoshkevich (i...@linux.ibm.com) wrote: > > zlib_send_prepare() compresses pages of a running VM. zlib does not > > make any thread-safety guarantees with respect to changing > > deflate() > > input concurrently with deflate(

Re: [PATCH 0/3] qapi-schema: support alternates with array type

Paolo Bonzini writes: > As suggested in the review of the statistics subsystem. Queued for 7.1, thanks!

Re: [PATCH v1 6/9] chardev: add appropriate getting address

On 3/30/22 14:32, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:15, Maxim Davydov wrote: Attempt to get address after initialization shouldn't fail on assert in the qapi automatically generated code. As a possible solution, it can return null type. But at some point this address appears?

Re: [PATCH] multifd: Copy pages before compressing them with zlib

On Mon, Apr 04, 2022 at 12:20:14PM +0100, Dr. David Alan Gilbert wrote: > * Ilya Leoshkevich (i...@linux.ibm.com) wrote: > > zlib_send_prepare() compresses pages of a running VM. zlib does not > > make any thread-safety guarantees with respect to changing deflate() > > input concurrently with defla

Re: [PATCH] multifd: Copy pages before compressing them with zlib

Daniel P. Berrangé wrote: > On Mon, Apr 04, 2022 at 12:20:14PM +0100, Dr. David Alan Gilbert wrote: >> * Ilya Leoshkevich (i...@linux.ibm.com) wrote: >> > zlib_send_prepare() compresses pages of a running VM. zlib does not >> > make any thread-safety guarantees with respect to changing deflate() >

[PULL 0/3] ppc queue

The following changes since commit bc6ec396d471d9e4aae7e2ff8b72e11da9a97665: Merge tag 'pull-request-2022-04-01' of https://gitlab.com/thuth/qemu into staging (2022-04-02 09:36:07 +0100) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-ppc-202

[PULL 2/3] ppc/pnv: Fix number of registers in the PCIe controller on POWER9

From: Frederic Barrat The spec defines 3 registers, even though only index 0 and 2 are valid on POWER9. The same model is used on POWER10. Register 1 is defined there but we currently don't use it in skiboot. So we can keep reporting an error on write. Reported by Coverity (CID 1487176). Fixes:

[PULL 3/3] linux-user/ppc: Narrow type of ccr in save_user_regs

From: Richard Henderson Coverity warns that we shift a 32-bit value by N, and then accumulate it into a 64-bit type (target_ulong on ppc64). The ccr is always 8 * 4-bit fields, and thus is always a 32-bit quantity; narrow the type to avoid the warning. Fixes: Coverity CID 1487223 Signed-off-by:

Re: [PATCH v2 5/7] block/block-copy: block_copy(): add timeout_ns parameter

On 01.04.22 18:08, Vladimir Sementsov-Ogievskiy wrote: 01.04.2022 16:16, Hanna Reitz wrote: On 01.04.22 11:19, Vladimir Sementsov-Ogievskiy wrote: Add possibility to limit block_copy() call in time. To be used in the next commit. Signed-off-by: Vladimir Sementsov-Ogievskiy ---   block/block-c

[PULL 1/3] hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

From: Daniel Henrique Barboza The timebase is allocated during spapr_realize_vcpu() and it's not freed. This results in memory leaks when doing vcpu unplugs: ==636935== ==636935== 144 (96 direct, 48 indirect) bytes in 1 blocks are definitely lost in loss record 6 ,461 of 8,135 ==636935==at

Re: [PATCH 2/4] virtio-ccw: move vhost_ccw_scsi to a separate file

On Mon, Mar 28 2022, Paolo Bonzini wrote: > Remove unecessary use of #ifdef CONFIG_VHOST_SCSI, instead just use a > separate file and a separate rule in meson.build. > > Signed-off-by: Paolo Bonzini > --- > hw/s390x/meson.build | 1 + > hw/s390x/vhost-scsi-ccw.c | 64 +++

Re: [PATCH v5 00/13] KVM: mm: fd-based approach for supporting KVM guest private memory

On Friday 01 Apr 2022 at 12:56:50 (-0700), Andy Lutomirski wrote: > On Fri, Apr 1, 2022, at 7:59 AM, Quentin Perret wrote: > > On Thursday 31 Mar 2022 at 09:04:56 (-0700), Andy Lutomirski wrote: > > > > To answer your original question about memory 'conversion', the key > > thing is that the pKVM

[PATCH v9 00/45] CXl 2.0 emulation Support

CI passing both with the full series and at appropriate points for a partial series merge if desired (at end of each section tests are introduced) https://gitlab.com/jic23/qemu/-/pipelines/508396913 Possible partial sets: 1-15 (end with the test of the pxb-cxl host bridge) 16-22 (end with the test

[PATCH v9 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)

From: Ben Widawsky A CXL 2.0 component is any entity in the CXL topology. All components have a analogous function in PCIe. Except for the CXL host bridge, all have a PCIe config space that is accessible via the common PCIe mechanisms. CXL components are enumerated via DVSEC fields in the extende

Re: [PATCH v8 04/46] hw/cxl/device: Introduce a CXL device (8.2.8)

On Fri, Apr 01, 2022 at 02:30:34PM +0100, Jonathan Cameron wrote: > On Thu, 31 Mar 2022 22:13:20 + > Adam Manzanares wrote: > > > On Wed, Mar 30, 2022 at 06:48:48PM +0100, Jonathan Cameron wrote: > > > On Tue, 29 Mar 2022 18:13:59 + > > > Adam Manzanares wrote: > > > > > > > On Fri, M

[PATCH v9 01/45] hw/pci/cxl: Add a CXL component type (interface)

From: Ben Widawsky A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of

[PATCH v9 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4)

From: Ben Widawsky This is the beginning of implementing mailbox support for CXL 2.0 devices. The implementation recognizes when the doorbell is rung, handles the command/payload, clears the doorbell while returning error codes and data. Generally the mailbox mechanism is designed to permit comm

[PATCH v9 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation

From: Jonathan Cameron The CXL emulation will be jointly maintained by Ben Widawsky and Jonathan Cameron. Broken out as a separate patch to improve visibility. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/

[PATCH v9 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2)

From: Ben Widawsky This implements all device MMIO up to the first capability. That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Endianness and alignme

[PATCH v9 07/45] hw/cxl/device: Add memory device utilities

From: Ben Widawsky Memory devices implement extra capabilities on top of CXL devices. This adds support for that. A large part of memory devices is the mailbox/command interface. All of the mailbox handling is done in the mailbox-utils library. Longer term, new CXL devices that are being emulate

[PATCH v9 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3)

From: Ben Widawsky Errata F4 to CXL 2.0 clarified the meaning of the timer as the sum of the value set with the timestamp set command and the number of nano seconds since it was last set. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/cxl/cxl-mail

[PATCH v9 04/45] hw/cxl/device: Introduce a CXL device (8.2.8)

From: Ben Widawsky A CXL device is a type of CXL component. Conceptually, a CXL device would be a leaf node in a CXL topology. From an emulation perspective, CXL devices are the most complex and so the actual implementation is reserved for discrete commits. This new device type is specifically c

[PATCH v9 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL

From: Ben Widawsky CXL specification provides for the ability to obtain logs from the device. Logs are either spec defined, like the "Command Effects Log" (CEL), or vendor specific. UUIDs are defined for all log types. The CEL is a mechanism to provide information to the host about which command

[PATCH v9 12/45] hw/pci/cxl: Create a CXL bus type

From: Ben Widawsky The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the

[PATCH v9 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)

From: Ben Widawsky Using the previously implemented stubbed helpers, it is now possible to easily add the missing, required commands to the implementation. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/cxl/cxl-mailbox-utils.c | 27 +++

[PATCH v9 11/45] hw/pxb: Use a type for realizing expanders

From: Ben Widawsky This opens up the possibility for more types of expanders (other than PCI and PCIe). We'll need this to create a CXL expander. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/pci-bridge/pci_expander_bridge.c | 11 +++ 1 f

[PATCH v9 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)

From: Ben Widawsky A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly

[PATCH v9 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge)

From: Ben Widawsky This works like adding a typical pxb device, except the name is 'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as follows: -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1 A CXL PXB is backward compatible with PCIe. What this means in practice is that an ope

[PATCH v9 19/45] hw/cxl/device: Add some trivial commands

From: Ben Widawsky GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to info already returned in the IDENTIFY command. To have a more robust implementation, add those. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mailbox-utils.c | 69 +

Re: [PATCH v1 7/9] colo-compare: safe finalization

The main problem that if we call object_new_with_class() and then object_unref(), it fails. First of all, this is due to the fact that finalize expects that net/colo-compare.c:colo_compare_complete() has been called before. On 3/30/22 17:54, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:1

[PATCH v9 25/45] acpi/cxl: Create the CEDT (9.14.1)

From: Ben Widawsky The CXL Early Discovery Table is defined in the CXL 2.0 specification as a way for the OS to get CXL specific information from the system firmware. CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware

[PATCH v9 16/45] hw/cxl/rp: Add a root port

From: Ben Widawsky This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to

[PATCH v9 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding

From: Jonathan Cameron Both registers and the CFMWS entries in CDAT use simple encodings for the number of interleave ways and the interleave granularity. Introduce simple conversion functions to/from the unencoded number / size. So far the iw decode has not been needed so is it not implemented.

[PATCH v9 22/45] qtests/cxl: Add initial root port and CXL type3 tests

At this stage we can boot configurations with host bridges, root ports and type 3 memory devices, so add appropriate tests. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- tests/qtest/cxl-test.c | 126 + 1 file changed, 126 insertions(+) dif

[PATCH v9 13/45] cxl: Machine level control on whether CXL support is enabled

From: Jonathan Cameron There are going to be some potential overheads to CXL enablement, for example the host bridge region reserved in memory maps. Add a machine level control so that CXL is disabled by default. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/core/machine.c

[PATCH v9 28/45] acpi/cxl: Introduce CFMWS structures in CEDT

From: Ben Widawsky The CEDT CXL Fixed Window Memory Window Structures (CFMWs) define regions of the host phyiscal address map which (via an impdef means) are configured such that they have a particular interleave setup across one or more CXL Host Bridges. Reported-by: Alison Schofield Signed-of

[PATCH v9 23/45] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)

From: Ben Widawsky CXL host bridges themselves may have MMIO. Since host bridges don't have a BAR they are treated as special for MMIO. This patch includes i386/pc support. Also hook up the device reset now that we have have the MMIO space in which the results are visible. Note that we duplicat

[PATCH v9 34/45] hw/cxl/component Add a dumb HDM decoder handler

From: Ben Widawsky Add a trivial handler for now to cover the root bridge where we could do some error checking in future. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-component-utils.c | 31 +++ 1 file changed, 31 insertions(+) diff

[PATCH v9 15/45] qtest/cxl: Introduce initial test for pxb-cxl only.

Initial test with just pxb-cxl. Other tests will be added alongside functionality. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Tested-by: Alex Bennée --- tests/qtest/cxl-test.c | 23 +++ tests/qtest/meson.build | 4 2 files changed, 27 insertions(+) di

[PATCH v9 30/45] pci/pcie_port: Add pci_find_port_by_pn()

From: Jonathan Cameron Simple function to search a PCIBus to find a port by it's port number. CXL interleave decoding uses the port number as a target so it is necessary to locate the port when doing interleave decoding. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/pci/pci

[PATCH v9 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port

An initial simple upstream port emulation to allow the creation of CXL switches. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron --- hw/pci-bridge/cxl_upstream.c | 211 +++ hw/pci-bridge/meson.build| 2 +- include/hw/cxl/cxl.h

[PATCH v9 35/45] i386/pc: Enable CXL fixed memory windows

From: Jonathan Cameron Add the CFMWs memory regions to the memorymap and adjust the PCI window to avoid hitting the same memory. Signed-off-by: Jonathan Cameron --- hw/i386/pc.c | 31 ++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/h

[PATCH v9 17/45] hw/cxl/device: Add a memory device (8.2.8.5)

From: Ben Widawsky A CXL memory device (AKA Type 3) is a CXL component that contains some combination of volatile and persistent memory. It also implements the previously defined mailbox interface as well as the memory device firmware interface. Although the memory device is configured like a no

[PATCH v9 31/45] CXL/cxl_component: Add cxl_get_hb_cstate()

From: Jonathan Cameron Accessor to get hold of the cxl state for a CXL host bridge without exposing the internals of the implementation. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée --- hw/pci-bridge/pci_expander_bridge.c | 7 +++ include/hw/cxl/cxl_component.h | 2 ++ 2

Re: [PATCH v1 8/9] qom: add command to print initial properties

On 3/30/22 18:17, Vladimir Sementsov-Ogievskiy wrote: 29.03.2022 00:15, Maxim Davydov wrote: The command "query-init-properties" is needed to get values of properties after initialization (not only default value). It makes sense, for example, when working with x86_64-cpu. All machine types (

[PATCH v9 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing

From: Ben Widawsky This should introduce no change. Subsequent work will make use of this new class member. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mailbox-utils.c | 3 +++ hw/mem/cxl_type3.c | 9 + include/hw/cxl/cxl_device.h | 11 ++

[PATCH v9 32/45] mem/cxl_type3: Add read and write functions for associated hostmem.

From: Jonathan Cameron Once a read or write reaches a CXL type 3 device, the HDM decoders on the device are used to establish the Device Physical Address which should be accessed. These functions peform the required maths and then use a device specific address space to access the hostmem->mr to

[PATCH v9 38/45] tests/acpi: Add tables for CXL emulation.

Tables that differ from normal Q35 tables when running the CXL test. Signed-off-by: Jonathan Cameron --- tests/data/acpi/q35/CEDT.cxl| Bin 0 -> 184 bytes tests/data/acpi/q35/DSDT.cxl| Bin 0 -> 9615 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 fi

[PATCH v9 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. The CFMWs are placed above the extended memmap. Only create the CEDT table if cxl=on set for the machine. Signed-off-by: Jonathan Cameron Signed-off-

[PATCH v9 39/45] qtest/cxl: Add more complex test cases with CFMWs

From: Ben Widawsky Add CXL Fixed Memory Windows to the CXL tests. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron --- tests/qtest/cxl-test.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tests/qtest/cxl-test.c b/test

[PATCH v9 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation.

Provide an introduction to the main components of a CXL system, with detailed explanation of memory interleaving, example command lines and kernel configuration. This was a challenging document to write due to the need to extract only that subset of CXL information which is relevant to either user

[PATCH v9 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA)

From: Ben Widawsky Implement get and set handlers for the Label Storage Area used to hold data describing persistent memory configuration so that it can be ensured it is seen in the same configuration after reboot. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mai

[PATCH v9 45/45] docs/cxl: Add switch documentation

Switches were already introduced, but now we support them update the documentation to provide an example in diagram and qemu command line parameter forms. Signed-off-by: Jonathan Cameron --- docs/system/devices/cxl.rst | 88 - 1 file changed, 86 insertions(+),

[PATCH for-7.1 02/18] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE

Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can delete the device entirely. Signed-off-by: Peter Maydell --- hw/intc/exynos4210_gic.c | 107 --- 1 file changed, 107 deletions(-) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gi

[PATCH v9 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port

Emulation of a simple CXL Switch downstream port. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-host.c | 43 +- hw/pci-bridge/cxl_downstream.c | 244 + hw/pci-bridge/meson.build | 2 +- 3 fil

[PATCH v9 24/45] acpi/cxl: Add _OSC implementation (9.14.2)

From: Ben Widawsky CXL 2.0 specification adds 2 new dwords to the existing _OSC definition from PCIe. The new dwords are accessed with a new uuid. This implementation supports what is in the specification. iasl -d decodes the result of this patch as: Name (SUPP, Zero) Name (CTRL, Zero) Name (SU

Re: [PATCH] [PATCH RFC v2] Implements Backend Program conventions for vhost-user-scsi

On Mon, 4 Apr 2022 at 15:51, Sakshi Kaushik wrote: > I am not able to find vhost-user-scsi inside build/contrib/vhost-user-scsi > despite running the 'make' command. It is probably not being built because the dependencies are not installed on your machine. Here are the contents of the contrib/vh

[PATCH for-7.1 01/18] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device

The Exynos4210 SoC device currently uses a custom device "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ line. We have a standard TYPE_OR_IRQ device for this now, so use that instead. (This is a migration compatibility break, but that is OK for this machine type.) Signed-off

[PATCH for-7.1 07/18] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c

The function exynos4210_init_board_irqs() currently lives in exynos4210_gic.c, but it isn't really part of the exynos4210.gic device -- it is a function that implements (some of) the wiring up of interrupts between the SoC's GIC and combiner components. This means it fits better in exynos4210.c, w

[PATCH v9 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows.

From: Jonathan Cameron The concept of these is introduced in [1] in terms of the description the CEDT ACPI table. The principal is more general. Unlike once traffic hits the CXL root bridges, the host system memory address routing is implementation defined and effectively static once observable b

[PATCH for-7.1 00/18] hw/arm: Make exynos4210 use TYPE_SPLIT_IRQ

The primary aim of this patchset is to make the exynos4210 code use the TYPE_SPLIT_IRQ device instead of the old qemu_split_irq() function (which we are trying to get rid of). However, the current code is quite complicated and so we have to do a fair amount of refactoring in order to be able to use

[PATCH v9 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl

This adds code to instantiate the slightly extended ACPI root port description in DSDT as per the CXL 2.0 specification. Basically a cut and paste job from the i386/pc code. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky Reviewed-by: Alex Bennée --- hw/arm/Kconfig | 1 +

[PATCH for-7.1 03/18] hw/arm/exynos4210: Put a9mpcore device into state struct

The exynos4210 SoC mostly creates its child devices as if it were board code. This includes the a9mpcore object. Switch that to a new-style "embedded in the state struct" creation, because in the next commit we're going to want to refer to the object again further down in the exynos4210_realize()

[PATCH for-7.1 12/18] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()

In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device instead of qemu_irq_split(). Signed-off-by: Peter Maydell --- include/hw/arm/exynos4210.h | 9 hw/arm/exynos4210.c | 41 + 2 files changed, 42 insertions(+), 8 deletions(-) diff

[PATCH v9 33/45] cxl/cxl-host: Add memops for CFMWS region.

From: Jonathan Cameron These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the

[PATCH for-7.1 11/18] hw/arm/exynos4210: Delete unused macro definitions

Delete a couple of #defines which are never used. Signed-off-by: Peter Maydell --- include/hw/arm/exynos4210.h | 4 1 file changed, 4 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index b564e3582bb..f0769a4045b 100644 --- a/include/hw/arm/exynos4210.h

[PATCH for-7.1 04/18] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct

The only time we use the int_gic_irq[] array in the Exynos4210Irq struct is in the exynos4210_realize() function: we initialize it with the GPIO inputs of the a9mpcore device, and then a bit later on we connect those to the outputs of the internal combiner. Now that the a9mpcore object is easily a

[PATCH for-7.1 16/18] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()

At this point, the function exynos4210_init_board_irqs() splits input IRQ lines to connect them to the input combiner, output combiner and external GIC. The function exynos4210_combiner_get_gpioin() splits some of the combiner input lines further to connect them to multiple different inputs on the

[PATCH v9 36/45] tests/acpi: q35: Allow addition of a CXL test.

Add exceptions for the DSDT and the new CEDT tables specific to a new CXL test in the following patch. Signed-off-by: Jonathan Cameron --- tests/data/acpi/q35/CEDT.cxl| 0 tests/data/acpi/q35/DSDT.cxl| 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 3 files

[PATCH for-7.1 05/18] hw/arm/exynos4210: Coalesce board_irqs and irq_table

The exynos4210 code currently has two very similar arrays of IRQs: * board_irqs is a field of the Exynos4210Irq struct which is filled in by exynos4210_init_board_irqs() with the appropriate qemu_irqs for each IRQ the board/SoC can assert * irq_table is a set of qemu_irqs pointed to from t

  1   2   >