Re: [PATCH 3/4] virtio-ccw: move device type declarations to .c files

On 28/03/2022 16.30, Paolo Bonzini wrote: Signed-off-by: Paolo Bonzini --- hw/s390x/s390-virtio-ccw.c| 1 + hw/s390x/vhost-scsi-ccw.c | 9 +++ hw/s390x/vhost-vsock-ccw.c| 9 +++ hw/s390x/virtio-ccw-9p.c | 9 +++ hw/s390x/virtio-ccw-balloon.c | 9 +++ hw/s390x/vi

Re: [PATCH 4/4] virtio-ccw: do not include headers for all virtio devices

On 28/03/2022 16.30, Paolo Bonzini wrote: Signed-off-by: Paolo Bonzini --- hw/s390x/ipl.c| 3 +++ hw/s390x/virtio-ccw.h | 16 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index e21776822a..ca56a1b29a 100644 --- a/hw

Re: [PATCH] target/riscv: Exit current TB after an sfence.vma

On Tue, Mar 29, 2022 at 11:15 PM Idan Horowitz wrote: > > On Wed, 30 Mar 2022 at 02:16, Atish Patra wrote: > > > > This is in for-next on Alistair's tree and fails to boot the kernel > > with the following error (found -d in_asm mode). > > Reverting the patch solves the issue. > > > > ---

Re: [PATCH] target/riscv: Exit current TB after an sfence.vma

On Wed, 30 Mar 2022 at 10:28, Atish Patra wrote: > > I tested on v5.17 built from defconfig for rv64. > > Here is the kernel code executing sfence.vma > https://elixir.bootlin.com/linux/v5.17/source/arch/riscv/kernel/head.S#L122 > I believe this is a kernel bug and not a QEMU one. They perform a

Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix

On Mon, Mar 28, 2022 at 11:11 PM Tsukasa OI wrote: > > Some bits in RISC-V `misa' CSR should not be reflected in the ISA > string. For instance, `S' and `U' (represents existence of supervisor > and user mode, respectively) in `misa' CSR must not be copied since > neither `S' nor `U' are valid si

RE: [PATCH V2 4/4] intel-iommu: PASID support

> From: Jason Wang > Sent: Tuesday, March 29, 2022 12:47 PM > > On Mon, Mar 28, 2022 at 2:47 PM Tian, Kevin wrote: > > > > > From: Jason Wang > > > Sent: Monday, March 28, 2022 10:31 AM > > > > > > On Thu, Mar 24, 2022 at 4:54 PM Tian, Kevin > wrote: > > > > > > > > > From: Jason Wang > > > >

[PATCH qemu v6 00/14] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v6 03/14] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PATCH qemu v6 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 32 + 2 files changed, 41 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH qemu v6 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 63193ba295..ea49394489 100644 --- a/target/riscv/vector_he

[PATCH qemu v6 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 +++ target/riscv/vector_helper.c| 12 2 files changed, 23 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tra

[PATCH qemu v6 02/14] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/ve

[PATCH qemu v6 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/

[PATCH qemu v6 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/vector_helper.c| 447 +--- 2 files changed, 262 insertions(+), 196 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

RE: [PATCH V2 4/4] intel-iommu: PASID support

> From: Jason Wang > Sent: Tuesday, March 29, 2022 12:49 PM > > On Mon, Mar 28, 2022 at 3:03 PM Tian, Kevin wrote: > > > > > From: Jason Wang > > > Sent: Monday, March 21, 2022 1:54 PM > > > > > > +/* > > > + * vtd-spec v3.4 3.14: > > > + * > > > + * """ > > > + * Requests-wi

[PATCH qemu v6 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 44 + target/riscv/vector_helper.c| 24 ++ 2 files changed, 68 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/targe

[PATCH qemu v6 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[PATCH qemu v6 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 22 target/riscv/vector_helper.c| 48 + 2 files changed, 70 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/

[PATCH qemu v6 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3592973973..0a18ecfa43 100644 --- a/target/riscv/vector_helper

[PATCH qemu v6 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 28 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v6 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 25 ++ target/riscv/vector_helper.c| 310 +--- 2 files changed, 197 insertions(+), 138 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

Re: [PATCH V2 4/4] intel-iommu: PASID support

On Wed, Mar 30, 2022 at 4:02 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Tuesday, March 29, 2022 12:49 PM > > > > On Mon, Mar 28, 2022 at 3:03 PM Tian, Kevin wrote: > > > > > > > From: Jason Wang > > > > Sent: Monday, March 21, 2022 1:54 PM > > > > > > > > +/* > > > > + * vtd-

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

在 2022/3/30 下午3:42, 陳約廷 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月28日 下午7:56 寫道： 在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD mailto:eop.c...@sifive.com>> Signed-off-by: eop Chen > Reviewed-by: Frank Chang > ---  target/r

Re: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry

On Wed, Mar 30, 2022 at 4:16 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Tuesday, March 29, 2022 12:52 PM > > > > > >>> > > >>> Currently the implementation of vtd_ce_get_rid2pasid_entry() is also > > >>> problematic. According to VT-d spec, RID2PASID field is effective only > > >>> wh

[PATCH qemu v6 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1854fe066..13cad80ae5 10

Re: [PATCH V2 4/4] intel-iommu: PASID support

On Wed, Mar 30, 2022 at 4:00 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Tuesday, March 29, 2022 12:47 PM > > > > On Mon, Mar 28, 2022 at 2:47 PM Tian, Kevin wrote: > > > > > > > From: Jason Wang > > > > Sent: Monday, March 28, 2022 10:31 AM > > > > > > > > On Thu, Mar 24, 2022 at 4:

Re: [RFC 2/8] numa: call ->ram_block_removed() in ram_block_notifer_remove()

On 23.03.22 12:17, Stefan Hajnoczi wrote: > When a RAMBlockNotifier is added, ->ram_block_added() is called with all > existing RAMBlocks. There is no equivalent ->ram_block_removed() call > when a RAMBlockNotifier is removed. > > The util/vfio-helpers.c code (the sole user of RAMBlockNotifier) is

RE: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry

> From: Jason Wang > Sent: Tuesday, March 29, 2022 12:52 PM > > > >>> > >>> Currently the implementation of vtd_ce_get_rid2pasid_entry() is also > >>> problematic. According to VT-d spec, RID2PASID field is effective only > >>> when ecap.rps is true otherwise PASID#0 is used for RID2PASID. I didn'

Re: [PATCH for-7.1] tests: Drop perl-Test-Harness from the CI containers / VMs

On 30/03/2022 10.19, Daniel P. Berrangé wrote: On Tue, Mar 29, 2022 at 12:28:08PM +0200, Thomas Huth wrote: The perl test harness is not necessary anymore since commit 3d2f73ef75 ("build: use "meson test" as the test harness"). Thus remove it from tests/lcitool/projects/qemu.yml, run "make lcito

Re: [PATCH] vdpa: Avoid reset when stop device

On Sat, Mar 26, 2022 at 3:59 AM Si-Wei Liu wrote: > > > > On 3/25/2022 12:18 AM, Michael Qiu wrote: > > > > > > On 2022/3/25 14:32, Si-Wei Liu Wrote: > >> > >> > >> On 3/23/2022 2:20 AM, Jason Wang wrote: > >>> Adding Eugenio, and Ling Shan. > >>> > >>> On Wed, Mar 23, 2022 at 4:58 PM <08005...@1

Re: [PATCH for-7.1] tests: Drop perl-Test-Harness from the CI containers / VMs

On Tue, Mar 29, 2022 at 12:28:08PM +0200, Thomas Huth wrote: > The perl test harness is not necessary anymore since commit 3d2f73ef75 > ("build: use "meson test" as the test harness"). Thus remove it from > tests/lcitool/projects/qemu.yml, run "make lcitool-refresh" and manually > clean the remaini

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 23.03.22 17:26, Thomas Huth wrote: > This program currently prints different results when run with TCG instead > of running on real s390x hardware: > > #include > > int overflow_32 (int x, int y) > { >int sum; >return ! __builtin_add_overflow (x, y, &sum); > } > > int overflow_6

Re: [PATCH 2/7] virtio-net: Fix indentation

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > From: Eugenio Pérez > > Signed-off-by: Eugenio Pérez Acked-by: Jason Wang > --- > hw/net/virtio-net.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c > index 484b215..ffaf

Re: [PATCH 1/7] virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > With MQ enabled vdpa device and non-MQ supporting guest e.g. > booting vdpa with mq=on over OVMF of single vqp, below assert > failure is seen: > > ../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >= > dev->vq_index && id

Re: [PATCH 2/2] target/s390x: Fix determination of overflow condition code after subtraction

On 23.03.22 17:26, Thomas Huth wrote: > Reported by Paul Eggert in > https://lists.gnu.org/archive/html/bug-gnulib/2021-09/msg00050.html > > This program currently prints different results when run with TCG instead > of running on real s390x hardware: > > #include > > int overflow_32 (int x,

Re: [PATCH 3/7] virtio-net: Only enable userland vq if using tap backend

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > From: Eugenio Pérez > > Qemu falls back on userland handlers even if vhost-user and vhost-vdpa > cases. These assumes a tap device can handle the packets. > > If a vdpa device fail to start, it can trigger a sigsegv because of > that. Do not r

Re: [PATCH v5 00/13] KVM: mm: fd-based approach for supporting KVM guest private memory

On 29/03/2022 18:01, Quentin Perret wrote: > On Monday 28 Mar 2022 at 18:58:35 (+), Sean Christopherson wrote: >> On Mon, Mar 28, 2022, Quentin Perret wrote: >>> Hi Sean, >>> >>> Thanks for the reply, this helps a lot. >>> >>> On Monday 28 Mar 2022 at 17:13:10 (+), Sean Christopherson wrote

Re: [PATCH 4/7] virtio: don't read pending event on host notifier if disabled

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > Previous commit prevents vhost-user and vhost-vdpa from using > userland vq handler via disable_ioeventfd_handler. The same > needs to be done for host notifier cleanup too, as the > virtio_queue_host_notifier_read handler still tends to read >

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

> > Ah seems I understand what you mean. > > One of my arguments is that "drain" - is not a lock against other > clients who want to modify the graph. Because, drained section allows > nested drained sections. > > And you try to solve it, by draining more things, this way, we'll drain > also the jo

Re: [PATCH 5/7] vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > ... such that no memory leaks on dangling net clients in case of > error. > > Signed-off-by: Si-Wei Liu Acked-by: Jason Wang > --- > net/vhost-vdpa.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/net/vhost-vdp

Re: [PATCH 7/7] vhost-vdpa: backend feature should set only once

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > The vhost_vdpa_one_time_request() branch in > vhost_vdpa_set_backend_cap() incorrectly sends down > iotls on vhost_dev with non-zero index. This may > end up with multiple VHOST_SET_BACKEND_FEATURES > ioctl calls sent down on the vhost-vdpa fd

Re: [PATCH 6/7] vhost-net: fix improper cleanup in vhost_net_start

On Wed, Mar 30, 2022 at 2:33 PM Si-Wei Liu wrote: > > vhost_net_start() missed a corresponding stop_one() upon error from > vhost_set_vring_enable(). While at it, make the error handling for > err_start more robust. No real issue was found due to this though. > > Signed-off-by: Si-Wei Liu > ---

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30/03/2022 10.52, David Hildenbrand wrote: On 23.03.22 17:26, Thomas Huth wrote: This program currently prints different results when run with TCG instead of running on real s390x hardware: #include int overflow_32 (int x, int y) { int sum; return ! __builtin_add_overflow (x,

RE: [PATCH v6 15/19] vfio-user: handle device interrupts

> -Original Message- > From: Jag Raman > Sent: 29 March 2022 20:07 > To: Stefan Hajnoczi > Cc: Alex Williamson ; qemu-devel de...@nongnu.org>; Michael S. Tsirkin ; Philippe Mathieu- > Daudé ; Paolo Bonzini ; Beraldo > Leal ; Daniel P. Berrangé ; > edua...@habkost.net; Marcel Apfelbaum ;

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30.03.22 11:29, Thomas Huth wrote: > On 30/03/2022 10.52, David Hildenbrand wrote: >> On 23.03.22 17:26, Thomas Huth wrote: >>> This program currently prints different results when run with TCG instead >>> of running on real s390x hardware: >>> >>> #include >>> >>> int overflow_32 (int x, i

Re: [PATCH v2] block/stream: Drain subtree around graph change

Am 29/03/2022 um 14:15 schrieb Hanna Reitz: > On 29.03.22 11:55, Vladimir Sementsov-Ogievskiy wrote: >> 29.03.2022 11:54, Hanna Reitz wrote: >>> On 28.03.22 12:24, Vladimir Sementsov-Ogievskiy wrote: 28.03.2022 11:09, Hanna Reitz wrote: > On 28.03.22 09:44, Hanna Reitz wrote: >> On

Re: [RFC PATCH v7 00/29] Add LoongArch softmmu support

Hi Richard. On 2022/3/29 上午2:13, Richard Henderson wrote: On 3/28/22 06:57, Xiaojuan Yang wrote: This series patch add softmmu support for LoongArch. The latest kernel:    * https://github.com/loongson/linux/tree/loongarch-next The latest uefi:    * https://github.com/loongson/edk2    * https:/

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

30.03.2022 12:09, Emanuele Giuseppe Esposito wrote: Ah seems I understand what you mean. One of my arguments is that "drain" - is not a lock against other clients who want to modify the graph. Because, drained section allows nested drained sections. And you try to solve it, by draining more th

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30/03/2022 11.34, David Hildenbrand wrote: On 30.03.22 11:29, Thomas Huth wrote: On 30/03/2022 10.52, David Hildenbrand wrote: On 23.03.22 17:26, Thomas Huth wrote: This program currently prints different results when run with TCG instead of running on real s390x hardware: #include

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30.03.22 11:42, Thomas Huth wrote: > On 30/03/2022 11.34, David Hildenbrand wrote: >> On 30.03.22 11:29, Thomas Huth wrote: >>> On 30/03/2022 10.52, David Hildenbrand wrote: On 23.03.22 17:26, Thomas Huth wrote: > This program currently prints different results when run with TCG instead

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

Am 30/03/2022 um 11:52 schrieb Vladimir Sementsov-Ogievskiy: > 30.03.2022 12:09, Emanuele Giuseppe Esposito wrote: >>> >>> Ah seems I understand what you mean. >>> >>> One of my arguments is that "drain" - is not a lock against other >>> clients who want to modify the graph. Because, drained sec

Re: [RFC PATCH v7 08/29] target/loongarch: Add LoongArch IOCSR instruction

On 2022/3/29 上午2:55, Richard Henderson wrote: On 3/28/22 06:57, Xiaojuan Yang wrote: +uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr, +   uint32_t size) +{ +    int cpuid = env_cpu(env)->cpu_index; +    CPUState  *cs = qemu_get_cpu(cpuid); +    e

Re: [RFC PATCH v7 07/29] target/loongarch: Add LoongArch CSR instruction

On 2022/3/29 上午2:34, Richard Henderson wrote: +target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr) +{ +    LoongArchCPU *cpu; +    int64_t v; + +    switch (csr) { +    case LOONGARCH_CSR_PGD: +    if (env->CSR_TLBRERA & 0x1) { +    v = env->CSR_TLBRBADV; +    } els

Re: [PATCH] target/sh4: Remove old README.sh4 file

On Wed, 30 Mar 2022 00:19:55 +0900, Thomas Huth wrote: > > This file didn't have any non-trivial update since it was initially > added in 2006, and looking at the content, it seems incredibly outdated, > saying e.g. "The sh4 target is not ready at all yet for integration in > qemu" or "A sh4 user-

Re: [RFC PATCH v7 02/29] target/loongarch: Add CSRs definition

On 2022/3/29 上午3:16, Richard Henderson wrote: On 3/28/22 06:57, Xiaojuan Yang wrote: +++ b/target/loongarch/cpu.h @@ -11,6 +11,7 @@   #include "exec/cpu-defs.h"   #include "fpu/softfloat-types.h"   #include "hw/registerfields.h" +#include "cpu-csr.h" Do you need this include here? No. I wo

[PATCH v2] vdpa: reset the backend device in stage of stop last vhost device

From: Michael Qiu Currently, when VM poweroff, it will trigger vdpa device(such as mlx bluefield2 VF) reset many times(with 1 datapath queue pair and one control queue, triggered 3 times), this leads to below issue: vhost VQ 2 ring restore failed: -22: Invalid argument (22) This because in vhos

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

> Weiwei Li 於 2022年3月30日 下午4:27 寫道： > 在 2022/3/30 下午3:42, 陳約廷 写道: >> >>> Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月28日 >>> 下午7:56 寫道： >>> >>> >>> 在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD mailto:eop.c...@sifive.com>> > Another question: max_elems is equal to total_elems when lmul

[PATCH v4 42/45] iotests.py: add VM.qmp_check() helper

I'm tired of this pattern being everywhere. Let's add a helper. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 4 1 file changed, 4 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 933e354822..88aea57f81 100644

[PATCH v4 44/45] block: bdrv_open_inherit: create BlockBackend only when necessary

We need this blk only for probing - let's create it only when we are going to probe. That's significant for further changes: we'll need to avoid permission update during open() when possible (to refresh them later of course). But blk_unref() leads to permission update. Instead of implementing extr

Re: [PATCH v7 12/17] vfio-user: IOMMU support for remote device

On Tue, Mar 29, 2022 at 07:58:51PM +, Jag Raman wrote: > > > > On Mar 29, 2022, at 10:48 AM, Stefan Hajnoczi wrote: > > > > On Tue, Mar 29, 2022 at 02:12:40PM +, Jag Raman wrote: > >>> On Mar 29, 2022, at 8:35 AM, Stefan Hajnoczi wrote: > >>> On Fri, Mar 25, 2022 at 03:19:41PM -0400, J

Re: [PATCH v7 14/17] vfio-user: handle PCI BAR accesses

On Tue, Mar 29, 2022 at 03:51:17PM +, Jag Raman wrote: > > > > On Mar 29, 2022, at 8:50 AM, Stefan Hajnoczi wrote: > > > > On Fri, Mar 25, 2022 at 03:19:43PM -0400, Jagannathan Raman wrote: > >> @@ -324,6 +325,170 @@ static void dma_unregister(vfu_ctx_t *vfu_ctx, > >> vfu_dma_info_t *info)

[PATCH v4 43/45] iotests: add filter-insertion

Demonstrate new API for filter insertion and removal. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/tests/filter-insertion | 253 ++ tests/qemu-iotests/tests/filter-insertion.out | 5 + 2 files changed, 258 insertions(+) create mode 100755 tests/qemu-i

[PATCH v4 39/45] block: bdrv_get_xdbg_block_graph(): report export ids

Currently for block exports we report empty blk names. That's not good. Let's try to find corresponding block export and report its id. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block.c | 4 block/export/export.c | 13 + include/block/export.h

[PATCH v4 41/45] iotests.py: introduce VM.assert_edges_list() method

Add an alternative method to check block graph, to be used in further commit. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 17 + 1 file changed, 17 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 0

[PATCH v4 40/45] iotests.py: qemu_img_create: use imgfmt by default

Less typing: let's use imgfmt by default if user doesn't specify neither -f nor --image-opts. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 8c

[PATCH qemu v7 02/14] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/ve

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30/03/2022 11.47, David Hildenbrand wrote: On 30.03.22 11:42, Thomas Huth wrote: On 30/03/2022 11.34, David Hildenbrand wrote: On 30.03.22 11:29, Thomas Huth wrote: On 30/03/2022 10.52, David Hildenbrand wrote: On 23.03.22 17:26, Thomas Huth wrote: This program currently prints different

Re: [PATCH v3 11/14] qapi: fix example of MEMORY_FAILURE

Hi, On Tue, Mar 29, 2022 at 05:52:47PM +0200, Markus Armbruster wrote: > Victor Toso writes: > > > Example output lacks mandatory member @timestamp. Provide it. > > > > While @flags is an optional member, > > Uh, it isn't. Wow! I was so sure I saw "*flags" before. Nice catch. > >

[PATCH qemu v7 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1462a664c6..ed72fffb71 100644 --- a/target/riscv/vector_helper

[PATCH qemu v7 03/14] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PATCH qemu v7 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 25 ++ target/riscv/vector_helper.c| 310 +--- 2 files changed, 197 insertions(+), 138 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v4 45/45] block/copy-before-write: correct permission scheme

Finally we can strictly unshare write on source node, as all write must go through copy-before-write filter. For this to work: - Declare independent close, so that blockdev-del transaction action may detach children of removed node at prepare phase (that's for filter removement). We can do

[PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v7 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 44 + target/riscv/vector_helper.c| 24 ++ 2 files changed, 68 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/targe

Re: [PATCH v5 00/13] KVM: mm: fd-based approach for supporting KVM guest private memory

On Wednesday 30 Mar 2022 at 09:58:27 (+0100), Steven Price wrote: > On 29/03/2022 18:01, Quentin Perret wrote: > > On Monday 28 Mar 2022 at 18:58:35 (+), Sean Christopherson wrote: > >> On Mon, Mar 28, 2022, Quentin Perret wrote: > >>> Hi Sean, > >>> > >>> Thanks for the reply, this helps a lot

Re: [PATCH 1/2] target/s390x: Fix determination of overflow condition code after addition

On 30/03/2022 12.12, Thomas Huth wrote: On 30/03/2022 11.47, David Hildenbrand wrote: On 30.03.22 11:42, Thomas Huth wrote: On 30/03/2022 11.34, David Hildenbrand wrote: On 30.03.22 11:29, Thomas Huth wrote: On 30/03/2022 10.52, David Hildenbrand wrote: On 23.03.22 17:26, Thomas Huth wrote:

[PATCH qemu v7 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85a0c667e..7884314779 100644 --- a/target/riscv/vector_he

[PATCH qemu v7 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[PATCH qemu v7 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 +++ target/riscv/vector_helper.c| 12 2 files changed, 23 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tra

[PATCH qemu v7 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 target/riscv/vector_helper.c| 28 + 2 files changed, 37 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/risc

[PATCH qemu v7 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/

[PATCH qemu v7 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 22 target/riscv/vector_helper.c| 48 + 2 files changed, 70 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/

Re: [PATCH v2] vdpa: reset the backend device in stage of stop last vhost device

On Wed, Mar 30, 2022 at 06:02:41AM -0400, 08005...@163.com wrote: It's an empty patch. -- MST

[PATCH qemu v7 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bd0aeda03f..057d67211b 10

[PATCH qemu v7 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 28 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

Re: [RFC 7/8] blkio: implement BDRV_REQ_REGISTERED_BUF optimization

On Tue, Mar 29, 2022 at 05:24:30PM +0200, Stefano Garzarella wrote: > On Wed, Mar 23, 2022 at 11:17:26AM +, Stefan Hajnoczi wrote: > > Avoid bounce buffers when QEMUIOVector elements are within previously > > registered bdrv_register_buf() buffers. > > > > The idea is that emulated storage con

[PATCH qemu v7 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/vector_helper.c| 447 +--- 2 files changed, 262 insertions(+), 196 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

Re: [PATCH v1 1/9] qmp: Add dump machine type compatible properties

29.03.2022 00:15, Maxim Davydov wrote: This patch adds the ability to get all the compat_props of the corresponding supported machines for their comparison. Example: { "execute" : "query-machines", "arguments" : { "is-full" : true } } Signed-off-by: Maxim Davydov --- hw/core/machine-qmp-cmds

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

On 17.03.22 17:23, Emanuele Giuseppe Esposito wrote: Am 09/03/2022 um 14:26 schrieb Emanuele Giuseppe Esposito: * Drains allow the caller (either main loop or iothread running the context) to wait all in_flights requests and operations of a BDS: normal drains target a given node and is parents,

Re: [PATCH v1 2/9] pci: add null-pointer check

29.03.2022 00:15, Maxim Davydov wrote: Call pci_bus_get_w64_range can fail with the segmentation fault. For example, this can happen during attempt to get pci-hole64-end immediately after initialization. So, immediately after initialization, h->bus is NULL? The significant bit is, is the value

Re: [PATCH v1 3/9] mem: appropriate handling getting mem region

29.03.2022 00:15, Maxim Davydov wrote: Attempt to get memory region if the device doesn't have hostmem may not be an error. This can be happen immediately after initialization (getting value without default one). Signed-off-by: Maxim Davydov --- hw/i386/sgx-epc.c | 5 - hw/mem/nvdimm.c

Re: [PATCH v1 6/9] chardev: add appropriate getting address

29.03.2022 00:15, Maxim Davydov wrote: Attempt to get address after initialization shouldn't fail on assert in the qapi automatically generated code. As a possible solution, it can return null type. But at some point this address appears? May be we try to query it too early, or we need some mo

Re: [PATCH for-7.0?] tcg/aarch64: Use 'ull' suffix to force 64-bit constant

On 30/3/22 01:49, Richard Henderson wrote: Typo used only 'ul' suffix, which is still 32-bits for windows host. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/947 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions

[PATCH for-7.0] meson.build: Fix dependency of page-vary-common.c to config-poison.h

Before compiling page-vary-common.c, we have to make sure that config-poison.h has been generated (which is in the "genh" list). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/948 Signed-off-by: Thomas Huth --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

Re: [RFC PATCH 0/5] Removal of AioContext lock, bs->parents and ->children: proof of concept

Am 30/03/2022 um 12:53 schrieb Hanna Reitz: > On 17.03.22 17:23, Emanuele Giuseppe Esposito wrote: >> >> Am 09/03/2022 um 14:26 schrieb Emanuele Giuseppe Esposito: > * Drains allow the caller (either main loop or iothread running > the context) to wait all in_flights requests and operati

Re: [PATCH for-7.0] meson.build: Fix dependency of page-vary-common.c to config-poison.h

Hi Thomas, On 30/3/22 13:48, Thomas Huth wrote: Before compiling page-vary-common.c, we have to make sure that config-poison.h has been generated (which is in the "genh" list). I am a bit confused, "config-poison.h" is include by "exec/poison.h" which is included by "qemu/osdep.h" for all non-

Re: [PATCH 1/5] trace: fix compilation with lttng-ust >= 2.13

On Mon, Mar 28, 2022 at 12:47:13PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > On Fedora 36, with lttng-ust 2.13.1, compilation fails with: > > In file included from trace/trace-ust-all.h:49085, > from trace/trace-ust-all.c:13: > /usr/include/lttng/tr

Re: [PATCH v8 04/46] hw/cxl/device: Introduce a CXL device (8.2.8)

On Tue, 29 Mar 2022 12:53:51 -0700 Davidlohr Bueso wrote: > On Tue, 29 Mar 2022, Adam Manzanares wrote: > >> +typedef struct cxl_device_state { > >> +MemoryRegion device_registers; > >> + > >> +/* mmio for device capabilities array - 8.2.8.2 */ > >> +MemoryRegion device; > >> +Mem

Re: [PATCH v3 0/3] util/thread-pool: Expose minimun and maximum size

On Wed, Mar 16, 2022 at 02:53:20PM +0100, Nicolas Saenz Julienne wrote: > As discussed on the previous RFC[1] the thread-pool's dynamic thread > management doesn't play well with real-time and latency sensitive > systems. This series introduces a set of controls that'll permit > achieving more dete

Re: [PATCH for-7.0] meson.build: Fix dependency of page-vary-common.c to config-poison.h

On 30/03/2022 14.05, Philippe Mathieu-Daudé wrote: Hi Thomas, On 30/3/22 13:48, Thomas Huth wrote: Before compiling page-vary-common.c, we have to make sure that config-poison.h has been generated (which is in the "genh" list). I am a bit confused, "config-poison.h" is include by "exec/poison

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