RE: [PATCH V2 4/4] intel-iommu: PASID support

> From: Jason Wang > Sent: Monday, March 21, 2022 1:54 PM > > +/* > + * vtd-spec v3.4 3.14: > + * > + * """ > + * Requests-with-PASID with input address in range 0xFEEx_ are > + * translated normally like any other request-with-PASID through > + * DMA-remapping hard

[PATCH qemu v5 02/14] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/ve

[PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[PATCH qemu v5 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/vector_helper.c| 447 +--- 2 files changed, 262 insertions(+), 196 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH qemu v5 03/14] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PATCH qemu v5 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/

[PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 32 + 2 files changed, 41 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH qemu v5 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 25 ++ target/riscv/vector_helper.c| 310 +--- 2 files changed, 197 insertions(+), 138 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH qemu v5 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 target/riscv/vector_helper.c| 28 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/in

[PATCH qemu v5 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 61ef60f278..0df06cd964 10

[PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 +++ target/riscv/vector_helper.c| 12 2 files changed, 23 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tra

[PULL 1/1] target/ppc: fix helper_xvmadd* argument order

From: Matheus Ferst When the xsmadd* insns were moved to decodetree, the helper arguments were reordered to better match the PowerISA description. The same macro is used to declare xvmadd* helpers, but the translation macro of these insns was not changed accordingly. Reported-by: Víctor Colombo

[PATCH qemu v5 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5449cc403d..a44666 100644 --- a/target/riscv/vector_he

[PATCH qemu v5 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6557a75e79..b5020f9d8c 100644 --- a/target/riscv/vector_helper

[PATCH qemu v5 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 22 target/riscv/vector_helper.c| 48 + 2 files changed, 70 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/

[PATCH qemu v5 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 44 + target/riscv/vector_helper.c| 24 ++ 2 files changed, 68 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/targe

[PULL 0/1] ppc queue

The following changes since commit 3d31fe4d662f13c70eb7e87f29513623ccd76322: Merge tag 'pull-target-arm-20220325' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-03-25 15:02:39 +) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-

Re: [PATCH v2] block/stream: Drain subtree around graph change

On 25.03.22 17:37, Vladimir Sementsov-Ogievskiy wrote: 24.03.2022 17:09, Hanna Reitz wrote: When the stream block job cuts out the nodes between top and base in stream_prepare(), it does not drain the subtree manually; it fetches the base node, and tries to insert it as the top node's backing no

"Future directions" vs. "TODO" in doc comments (was: [PATCH 01/14] qapi: BlockExportRemoveMode: move comments to TODO)

Victor Toso writes: > Hi, > > On Fri, Mar 25, 2022 at 11:11:23AM -0400, John Snow wrote: >> On Fri, Mar 25, 2022, 8:33 AM Markus Armbruster wrote: [...] >> > Doc comments embed user documentation in the source code. The doc >> > generator extracts it. >> > >> > TODOs are generally for develop

Re: [PATCH v2] block/stream: Drain subtree around graph change

On 28.03.22 09:44, Hanna Reitz wrote: On 25.03.22 17:37, Vladimir Sementsov-Ogievskiy wrote: 24.03.2022 17:09, Hanna Reitz wrote: When the stream block job cuts out the nodes between top and base in stream_prepare(), it does not drain the subtree manually; it fetches the base node, and tries

[PATCH] chardev: avoid use-after-free when client disconnect

IOWatchPoll object did not hold the @ioc and @src objects reference, then io_watch_poll_prepare execute in IO thread, if IOWatchPoll removed by mian thread, io_watch_poll_prepare may execute at last chance and access the freed @ioc or @src object. In IO thread monitor scene, the IO thread used to

Re: [libvirt RFC] virFile: new VIR_FILE_WRAPPER_BIG_PIPE to improve performance

On Sat, Mar 26, 2022 at 04:49:46PM +0100, Claudio Fontana wrote: > On 3/25/22 12:29 PM, Daniel P. Berrangé wrote: > > On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote: > >> On 3/17/22 4:03 PM, Dr. David Alan Gilbert wrote: > >>> * Claudio Fontana (cfont...@suse.de) wrote: > On 3

Re: [PATCH V2 4/4] intel-iommu: PASID support

On 2022/3/21 13:54, Jason Wang wrote: This patch introduce ECAP_PASID via "x-pasid-mode". Based on the existing support for scalable mode, we need to implement the following missing parts: 1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation with PASID should it be taggin

[PATCH 2/5] arm/digic: fix format-truncation warning

From: Marc-André Lureau ../hw/arm/digic.c: In function ‘digic_init’: ../hw/arm/digic.c:45:54: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 5 [-Werror=format-truncation=] 45 | snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);

[PATCH 0/5] Compilation fixes for 7.0

From: Marc-André Lureau Hi, UST tracing fails to build on Fedora 36, with lttng-ust-2.13.1-2.fc36.x86_64. There are also various GCC 12.0.1 warnings worth fixing. Marc-André Lureau (5): trace: fix compilation with lttng-ust >= 2.13 arm/digic: fix format-truncation warning arm/allwinner-a

[PATCH 1/5] trace: fix compilation with lttng-ust >= 2.13

From: Marc-André Lureau On Fedora 36, with lttng-ust 2.13.1, compilation fails with: In file included from trace/trace-ust-all.h:49085, from trace/trace-ust-all.c:13: /usr/include/lttng/tracepoint-event.h:67:10: error: #include expects "FILENAME" or 67 | #include LTTNG_UST_

[PATCH 3/5] arm/allwinner-a10: fix format-overflow warning

From: Marc-André Lureau ../hw/arm/allwinner-a10.c: In function ‘aw_a10_realize’: ../hw/arm/allwinner-a10.c:135:35: error: ‘%d’ directive writing between 1 and 11 bytes into a region of size 8 [-Werror=format-overflow=] 135 | sprintf(bus, "usb-bus.%d", i); |

[PATCH 4/5] intc/exynos4210_gic: fix format-overflow warning

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- hw/intc/exynos4210_gic.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index bc73d1f11524..5b6f4330a5f3 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/

Re: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry

On 2022/3/28 10:27, Jason Wang wrote: On Thu, Mar 24, 2022 at 4:21 PM Tian, Kevin wrote: From: Jason Wang Sent: Monday, March 21, 2022 1:54 PM We use to warn on wrong rid2pasid entry. But this error could be triggered by the guest and could happens during initialization. So let's don't wa

Re: [PATCH v2 02/14] qapi: fix example of BLOCK_IMAGE_CORRUPTED event

Victor Toso writes: > Fatal is not optional. Recognizing that "Fatal" refers to member "fatal" takes mental effort. Always use identifiers verbatim, including case. Where that makes for confusing prose, prefix with a @ like @fatal, or rephrase, like "The member fatal". > > Signed-off-by: Victo

[PATCH 5/5] s390x/tcg: fix format-truncation warning

From: Marc-André Lureau ../target/s390x/tcg/translate.c: In function ‘s390x_translate_init’: ../target/s390x/tcg/translate.c:224:64: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 3 [-Werror=format-truncation=] 224 | snprintf(cpu_reg

Re: [PATCH 5/5] s390x/tcg: fix format-truncation warning

On 28/03/2022 10.47, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau ../target/s390x/tcg/translate.c: In function ‘s390x_translate_init’: ../target/s390x/tcg/translate.c:224:64: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 3 [-W

Re: [PATCH 5/5] s390x/tcg: fix format-truncation warning

On 28.03.22 10:47, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > ../target/s390x/tcg/translate.c: In function ‘s390x_translate_init’: > ../target/s390x/tcg/translate.c:224:64: error: ‘%d’ directive output may be > truncated writing between 1 and 11 bytes into a region of size

[PATCH v2.1] qapi: fix example of BLOCK_IMAGE_CORRUPTED event

Example output lacks mandatory member @fatal. Provide it. Example output shows a value of @msg no version of the code produces. No big deal, but replace it anyway by one that today's code does produce. Signed-off-by: Victor Toso --- qapi/block-core.json | 7 +++ 1 file changed, 3 insertio

Re: [PATCH v2 02/14] qapi: fix example of BLOCK_IMAGE_CORRUPTED event

Hi, On Mon, Mar 28, 2022 at 10:54:41AM +0200, Markus Armbruster wrote: > Victor Toso writes: > > > Fatal is not optional. > > Recognizing that "Fatal" refers to member "fatal" takes mental > effort. Always use identifiers verbatim, including case. > Where that makes for confusing prose, prefix

Re: [PATCH 1/2] gdbstub: Set current_cpu for memory read write

On Mon, 28 Mar 2022 at 03:10, Bin Meng wrote: > IMHO it's too bad to just ignore this bug forever. > > This is a valid use case. It's not about whether we intentionally want > to inspect the GIC register value from gdb. The case is that when > single stepping the source codes it triggers the core

Re: [PATCH 2/5] arm/digic: fix format-truncation warning

On Mon, 28 Mar 2022 at 09:47, wrote: > > From: Marc-André Lureau > > ../hw/arm/digic.c: In function ‘digic_init’: > ../hw/arm/digic.c:45:54: error: ‘%d’ directive output may be truncated > writing between 1 and 11 bytes into a region of size 5 > [-Werror=format-truncation=] >45 | sn

RE: [PATCH 2/4] net/colo: Fix a "double free" crash to clear the conn_list

> -Original Message- > From: lizhij...@fujitsu.com > Sent: Monday, March 21, 2022 11:06 AM > To: Zhang, Chen ; Jason Wang > ; lizhij...@fujitsu.com > Cc: qemu-dev ; Like Xu > Subject: Re: [PATCH 2/4] net/colo: Fix a "double free" crash to clear the > conn_list > > > > On 09/03/2022 1

Re: [PATCH 3/5] arm/allwinner-a10: fix format-overflow warning

On Mon, 28 Mar 2022 at 09:48, wrote: > > From: Marc-André Lureau > > ../hw/arm/allwinner-a10.c: In function ‘aw_a10_realize’: > ../hw/arm/allwinner-a10.c:135:35: error: ‘%d’ directive writing between 1 and > 11 bytes into a region of size 8 [-Werror=format-overflow=] > 135 | sprint

Re: [PATCH 4/5] intc/exynos4210_gic: fix format-overflow warning

On Mon, 28 Mar 2022 at 09:48, wrote: > > From: Marc-André Lureau > > Signed-off-by: Marc-André Lureau > --- > hw/intc/exynos4210_gic.c | 9 +++-- > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c > index bc73d1f11524..5b6f

Re: [libvirt RFC] virFile: new VIR_FILE_WRAPPER_BIG_PIPE to improve performance

On 3/28/22 10:31 AM, Daniel P. Berrangé wrote: > On Sat, Mar 26, 2022 at 04:49:46PM +0100, Claudio Fontana wrote: >> On 3/25/22 12:29 PM, Daniel P. Berrangé wrote: >>> On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote: On 3/17/22 4:03 PM, Dr. David Alan Gilbert wrote: > * Cla

Re: [PATCH 2/5] arm/digic: fix format-truncation warning

On 28/03/2022 10.47, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau ../hw/arm/digic.c: In function ‘digic_init’: ../hw/arm/digic.c:45:54: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 5 [-Werror=format-truncation=] 45 |

Re: [libvirt RFC] virFile: new VIR_FILE_WRAPPER_BIG_PIPE to improve performance

On 3/28/22 10:31 AM, Daniel P. Berrangé wrote: > On Sat, Mar 26, 2022 at 04:49:46PM +0100, Claudio Fontana wrote: >> On 3/25/22 12:29 PM, Daniel P. Berrangé wrote: >>> On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote: On 3/17/22 4:03 PM, Dr. David Alan Gilbert wrote: > * Cla

Re: [libvirt RFC] virFile: new VIR_FILE_WRAPPER_BIG_PIPE to improve performance

On 3/28/22 11:19 AM, Claudio Fontana wrote: > On 3/28/22 10:31 AM, Daniel P. Berrangé wrote: >> On Sat, Mar 26, 2022 at 04:49:46PM +0100, Claudio Fontana wrote: >>> On 3/25/22 12:29 PM, Daniel P. Berrangé wrote: On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote: > On 3/17/22

Re: [PATCH] kvm/arm64: Fix memory section did not set to kvm

On 2022/3/25 23:00, Peter Maydell wrote: On Fri, 25 Mar 2022 at 14:42, wrote: I found this issue on qmeu 4.2 with host linux 4.19, I want to use qxl on arm64. on arm64, default page size is 64k, and the qxl_rom_size is fixed 8192. OK, so the fix to this is "use a newer QEMU". but when I

Re: [PATCH v2 1/2] Replacing CONFIG_VNC_PNG with CONFIG_PNG

Hi, Hope this mail finds you well. I have updated the code as required and would be grateful if you could review and suggest changes that are needed to be implemented. In case no change is required, please do let me know the next steps for the same. Regards, Kshitij Suri On 22/03/22 4:19 pm,

Re: [PATCH v2 2/2] Added parameter to take screenshot with screendump as PNG

Hi, Hope this mail finds you well. I have updated the code as required and would be grateful if you could review and suggest changes that are needed to be implemented. In case no change is required, please do let me know the next steps for the same. Regards, Kshitij Suri On 22/03/22 4:19 pm,

Re: [PATCH v2 2/2] Added parameter to take screenshot with screendump as PNG

On Tue, Mar 22, 2022 at 10:49:53AM +, Kshitij Suri wrote: > Currently screendump only supports PPM format, which is un-compressed and not > standard. Added a "format" parameter to qemu monitor screendump capabilites > to support PNG image capture using libpng. The param was added in QAPI schema

Re: [PATCH v2 2/2] Added parameter to take screenshot with screendump as PNG

On 28/03/22 3:22 pm, Daniel P. Berrangé wrote: On Tue, Mar 22, 2022 at 10:49:53AM +, Kshitij Suri wrote: Currently screendump only supports PPM format, which is un-compressed and not standard. Added a "format" parameter to qemu monitor screendump capabilites to support PNG image capture us

Re: Proposal for a regular upstream performance testing

On Mon, Mar 28, 2022 at 08:18:43AM +0200, Lukáš Doktor wrote: > Hello Stefan, folks, > > I seem to have another hit, an improvement actually and it seems to be > bisected all the way to you, Stefan. Let me use this as another example of > how such process could look like and we can use this to h

Re: [PATCH 5/5] s390x/tcg: fix format-truncation warning

Hi On Mon, Mar 28, 2022 at 12:59 PM Thomas Huth wrote: > > On 28/03/2022 10.47, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > ../target/s390x/tcg/translate.c: In function ‘s390x_translate_init’: > > ../target/s390x/tcg/translate.c:224:64: error: ‘%d’ directive output may

Re: [PATCH v2] block/stream: Drain subtree around graph change

28.03.2022 11:09, Hanna Reitz wrote: On 28.03.22 09:44, Hanna Reitz wrote: On 25.03.22 17:37, Vladimir Sementsov-Ogievskiy wrote: 24.03.2022 17:09, Hanna Reitz wrote: When the stream block job cuts out the nodes between top and base in stream_prepare(), it does not drain the subtree manually;

Re: [libvirt RFC] virFile: new VIR_FILE_WRAPPER_BIG_PIPE to improve performance

On 3/26/22 4:49 PM, Claudio Fontana wrote: > On 3/25/22 12:29 PM, Daniel P. Berrangé wrote: >> On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote: >>> On 3/17/22 4:03 PM, Dr. David Alan Gilbert wrote: * Claudio Fontana (cfont...@suse.de) wrote: > On 3/17/22 2:41 PM, Claudio Fo

Re: [PATCH 5/5] s390x/tcg: fix format-truncation warning

On 28/03/2022 12.22, Marc-André Lureau wrote: Hi On Mon, Mar 28, 2022 at 12:59 PM Thomas Huth wrote: On 28/03/2022 10.47, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau ../target/s390x/tcg/translate.c: In function ‘s390x_translate_init’: ../target/s390x/tcg/translate.c:224:64:

Re: Proposal for a regular upstream performance testing

Dne 28. 03. 22 v 11:57 Stefan Hajnoczi napsal(a): > On Mon, Mar 28, 2022 at 08:18:43AM +0200, Lukáš Doktor wrote: >> Hello Stefan, folks, >> >> I seem to have another hit, an improvement actually and it seems to be >> bisected all the way to you, Stefan. Let me use this as another example of >> h

Re: [PATCH v2.1] qapi: fix example of BLOCK_IMAGE_CORRUPTED event

Victor Toso writes: > Example output lacks mandatory member @fatal. Provide it. > > Example output shows a value of @msg no version of the code > produces. No big deal, but replace it anyway by one that > today's code does produce. > > Signed-off-by: Victor Toso > --- > qapi/block-core.json |

Re: [PATCH v2 02/14] qapi: fix example of BLOCK_IMAGE_CORRUPTED event

Victor Toso writes: > Hi, > > On Mon, Mar 28, 2022 at 10:54:41AM +0200, Markus Armbruster wrote: >> Victor Toso writes: >> >> > Fatal is not optional. >> >> Recognizing that "Fatal" refers to member "fatal" takes mental >> effort. Always use identifiers verbatim, including case. >> Where that

Re: [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

在 2022/3/1 下午5:07, ~eopxd 写道: From: eopXD This is the first commit regarding the tail agnostic behavior. Added option 'rvv_ta_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1

Re: [PATCH] kvm/arm64: Fix memory section did not set to kvm

On Mon, 28 Mar 2022 at 10:42, Cong Liu wrote: > On 2022/3/25 23:00, Peter Maydell wrote: > > This is correct behaviour. If the memory region is less than > > a complete host page then it is not possible for KVM to > > map it into the guest as directly accessible memory, > > because that can only b

Re: [PATCH] schemas: add missing vim modeline

Victor Toso writes: > This is the last qapi schema that is missing the modeline. > Fixes 7e7237cd2b "schemas: add missing vim modeline" > > Signed-off-by: Victor Toso > --- > qapi/pragma.json | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/qapi/pragma.json b/qapi/pragma.json > index

Re: [PATCH] schemas: add missing vim modeline

Victor Toso writes: > This is the last qapi schema that is missing the modeline. > Fixes 7e7237cd2b "schemas: add missing vim modeline" > > Signed-off-by: Victor Toso Reviewed-by: Markus Armbruster

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++ target/riscv/vector_helper.c| 32 + 2 files changed, 41 insertions(+) diff --git a/target/riscv/insn_

Re: [RFC PATCH 11/17] hw/sd: Add eMMC support

Hi Cédric, On 3/18/22 14:28, Cédric Le Goater wrote: > The initial eMMC support from Vincent Palatin was largely reworked to > match the current SD framework. The parameters mimick a real 4GB eMMC, > but it can be set to various sizes. > > This adds a new QOM object class for EMMC devices. That

回复: Re: [PATCH] kvm/arm64: Fix memory section did not set to kvm

thanks for you explain, I will learn it later.in the scenario of rom bar size 8k, page size 64k, the value of 'size = ROUND_UP(size, qemu_real_host_page_size)' is 64k, kvm_align_sectionalso return 64k bytes.  just the same size as the size of RAMBlock. I stilldid not understand why it is wrong.the

Re: [PATCH v1 8/9] aspeed: Add an AST1030 eval board

Hello Jamin, On 3/22/22 03:51, Jamin Lin wrote: From: Steven Lee The image should be supplied with ELF binary. $ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee I don't see the benefits of duplicatin

Re: [PATCH v8 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows.

Jonathan Cameron writes: > From: Jonathan Cameron > > The concept of these is introduced in [1] in terms of the > description the CEDT ACPI table. The principal is more general. > Unlike once traffic hits the CXL root bridges, the host system > memory address routing is implementation defined an

Re: [External] [PATCH v3 4/6] crypto: Implement RSA algorithm by hogweed

> On Mar 23, 2022, at 9:50 PM, Daniel P. Berrangé wrote: > > On Wed, Mar 23, 2022 at 10:49:10AM +0800, zhenwei pi wrote: >> From: Lei He >> >> Introduce ASN.1 decoder, and implement RSA algorithm by hogweed >> from nettle. Thus QEMU supports a 'real' RSA backend to handle >> request from gue

[RFC PATCH v7 02/29] target/loongarch: Add CSRs definition

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 236 + target/loongarch/cpu.c | 35 ++ target/loongarch/cpu.h | 57 + 3 files changed, 328 insertions(+) create mode 100644 target/loongarch/cpu-csr.h

[RFC PATCH v7 04/29] target/loongarch: Implement qmp_query_cpu_definitions()

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- qapi/machine-target.json | 6 -- target/loongarch/cpu.c | 26 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/qapi/machine-target.json b/qapi/machine-target.

[RFC PATCH v7 00/29] Add LoongArch softmmu support

This series patch add softmmu support for LoongArch. The latest kernel: * https://github.com/loongson/linux/tree/loongarch-next The latest uefi: * https://github.com/loongson/edk2 * https://github.com/loongson/edk2-platforms The manual: * https://github.com/loongson/LoongArch-Documentation/

[RFC PATCH v7 06/29] target/loongarch: Add MMU support for LoongArch CPU.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu-param.h | 2 +- target/loongarch/cpu.c| 30 target/loongarch/cpu.h| 42 - target/loongarch/internals.h | 9 + target/loongarch/machine.c| 17 ++ target/loongarch/meson.build | 1

[RFC PATCH v7 07/29] target/loongarch: Add LoongArch CSR instruction

This includes: - CSRRD - CSRWR - CSRXCHG Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h| 88 target/loongarch/csr_helper.c | 112 target/loongarch/disas.c | 15 +++ targ

[RFC PATCH v7 05/29] target/loongarch: Add constant timer support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/constant_timer.c | 62 +++ target/loongarch/cpu.h| 10 + target/loongarch/meson.build | 1 + 3 files changed, 73 insertions(+) create mode 100644 target/loongarch/constant

[RFC PATCH v7 08/29] target/loongarch: Add LoongArch IOCSR instruction

This includes: - IOCSR{RD/WR}.{B/H/W/D} Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h| 4 + target/loongarch/disas.c | 8 + target/loongarch/helper.h | 2 + .../insn_trans/trans_privileged.c

[RFC PATCH v7 01/29] target/loongarch: Add system emulation introduction

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 8 +++ docs/system/loongarch/loongson3.rst | 37 + target/loongarch/README | 28 ++ 3 files changed, 73 insertions(+) create mode 10064

[RFC PATCH v7 03/29] target/loongarch: Add basic vmstate description of CPU.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 3 ++ target/loongarch/internals.h | 4 ++ target/loongarch/machine.c | 85 target/loongarch/meson.build | 6 +++ 4 files changed, 98

[RFC PATCH v7 17/29] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 4 + hw/intc/loongarch_pch_pic.c | 488 hw/intc/meson.build | 1 + hw/intc/trace-events

[RFC PATCH v7 14/29] hw/loongarch: Add support loongson3 virt machine type.

Emulate a 3A5000 board use the new loongarch instruction. 3A5000 belongs to the Loongson3 series processors. The board consists of a 3A5000 cpu model and the virt bridge. The host 3A5000 board is really complicated and contains many functions.Now for the tcg softmmu mode only part functions are emu

[RFC PATCH v7 10/29] target/loongarch: Add other core instructions support

This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.h| 2 + target/loongarch/disas.c | 17 target/loongarch/helper.h | 4 + .../insn_trans/tran

[RFC PATCH v7 24/29] hw/loongarch: Add default bios startup support.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 4 ++ hw/loongarch/fw_cfg.c| 33 ++ hw/loongarch/fw_cfg.h| 15 +++ hw/loongarch/loongson3.c | 76 +++- hw/loongarch/meson.build

[RFC PATCH v7 09/29] target/loongarch: Add TLB instruction support

This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 + target/loongarch/helper.h | 12 + .../insn_trans/trans_privileged.c.inc |

[RFC PATCH v7 20/29] hw/loongarch: Add irq hierarchy for the system

This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS| 1 + hw/loongarch/loongson3.c | 99 ++ include/hw/pci-host/ls7a.h | 30 3 files changed, 130 insertions(

[RFC PATCH v7 12/29] target/loongarch: Add timer related instructions support.

This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/helper.h | 1 + target/loongarch/insn_trans/trans_extra.c.inc | 32 +++ target/loongarch/op_helper.c | 6 target/loongarc

[RFC PATCH v7 21/29] Enable common virtio pci support for LoongArch

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- softmmu/qdev-monitor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c index 12fe60c467..bb5897fc76 100644 --- a/softmmu/qdev-monitor.c +++ b/softmmu/qdev-monitor.c @@ -

[PATCH 0/2] ppc: fix vcpu hotunplug leak in spapr_realize_vcpu

Hi, This is a memory leak found by Valgrind when testing vcpu hotplug/unplug in pSeries guests. Other vcpu hotplug/unplug leaks are still present in the common code (one in the KVM thread loop and another in cpu_address_space via cpu->cpu_ases) but these are already being handled by Mark Kanda an

[RFC PATCH v7 15/29] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)

Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76) Loongson-3A5000 and ls7a form a legacy model and extended model irq hierarchy.Tcg mode emulate a simplified extended model which has no Legacy I/O Interrupt Controller(LIOINTC) and LPC. e.g: |+-++-+ +---

[RFC PATCH v7 13/29] target/loongarch: Add gdb support.

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 2 + configs/targets/loongarch64-softmmu.mak | 1 + gdb-xml/loongarch-base64.xml| 44 +++ gdb-xml/loongarch-fpu64.xml | 57 ++ target/loongarch/cpu.c

[RFC PATCH v7 26/29] hw/loongarch: Add LoongArch smbios support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 1 + hw/loongarch/loongson3.c | 43 include/hw/loongarch/loongarch.h | 1 + 3 files changed, 45 insertions(+) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/K

[RFC PATCH v7 16/29] hw/loongarch: Add LoongArch ipi interrupt support(IPI)

This patch realize the IPI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- MAINTAINERS | 2 + hw/intc/Kconfig | 3 + hw/intc/loongarch_ipi.c | 164 hw/intc/meson.build |

[PATCH 2/2] hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

The timebase is allocated during spapr_realize_vcpu() and it's not freed. This results in memory leaks when doing vcpu unplugs: ==636935== ==636935== 144 (96 direct, 48 indirect) bytes in 1 blocks are definitely lost in loss record 6 ,461 of 8,135 ==636935==at 0x4897468: calloc (vg_replace_ma

[RFC PATCH v7 28/29] hw/loongarch: Add fdt support.

Add tree nodes for 3A5000 device tree. - cpu nodes; - fw_cfg nodes; - pcie nodes. The lastest loongarch bios have supported fdt. - https://github.com/loongson/edk2 - https://github.com/loongson/edk2-platforms Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c

[RFC PATCH v7 11/29] target/loongarch: Add LoongArch interrupt and exception handle

1.This patch Add loongarch interrupt and exception handle. 2.Rename the user excp to the exccode from the csr defintions. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- linux-user/loongarch64/cpu_loop.c | 8 +- target/loongarch/cpu.c| 260

[PATCH v2 1/1] target/riscv: misa to ISA string conversion fix

Some bits in RISC-V `misa' CSR should not be reflected in the ISA string. For instance, `S' and `U' (represents existence of supervisor and user mode, respectively) in `misa' CSR must not be copied since neither `S' nor `U' are valid single-letter extensions. This commit also removes all reserved

[RFC PATCH v7 25/29] hw/loongarch: Add -kernel and -initrd options support

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 81 include/hw/loongarch/loongarch.h | 5 ++ 2 files changed, 86 insertions(+) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 2795fcc895..9533057

[RFC PATCH v7 18/29] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 5 ++ hw/intc/loongarch_pch_msi.c | 75 + hw/intc/meson.build | 1 + hw/intc/trace-events

[PATCH 1/2] hw/ppc/ppc.c: add cpu_ppc_tb_free()

The timebase is created using cpu_ppc_tb_init(). At this moment we don't have a way to free it. Add cpu_ppc_tb_free() to allow env->tb_env to be freed. Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc.c | 7 +++ include/hw/ppc/ppc.h | 1 + 2 files changed, 8 insertions(+) diff

[RFC PATCH v7 22/29] hw/loongarch: Add some devices support for 3A5000.

1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-64. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 7 +

Re: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix

On 2022/03/28 8:29, Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: >> >> [This is the same patch as previous ones] > > Hello, > > Thanks for the patch! > >> >> (qemu-riscv only) > > This n

[RFC PATCH v7 19/29] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig| 3 + hw/intc/loongarch_extioi.c | 408 + hw/intc/meson.build| 1 + hw/intc/trace-events

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