On Fri, Mar 04, 2022 at 05:23:44PM +0100, Halil Pasic wrote:
> Unlike most virtio features ACCESS_PLATFORM is considered mandatory by
> QEMU, i.e. the driver must accept it if offered by the device. The
> virtio specification says that the driver SHOULD accept the
> ACCESS_PLATFORM feature if offer
On Fri, Mar 04, 2022 at 09:10:30PM +0530, Ani Sinha wrote:
> From: Liav Albani
>
> This can allow the guest OS to determine more easily if i8042 controller
> is present in the system or not, so it doesn't need to do probing of the
> controller, but just initialize it immediately, before enumerati
On Fri, Mar 04, 2022 at 10:13:13PM +, Peter Maydell wrote:
> On Fri, 4 Mar 2022 at 13:37, Michael S. Tsirkin wrote:
> >
> > The following changes since commit 6629bf78aac7e53f83fd0bcbdbe322e2302dfd1f:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/pull-target-arm-20220302'
On Sonntag, 6. März 2022 07:39:49 CET Akihiko Odaki wrote:
> MacOSX.sdk/System/Library/Frameworks/CoreAudio.framework/Headers/AudioHardwa
> re.h
> says:
> > The return value is currently unused and should always be 0.
Where does it say that, about which macOS functions? There are quite a bunch
of
On Thu, Feb 10, 2022 at 03:52:49PM +0100, Eric Auger wrote:
> Up to now the virt-machine node only contains a virtio-mmio
> driver node but no driver that eventually produces any pci-bus
> interface.
>
> Hence, PCI libqos tests cannot be run with aarch64 binary.
>
> This series brings the pieces
On Thu, Feb 10, 2022 at 03:52:54PM +0100, Eric Auger wrote:
> Up to now the virt-machine node contains a virtio-mmio node.
> However no driver produces any PCI interface node. Hence, PCI
> tests cannot be run with aarch64 binary.
>
> Add a GPEX driver node that produces a pci interface node. This
On 2022/03/06 19:49, Christian Schoenebeck wrote:
On Sonntag, 6. März 2022 07:39:49 CET Akihiko Odaki wrote:
MacOSX.sdk/System/Library/Frameworks/CoreAudio.framework/Headers/AudioHardwa
re.h
says:
The return value is currently unused and should always be 0.
Where does it say that, about which
Vitaly Kuznetsov writes:
> 'XMM fast hypercall input feature' is supported by KVM since v5.14,
> it allows for faster Hyper-V hypercall processing.
>
> 'Enlightened MSR-Bitmap' is a new nested specific enlightenment speeds up
> L2 vmexits by avoiding unnecessary updates to L2 MSR-Bitmap. KVM supp
On 7/2/22 08:54, Philippe Mathieu-Daudé wrote:
This is a re-org accel/ and softmmu/ to have more target-agnostic
objects.
Series fully reviewed. Paolo, Richard, do you want me to send a
pull request for this and the 'Remove "qemu/log.h"' series?
Since soft-freeze is soon, I'm going to send a p
The patch series was originally posted by Gustavo Noronha Silva,
and rebased to commit 2acf5e1d0e0f15be1b0ad85cf05b3a6e6307680c by
Akihiko Odaki.
This series adds two new options to the cocoa display:
- full-grab causes it to use a global tap to steal system combos
away from Mac OS X, so they
From: Gustavo Noronha Silva
On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change
swaps them around so that Alt is the key closer to the space bar and Meta/Super
is between Control and Alt, like on non-Mac keyboards.
It is a cocoa display option, disabled by default.
Ack
On 6/3/22 05:43, Richard Henderson wrote:
On 3/5/22 13:34, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Now than we can use the abstract CPUArchState, let's clean up.
Based-on:<20220214183144.27402-1-f4...@amsat.org>
target: Use ArchCPU & CPUArchState as abstract interface to tar
From: Gustavo Noronha Silva
Applications such as Gnome may use Alt-Tab and Super-Tab for different
purposes, some use Ctrl-arrows so we want to allow qemu to handle
everything when it captures the mouse/keyboard.
However, Mac OS handles some combos like Command-Tab and Ctrl-arrows
at an earlier
On 14/2/22 19:31, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (13):
meson: Display libfdt as disabled when system emulation is disabled
hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
hw/tricore: Remove unused and incorrect header
exec/cpu_ldst: Include 'cpu.h' to get target
On Fri, Mar 04, 2022 at 08:37:19PM +0530, Ani Sinha wrote:
> From: Liav Albani
>
> The FACP table is going to be changed for x86/q35 machines. To be sure
> the following changes are not breaking any QEMU test this change follows
> step 2 from the bios-tables-test.c guide on changes that affect AC
On Sun, 6 Mar 2022, Akihiko Odaki wrote:
From: Gustavo Noronha Silva
Applications such as Gnome may use Alt-Tab and Super-Tab for different
purposes, some use Ctrl-arrows so we want to allow qemu to handle
everything when it captures the mouse/keyboard.
However, Mac OS handles some combos like
On Sun, 6 Mar 2022, Akihiko Odaki wrote:
From: Gustavo Noronha Silva
On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change
swaps them around so that Alt is the key closer to the space bar and Meta/Super
is between Control and Alt, like on non-Mac keyboards.
It is a coco
On Sat, 5 Mar 2022 at 11:00, Cédric Le Goater wrote:
>
> The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
>
> Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request'
> into staging (2022-03-04 15:31:23 +)
>
> are available in the Git repository at
From: Gustavo Noronha Silva
On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change
swaps them around so that Alt is the key closer to the space bar and Meta/Super
is between Control and Alt, like on non-Mac keyboards.
It is a cocoa display option, disabled by default.
Ack
The patch series was originally posted by Gustavo Noronha Silva,
and rebased to commit 2acf5e1d0e0f15be1b0ad85cf05b3a6e6307680c by
Akihiko Odaki.
This series adds two new options to the cocoa display:
- full-grab causes it to use a global tap to steal system combos
away from Mac OS X, so they
From: Gustavo Noronha Silva
Applications such as Gnome may use Alt-Tab and Super-Tab for different
purposes, some use Ctrl-arrows so we want to allow qemu to handle
everything when it captures the mouse/keyboard.
However, Mac OS handles some combos like Command-Tab and Ctrl-arrows
at an earlier
On Sonntag, 6. März 2022 11:54:00 CET Akihiko Odaki wrote:
> On 2022/03/06 19:49, Christian Schoenebeck wrote:
> > On Sonntag, 6. März 2022 07:39:49 CET Akihiko Odaki wrote:
> >> MacOSX.sdk/System/Library/Frameworks/CoreAudio.framework/Headers/AudioHar
> >> dwa re.h
> >>
> >> says:
> >>> The retur
On Sun, Mar 6, 2022 at 9:16 PM Christian Schoenebeck
wrote:
>
> On Sonntag, 6. März 2022 11:54:00 CET Akihiko Odaki wrote:
> > On 2022/03/06 19:49, Christian Schoenebeck wrote:
> > > On Sonntag, 6. März 2022 07:39:49 CET Akihiko Odaki wrote:
> > >> MacOSX.sdk/System/Library/Frameworks/CoreAudio.fr
handle_voice_change() is a CoreAudio callback function as of CoreAudio type
AudioObjectPropertyListenerProc, and for the latter MacOSX.sdk/System/
Library/Frameworks/CoreAudio.framework/Headers/AudioHardware.h
says "The return value is currently unused and should always be 0.".
Signed-off-by: Akih
From: Philippe Mathieu-Daudé
target_ulong is target-specific, while vaddr isn't.
Remove the unnecessary "exec/cpu-defs.h" target-speficic header
from "memory_mapping.h" and use the target-agnostic "hw/core/cpu.h"
locally in memory_mapping.c.
Remove "exec/memory.h" since MemoryRegion is forward-
com/philmd/qemu.git tags/abstract-arch-cpu-20220306
for you to fetch changes up to 5bbf37aa89881751828d28e38608db0371874aef:
accel/tcg: Remove pointless CPUArchState casts (2022-03-06 13:15:42 +0100)
- Re-org accel/ and softmmu/ to
From: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-3-f4...@amsat.org>
---
accel/meson.build | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/accel/meson.
From: Philippe Mathieu-Daudé
cpu_memory_rw_debug() is declared in "exec/cpu-all.h" which
contains target-specific declarations. To be able to use it
from target agnostic source, move the declaration to the
generic "exec/cpu-common.h" header.
Replace the target-specific 'target_ulong' type by 'va
From: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-2-f4...@amsat.org>
---
accel/stubs/meson.build | 11 +++
1 file changed, 7 insertions(+), 4 deletion
From: Philippe Mathieu-Daudé
Mirror "sysemu/kvm.h" #ifdef'ry to define CONFIG_HAX_IS_POSSIBLE,
expose hax_allowed to hax_enabled() macro.
Suggested-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <2022020707542
From: Philippe Mathieu-Daudé
Move vaddr type declaration to the generic "exec/cpu-common.h" header.
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-4-f4...@amsat.org>
---
include/exec/cpu-common.h | 12
From: Philippe Mathieu-Daudé
Add cpu_thread_is_idle() to AccelOps, and implement it for the
KVM / WHPX accelerators.
Suggested-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-11-f4...@amsa
From: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-17-f4...@amsat.org>
---
accel/qtest/qtest.c| 1 -
target/alpha/translate.c | 1 -
tests/unit/ptimer-test-stubs.c | 1
From: Philippe Mathieu-Daudé
Add cpus_are_resettable() to AccelOps, and implement it for the
KVM accelerator.
Suggested-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-12-f4...@amsat.org>
From: Philippe Mathieu-Daudé
We want cpu_thread_is_idle() to use cpus_accel, so declare this
variable earlier.
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-10-f4...@amsat.org>
---
softmmu/cpus.c | 10 +--
From: Philippe Mathieu-Daudé
kvm_on_sigbus() and kvm_on_sigbus_vcpu() prototypes don't have
to be target specific. Remove this limitation to be able to build
softmmu/cpus.c once for all targets.
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Me
From: Philippe Mathieu-Daudé
cpu.c requires "exec/exec-all.h" to call tlb_flush() and
"qemu/accel.h" to call accel_cpu_realizefn().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-6-f4...@amsat.org>
---
cpu.c | 2 ++
1 file changed, 2 ins
From: Philippe Mathieu-Daudé
cpu_address_space_init() and cpu_reloading_memory_map() are
target-agnostic, but are declared in "exec/exec-all.h" which
contains target-specific declarations. Any target-agnostic
source including "exec/exec-all.h" becomes target-specific and
we have to compile it N t
From: Philippe Mathieu-Daudé
Now than we only build this stub with system emulation,
remove the user-mode #ifdef'ry.
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-8-f4...@amsat.org>
---
accel/stubs/kvm-stub.c
From: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-13-f4...@amsat.org>
---
softmmu/globals.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/softmmu/globals.c b/softmmu/globals.c
i
From: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-16-f4...@amsat.org>
---
softmmu/cpu-timers.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/softmmu/cpu-timers.c b/softmmu/cpu-tim
From: Philippe Mathieu-Daudé
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-15-f
From: Philippe Mathieu-Daudé
module_allow_arch() is the single target-specific call in the
whole vl.c file. Move the module initialization out to arch_init.c,
that way we'll be able to build vl.o once for all targets (the
next commit).
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
From: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-14-f4...@amsat.org>
---
softmmu/physmem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
ind
From: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220207075426.81934-18-f4...@amsat.org>
---
include/exec/exec-all.h | 1 -
accel/tcg/tcg-accel-ops-icount.c | 1 +
accel/tcg/tcg-accel-ops-mttcg.
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20220305233415.64627-2-philippe.mathieu.da...@gmail.com>
---
accel/tcg/cpu-exec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/
From: Philippe Mathieu-Daudé
When configuring QEMU with --disable-system, meson keeps showing
libfdt as "auto". Mark it as disabled instead.
Acked-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-2-f4...@amsat.org>
---
meson.build | 4 +++-
1 file chan
From: Philippe Mathieu-Daudé
gdb_exit() and gdb_set_stop_cpu() prototypes don't have to be
target specific. Remove this limitation to be able to build
softmmu/cpus.c and softmmu/runstate.c once for all targets.
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe M
From: Philippe Mathieu-Daudé
Various softmmu objects aren't target specific. Move them
to the generic softmmu source set.
For our 31 softmmu targets, this is in total 330 objects
less to build!
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Me
From: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-5-f4...@amsat.org>
---
include/exec/cpu_ldst.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index da987fe
From: Philippe Mathieu-Daudé
These target-specific files use the target-specific CPU state
but lack to include "cpu.h"; i.e.:
../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState'
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
^
From: Philippe Mathieu-Daudé
excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs()
and misc_helper.c for tlb_flush().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-8-f4...@amsat.org>
---
target/i386/tcg/sysemu/excp_help
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220211033034.21107-1-tsimp...@quicinc.com>
[PMD: Add missing "qom/object.h" include]
Signed-off-by: Philippe Mathieu-Daudé
---
From: Philippe Mathieu-Daudé
The CPU / CPU state are forward declared.
$ git grep -E 'struct [A-Za-z]+CPU\ \*'
target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU
*cpu);
target/openrisc/cpu.h:234:int (*cpu_openrisc_map_address_code)(struct
OpenRISCCPU *cpu,
From: Philippe Mathieu-Daudé
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <2022021418314
From: Philippe Mathieu-Daudé
HexagonCPU field parent_class is of type CPUClass, which
is declared in "hw/core/cpu.h".
Reviewed-by: Damien Hedde
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-11-f4...@amsat.org>
---
target/hexagon/cpu.h
From: Philippe Mathieu-Daudé
Replace the boilerplate code to declare CPU QOM types
and macros, and forward-declare the CPU instance type.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20220214183144.27402-14-f4...@amsat.org>
---
include/hw/core/cpu.h
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20220305233415.64627-3-philippe.mathieu.da...@gmail.com>
---
target/i386/hax/hax-all.c | 4 ++--
target/i386/nvmm/nvmm-all.c | 14 +++---
target/i386/whpx/whpx-all.c | 18 +
Qemu Linux Developers,
I’m looking for a solution to keep Hackintoshing a possibly for people like
me. I saw a group of people use your program and turned it into UTM a
problem using Qemu, but can emulate .ipsw restores of MacOS that include
the M1 Chip. The thing is UTM can only be run on a Mac O
On Sun, Mar 6, 2022 at 4:49 PM Michael S. Tsirkin wrote:
>
> On Fri, Mar 04, 2022 at 08:37:19PM +0530, Ani Sinha wrote:
> > From: Liav Albani
> >
> > The FACP table is going to be changed for x86/q35 machines. To be sure
> > the following changes are not breaking any QEMU test this change follows
On Sun, 6 Mar 2022, Akihiko Odaki wrote:
From: Gustavo Noronha Silva
Applications such as Gnome may use Alt-Tab and Super-Tab for different
purposes, some use Ctrl-arrows so we want to allow qemu to handle
everything when it captures the mouse/keyboard.
However, Mac OS handles some combos like
On Sun, Mar 6, 2022 at 4:06 PM Michael S. Tsirkin wrote:
>
> On Fri, Mar 04, 2022 at 09:10:30PM +0530, Ani Sinha wrote:
> > From: Liav Albani
> >
> > This can allow the guest OS to determine more easily if i8042 controller
> > is present in the system or not, so it doesn't need to do probing of t
On Sun, 6 Mar 2022, Akihiko Odaki wrote:
From: Gustavo Noronha Silva
On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change
swaps them around so that Alt is the key closer to the space bar and Meta/Super
is between Control and Alt, like on non-Mac keyboards.
It is a coco
Ideally I'd love it if we could start picking up the earlier
sections of this series as I think those have been reasonably
well reviewed and should not be particularly controversial.
(perhaps up to patch 15 inline with what Michael Tsirkin suggested
on v5).
There is one core memory handling relate
From: Ben Widawsky
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of
From: Ben Widawsky
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extende
From: Ben Widawsky
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically c
From: Jonathan Cameron
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
From: Ben Widawsky
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulate
From: Ben Widawsky
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignme
From: Ben Widawsky
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
command
From: Ben Widawsky
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the
From: Ben Widawsky
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit comm
From: Jonathan Cameron
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/core/machine.c
From: Ben Widawsky
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/cxl/cxl-mailbox-utils.c | 27 +++
From: Ben Widawsky
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to
From: Ben Widawsky
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v7:
* Code reord
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v7: Patch moved from 18 to 22 as we need LSA support in place to avoid
introducing backwards compatibility
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a no
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
---
tests/qtest/cxl-test.c | 23 +++
tests/qtest/meson.build | 4
2 files changed, 27 insertions(+)
di
From: Ben Widawsky
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 11 +++
1 f
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicat
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v7:
* Moved struct cxl_type3_dev to final location in earlier patch (17)
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cx
From: Ben Widawsky
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly
From: Jonathan Cameron
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable b
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v7:
* Move a va
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v7:
* Use QEMU_PACKED etc from compiler.h
From: Ben Widawsky
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield
Signed-of
From: Ben Widawsky
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
From: Ben Widawsky
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
--
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
Reviewed-by: Alex Bennée
---
v7:
* Host is_cxl assignment to
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
From: Jonathan Cameron
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 7 +++
include/hw/cxl/cxl_component.h | 2 ++
2
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci/pci
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/h
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| Bin 0 -> 184 bytes
tests/data/acpi/q35/DSDT.cxl| Bin 0 -> 9627 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 fi
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then directly access the hostmem->mr to fullfil the actual
operation.
From: Jonathan Cameron
Inorder to implement memory interleaving we need a means to proxy
the calls. Adding mem_ops allows such proxying.
Note should have no impact on use cases not using _dispatch_read/write.
For now, only file backed hostmem is considered to seek feedback on
the approach before
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