On Thu, Feb 17, 2022 at 1:49 AM Christoph Muellner wrote:
>
> The existing probe_access* functions do not allow to specify the
> access size and a non-faulting behavior at the same time.
>
> This is resolved by adding a generalization of probe_access_flags()
> that takes an additional size paramet
On Tue, Mar 01, 2022 at 07:37:06PM +0100, Jason A. Donenfeld wrote:
> Hi Michael,
>
> On Tue, Mar 1, 2022 at 6:17 PM Michael S. Tsirkin wrote:
> > Hmm okay, so it's a performance optimization... some batching then? Do
> > you really need to worry about every packet? Every 64 packets not
> > enoug
From: Wentao_Liang
A memory chunk is allocated with g_new0() and assigned to the variable
'storage'. However, if the branch takes true, there will be only an
error report but not a free operation for 'storage' before function
returns. As a result, a memory leak bug is triggered.
Use g_autofree t
Hi Markus, thanks for the review. Please let me know if this patch needs
to be rebased on top of current master or does it looks good to merge.
Thanks !
On 16/02/22 7:25 pm, Markus Armbruster wrote:
Rohit Kumar writes:
Qemu might crash when provided incomplete '-global' option.
For example:
On Tue, Mar 01, 2022 at 09:11:09PM +0200, Liav Albani wrote:
>
> On 3/1/22 13:19, Michael S. Tsirkin wrote:
> > On Tue, Mar 01, 2022 at 09:43:54AM +0100, Igor Mammedov wrote:
> > > On Mon, 28 Feb 2022 22:17:32 +0200
> > > Liav Albani wrote:
> > >
> > > > This can allow the guest OS to determine
On Tue, Mar 01, 2022 at 09:13:04PM +0200, Liav Albani wrote:
>
> On 3/1/22 13:21, Michael S. Tsirkin wrote:
> > On Tue, Mar 01, 2022 at 08:29:57AM +0530, Ani Sinha wrote:
> > >
> > > On Mon, 28 Feb 2022, Liav Albani wrote:
> > >
> > > > After changing the IAPC boot flags register to indicate sup
Support NVMe disk type, test PCI passthrough case:
~#virsh qemu-agent-command buster '{"execute":"guest-get-disks"}' | jq
...
{
"name": "/dev/nvme0n1",
"dependencies": [],
"partition": false,
"address": {
"serial": "SAMSUNG MZQL23T8HCLS-00A07_S64HNE0N500076",
Assigning a NVMe disk by VFIO or emulating a NVMe controller by QEMU,
a NVMe disk get exposed in guest side. Support NVMe disk bus type for
QAPI.
Signed-off-by: zhenwei pi
---
qga/qapi-schema.json | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/qga/qapi-schema.json b/qga/qa
- Introduce NVMe disk type
- Support NVMe disk type for posix
Zhenwei Pi (2):
qapi: Introduce NVMe disk bus type
qga/commands-posix: Support NVMe disk type
qga/commands-posix.c | 5 -
qga/qapi-schema.json | 3 ++-
2 files changed, 6 insertions(+), 2 deletions(-)
--
2.20.1
On 28/02/2022 22:25, Mark Cave-Ayland wrote:
The MacOS toolbox ROM accesses a number of addresses between 0x0 and 0x200
during
initialisation and resolution changes. Whilst the function of many of these
registers is unknown, it is worth the minimal cost of saving these extra values
as
part of
On 28/02/2022 23:10, Philippe Mathieu-Daudé wrote:
On 28/2/22 23:25, Mark Cave-Ayland wrote:
This prepares for the inclusion of the current PDMA callback in the migration
stream since the callback is referenced by an integer instead of a function
pointer.
Signed-off-by: Mark Cave-Ayland
---
zhenwei pi writes:
> Assigning a NVMe disk by VFIO or emulating a NVMe controller by QEMU,
> a NVMe disk get exposed in guest side. Support NVMe disk bus type for
> QAPI.
>
> Signed-off-by: zhenwei pi
> ---
> qga/qapi-schema.json | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> dif
Rohit Kumar writes:
> Hi Markus, thanks for the review. Please let me know if this patch
> needs to be rebased on top of current master or does it looks good to
> merge.
> Thanks !
Paolo, can you take care of this one?
On Tue, Mar 01, 2022 at 09:21:08AM -0500, Emanuele Giuseppe Esposito wrote:
> This serie tries to provide a proof of concept and a clear explanation
> on why we need to use drains (and more precisely subtree_drains)
> to replace the aiocontext lock, especially to protect BlockDriverState
> ->childr
Jonathan Cameron writes:
> From: Ben Widawsky
>
> This should introduce no change. Subsequent work will make use of this
> new class member.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 3 +++
> hw/mem/cxl_type3.c | 24 +++
Jonathan Cameron writes:
> From: Ben Widawsky
>
> Implement get and set handlers for the Label Storage Area
> used to hold data describing persistent memory configuration
> so that it can be ensured it is seen in the same configuration
> after reboot.
>
> Signed-off-by: Ben Widawsky
> Signed-
On Thu, Feb 24 2022, Yishai Hadas wrote:
> From: Jason Gunthorpe
>
> v1 was never implemented and is replaced by v2.
>
> The old uAPI documentation is removed from the header file.
>
> The old uAPI definitions are still kept in the header file to ease
> transition for userspace copying these hea
On Tue, Mar 1, 2022 at 6:22 PM Janosch Frank wrote:
>
> Offset calculations are easy enough to get wrong. Let's add a few
> variables to make moving around elf headers and data sections easier.
>
> Signed-off-by: Janosch Frank
Reviewed-by: Marc-André Lureau
> ---
> dump/dump.c | 34
Jonathan Cameron writes:
> From: Ben Widawsky
>
> CXL host bridges themselves may have MMIO. Since host bridges don't have
> a BAR they are treated as special for MMIO. This patch includes
> i386/pc support.
> Also hook up the device reset now that we have have the MMIO
> space in which the r
Hi
On Tue, Mar 1, 2022 at 6:22 PM Janosch Frank wrote:
>
> Just like with the other write functions let's move the 32/64 bit elf
> handling to a function to improve readability.
>
> Signed-off-by: Janosch Frank
> ---
> dump/dump.c | 24 +---
> 1 file changed, 17 insertions(+
On Tue, Mar 01, 2022 at 11:00:37PM +0100, Bernhard Beschow wrote:
> isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
> It can therefore be removed.
>
> Signed-off-by: Bernhard Beschow
> Reviewed-by: Stefan Berger (tpm_tis_isa)
> Acked-by: Corey Minyard (isa_ipmi_bt,
> isa
On Mon, 28 Feb 2022 at 18:11, Warner Losh wrote:
>
> The following changes since commit fa435db8ce1dff3b15e3f59a12f55f7b3a347b08:
>
> Merge remote-tracking branch
> 'remotes/jsnow-gitlab/tags/python-pull-request' into staging (2022-02-24
> 12:48:14 +)
>
> are available in the Git repositor
Am 1. März 2022 22:52:19 UTC schrieb Bernhard Beschow :
>The QOM API already provides getters for uint64 and uint32 values, so reuse
>them.
>
>Signed-off-by: Bernhard Beschow
>Reviewed-by: Alistair Francis
Meh, I accidently swapped Alistair's Reviewed-by into this patch while dropping
it from t
* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote:
> From: "Dr. David Alan Gilbert"
>
> Add the missing VMSTATE_END_OF_LIST to vmstate_muldiv
Queued
>
> Fixes: 99abcbc7600 ("clock: Provide builtin multiplier/divider")
> Signed-off-by: Dr. David Alan Gilbert
> ---
> hw/core/clock-vms
Assigning a NVMe disk by VFIO or emulating a NVMe controller by QEMU,
a NVMe disk get exposed in guest side. Support NVMe disk bus type and
implement posix version.
Test PCI passthrough case:
~#virsh qemu-agent-command buster '{"execute":"guest-get-disks"}' | jq
...
{
"name": "/dev/nvm
* Hanna Reitz (hre...@redhat.com) wrote:
> In virtiofsd, we assume that the presence of the STATX_MNT_ID macro
> implies existence of the statx.stx_mnt_id field. Unfortunately, that is
> not necessarily the case: glibc has introduced the macro in its commit
> 88a2cf6c4bab6e94a65e9c0db8813709372e91
From: "Lucas Mateus Castro (alqotel)"
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.
Reviewed-by: Richard Henderson
Si
01.03.2022 17:21, Emanuele Giuseppe Esposito wrote:
This serie tries to provide a proof of concept and a clear explanation
on why we need to use drains (and more precisely subtree_drains)
to replace the aiocontext lock, especially to protect BlockDriverState
->children and ->parent lists.
Just a
From: Daniel Henrique Barboza
There are still PMU exclusive bits to handle in fire_PMC_interrupt()
before implementing the EBB support. Let's finalize it now to avoid
dealing with PMU and EBB logic at the same time in the next patches.
fire_PMC_interrupt() will fire an Performance Monitor alert
The following changes since commit 09591fcf6eb3157ab9c50a9fbbef5f8a567fb49f:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220228' into
staging (2022-03-01 15:55:31 +)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-pp
From: Bernhard Beschow
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This
resolves one usage of ISADevice::isairq[] which allows it to be removed
eventually.
Signed-off-by: Bernhard Beschow
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2022
From: Daniel Henrique Barboza
This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing
meson.build accordingly will prevent problems --disable-tcg and
--disable-linux-user later on.
We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid
adding "defined(CONFIG_TCG
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vcmpsq: Vector Compare Signed Quadword
vcmpuq: Vector Compare Unsigned Quadword
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-14-matheus.fe...@eldorado.org.br>
Signed-off-b
From: Daniel Henrique Barboza
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monito
From: Daniel Henrique Barboza
This patch adds the EBB exception support that are triggered by
Performance Monitor alerts. This happens when a Performance Monitor
alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper
w
From: Luis Pires
New macros that add FLAGS and FLAGS2 checking were added for
both TRANS and TRANS64.
Reviewed-by: Richard Henderson
Signed-off-by: Luis Pires
[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
- Use the new macros in load/store vector insns ]
Signed-off-by: Matheus Ferst
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-17-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 32 +-
From: Daniel Henrique Barboza
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s")
changed phb4_pec code to create the default PHB4 objects in
pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was
removed and each PHB4 object is tied together with its PEC via th
From: Víctor Colombo
Based on [1] by Lijun Pan , which was never merged
into master.
[1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-7-matheus.
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-16-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 2 ++
target/ppc/translate/vmx-impl.c.inc | 40 +
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vcmpgtsq: Vector Compare Greater Than Signed Quadword
vcmpgtuq: Vector Compare Greater Than Unsigned Quadword
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-13-matheus.fe...
From: "Lucas Mateus Castro (alqotel)"
Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not
use helpers.
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-5-matheus.fe...@eldorado.org.br>
Signed-off-by: Céd
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-15-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 4
target/ppc/insn32.decode| 10 ++
target/
From: Lucas Coutinho
Reviewed-by: Richard Henderson
Signed-off-by: Lucas Coutinho
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-9-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.
From: Lucas Coutinho
Move the following instructions to decodetree:
vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign Halfword To Doubleword
vextsw2d: Vector Extend Sign Word To Doub
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-18-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 8
target/ppc/translate/vmx-impl.c.inc | 32 +++
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-10-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 30 --
target/ppc/insn32.decode| 24
tar
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-23-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 23 +-
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vcmpequq: Vector Compare Equal Quadword
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-12-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédr
From: Matheus Ferst
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-19-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 5 ++
target/ppc/translate/vmx-imp
From: "Lucas Mateus Castro (alqotel)"
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to
decodetree
Reviewed-by: Richard Henderson
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-4-matheus.fe...@eldorado.org.br>
Si
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-11-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 9 ++--
target/ppc/insn32.decode| 4 ++
target/ppc/int_
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-27-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 81 ++
On Tue, 1 Mar 2022 at 22:00, Richard Henderson
wrote:
>
> Changes for v4:
> * Add cpu property for lpa2.
> * Disable that property for -machine virt-6.2 and previous.
>
> Changes for v3:
> * Update emulation.rst.
> * Split out separate update to ID_AA64MMFR0.
> * Hack for avocado.
>
I'v
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-21-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 40 ++
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-25-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 8 +-
target/ppc/insn32.decode| 6 ++
target/ppc/int_
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-26-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 48 ++
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-22-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +-
From: Matheus Ferst
Following the implementation of tcg_gen_gvec_3i, add a four-vector and
immediate operand expansion method.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-34-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-24-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 5 +
target/ppc/translate/vmx-impl.c.inc | 13 +
tar
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-28-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 21 +
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-29-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 5 +--
target/ppc/insn32.decode| 5 +++
target/ppc/int_
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-35-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 1 +
target/ppc/insn64.decode| 8 +
target/ppc/int_he
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-20-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 17
target/ppc/translate/vmx-impl.c.inc | 41 +++
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-33-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 1 +
target/ppc/insn64.decode| 8
target/ppc/i
From: Víctor Colombo
Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and
prepare the helper to be used for quadword comparisons.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <202202252109
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-31-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 2 --
target/ppc/insn32.decode| 5
target/ppc/fpu_
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-32-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 4 ++
target/ppc/translate/vsx-impl.c.inc | 71 +
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-47-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode
From: Víctor Colombo
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-42-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 3 +++
target/ppc/insn32.decode
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-37-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 16 -
target/ppc/insn32.decode| 22
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-39-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 7 +
target/ppc/translate/vsx-impl.c.inc | 40 ++
From: Lucas Coutinho
Implement the following PowerISA v3.1 instuctions:
lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form
lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form
lxvrwx: Load VSX Vector Rightmost Word Indexed X-form
lxvrdx: Load VSX Vector Rightmost Doubleword Indexed X-form
From: Matheus Ferst
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220225210936.1749575-36-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 16 +
target/ppc/insn32.decode| 10
target/ppc/i
From: Víctor Colombo
Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for
xs{max,min}cqp implementation.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-45-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_h
The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on
XIVE (P9), and the CAM line can use a 7bits or 8bits thread id.
For now, we only use 7bits thread ids, same as P9, but because of the
change of the size of the VP space, the CAM matching routine is
different between P9 and P10. It
From: Víctor Colombo
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-43-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 6 +++---
target/ppc/insn32.decode
From: Víctor Colombo
xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
removes this instruction as it was not in the final version of v3.0.
Signed-off-by: Víctor Colombo
Acked-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Fer
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-30-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 6
target/ppc/insn64.decode| 24
t
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB
to be consistent with the other interrupt sources of the system.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 6 ++
hw/ppc/pnv_psi.c | 30 --
2
From: Leandro Lupori
Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode
tree.
Reviewed-by: Richard Henderson
Signed-off-by: Leandro Lupori
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-48-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
ta
Only the CAM line updates done by the hypervisor are specific to
POWER10. Instead of duplicating the TM ops table, we handle these
commands locally under the PowerNV XIVE2 model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 8
hw/intc/p
From: Víctor Colombo
Also, fixes these instructions not being capitalized.
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-44-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h
From: Matheus Ferst
Implement the following PowerISA v3.0 instuctions:
xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd]
xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round
to Odd]
xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision
When the Address-Based Interrupt Trigger mode is activated, the PHB
maps the interrupt source number into the interrupt command address.
The PHB directly triggers the IC ESB page of the interrupt number and
not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by:
The trigger message coming from a HW source contains a special bit
informing the XIVE interrupt controller that the PQ bits have been
checked at the source or not. Depending on the value, the IC can
perform the check and the state transition locally using its own PQ
state bits.
The following chang
The XIVE2 interrupt controller of the POWER10 processor as the same
logic as on POWER9 but its SW interface has been largely reworked. The
interrupt controller has a new register interface, different BARs,
extra VSDs. These will be described when we add the device model for
the baremetal machine.
On 22.02.22 16:55, Vladimir Sementsov-Ogievskiy wrote:
21.02.2022 20:08, Hanna Reitz wrote:
303 runs two test cases, one of which requires zstd support.
Unfortunately, given that this is not a unittest-style test, we cannot
easily skip that single case, and instead can only skip the whole test.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c| 5 +
hw/intc/xive2.c| 3 ++-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 296a2d94949
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This
Add GEN1 config even if we don't use it yet in the core framework.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 8
hw/intc/pnv_xive2.c| 13 +
hw/intc/xive2.c| 7 +++
3 files changed, 28 insertions(+)
di
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
Message-Id: <20220225210936.1749575-46-matheus.fe...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 3 +++
target/ppc/fpu_hel
Reviewed-by: David Gibson
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 10 ++
include/hw/ppc/pnv_homer.h | 3 ++
include/hw/ppc/pnv_xscom.h | 3 ++
hw/ppc/pnv.c | 20
hw/ppc/pnv_homer.c | 64 ++
5 fi
From: Daniel Henrique Barboza
And get rid of the 'out' label since it's now unused.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220228175004.8862-4-danielhb...@gmail.com>
[ clg: Fixed typo in commit log ]
Signed-off-by: Cédric Le Goater
---
hw/pp
From: Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220228175004.8862-14-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr_rtas.c | 25 -
1 file changed, 12 insertions(+), 13 dele
The thread interrupt management area (TIMA) is a set of pages mapped
in the Hypervisor and in the guest OS address space giving access to
the interrupt thread context registers for interrupt management, ACK,
EOI, CPPR, etc.
XIVE2 changes slightly the TIMA layout with extra bits for the new
feature
These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.
The
From: Daniel Henrique Barboza
Use g_autoptr() with GArray* and GString* pointers to avoid calling
g_free() and the need for the 'out' label.
'drc_name' can also be g_autofreed to avoid a g_free() call at the end
of the while() loop.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe
Our OCC model is very mininal and POWER10 can simply reuse the OCC
model we introduced for POWER9.
Reviewed-by: David Gibson
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_occ.h | 2 ++
include/hw/ppc/pnv_xscom.h | 3 +++
hw/ppc/pnv.c
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits
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