From: Weiwei Li
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU,
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Reviewed
Create a new socket for postcopy to be prepared to send postcopy requested
pages via this specific channel, so as to not get blocked by precopy pages.
A new thread is also created on dest qemu to receive data from this new channel
based on the ram_load_postcopy() routine.
The ram_load_postcopy(PO
From: Philipp Tomsich
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This com
From: Anup Patel
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alista
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
---
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c| 53 --
2 files changed, 54 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index d8b102fa0ad
Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM
guests. Keep the fallback heuristic for KVM hosts that pre-date this
CAP.
This is only proposed the KVM CAP has not yet been allocated. I will
ask to merge the new KVM cap when there are no objections on the QEMU
side.
not-yet
From: Philipp Tomsich
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220202005249.3566542-8-philipp.toms...@vrull.
From: Anup Patel
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-i
16.02.2022 02:24, Eric Blake wrote:
On Tue, Feb 15, 2022 at 09:23:36PM +0200, Nir Soffer wrote:
On Tue, Feb 15, 2022 at 7:22 PM Eric Blake wrote:
According to the NBD spec, a server advertising
NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
not see any cache inconsiste
Firstly, postcopy already preempts precopy due to the fact that we do
unqueue_page() first before looking into dirty bits.
However that's not enough, e.g., when there're host huge page enabled, when
sending a precopy huge page, a postcopy request needs to wait until the whole
huge page that is sen
From: Anup Patel
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank Chang
On Wed, Feb 16, 2022 at 12:13:31PM +0800, huang...@chinatelecom.cn wrote:
> From: Hyman Huang(黄勇)
>
> v15
> - rebase on master
> - drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate
> - drop the 'setup' field in dirtylimit_state and call dirtylimit_process
> directly, which
From: Anup Patel
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish r
On Wed, 16 Feb 2022 at 08:07, Cédric Le Goater wrote:
>
> On 2/16/22 09:03, Joel Stanley wrote:
> > It was scheduled for removal in 7.0.
> >
> > Signed-off-by: Joel Stanley
>
> Could you please send a v2 with an update of docs/about/deprecated.rst ?
Sure. Do we remove the machine from the list o
From: Anup Patel
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank
From: Anup Patel
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
From: Anup Patel
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Cha
On 2/16/22 09:09, Joel Stanley wrote:
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
v2: also remove from docs/about/deprecated.rst
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspee
To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU thread
needs similar handling on fault tolerance. When ram_load_postcopy() fails,
instead of stopping the thread it halts with a semaphore, preparing to be
kicked again when recovery is detected.
A mutex is introduced to make
On Fri, Feb 11, 2022 at 06:02:59PM +0100, Laurent Vivier wrote:
If call virtio_queue_set_host_notifier_mr fails, should free
host-notifier memory-region.
This problem can trigger a coredump with some vDPA drivers (mlx5,
but not with the vdpasim), if we unplug the virtio-net card from
the guest a
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interup
From: Anup Patel
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id: 20220204174700.534953-8-
From: Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual
Two tests are added: a normal postcopy preempt test, and a recovery test.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 39 ++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
From: Weiwei Li
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <20220204022658.18097-4
From: Anup Patel
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subseque
On Wed, Feb 16, 2022 at 4:23 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1]
> https://github.com/lowRISC/opentitan/bl
From: Anup Patel
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id: 20220204174700.534953-11-a...@brainf
The POWER9 DD2.0 PVR is incorrect. It doesn't cause problems because
the pvr check is masking it and matching against the base.
Correct it, add a PVR for DD2.1.
Signed-off-by: Nicholas Piggin
---
Since v1: new patch
target/ppc/cpu-models.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-
In the first generation of Arch LBR, the max support
Arch LBR depth is 32, both host and guest use the value
to set depth MSR. This can simplify the implementation
of patch given the side-effect of mismatch of host/guest
depth MSR: XRSTORS will reset all recording MSRs to 0s
if the saved depth mism
From: Anup Patel
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank
The Last Branch Recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors which records a running trace of the most
recent branches taken by the processor in the LBR stack. This option
indicates the LBR format to enable for guest perf.
The LBR feature is enabled if below cond
Qemu might crash when provided incomplete '-global' option.
For example:
qemu-system-x86_64 -global driver=isa-fdc
qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394:
string_input_visitor_new: Assertion `str' failed.
Aborted (core dumped)
Fixes: 3751d7c43f795b
From: Yu Li
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li
Reviewed-by: Alistair Francis
Message-Id: <9040401e-8f87-ef4a-d840-67
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
include/hw/
On Mon, 14 Feb 2022 10:30:18 +
Daniel P. Berrangé wrote:
> On Mon, Feb 14, 2022 at 09:21:07AM +0100, Igor Mammedov wrote:
> > On Mon, 14 Feb 2022 14:58:57 +0800
> > Yang Zhong wrote:
> >
> > > On Mon, Feb 07, 2022 at 09:37:52AM +0100, Igor Mammedov wrote:
> > > > On Sat, 5 Feb 2022 13:
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang
---
target/
The behaviour of the Address Translation Mode on Interrupt resource is
not consistently supported by all CPU versions or all KVM versions:
KVM-HV does not support mode 2, and does not support mode 3 on POWER7 or
early POWER9 processesors. KVM PR only supports mode 0. TCG supports all
modes (0, 2, 3
Commit 7319d83a (tcg: Combine dh_is_64bit and dh_is_signed to
dh_typecode) converted the tcg type system to a 3-bit field from two
separate 1-bit fields. This subtly lost the 'signed' information from
the types as it uses the dh_alias macro to reduce the types down to
basic machine types. However,
On 15.02.22 21:26, David Miller wrote:
> resolves: https://gitlab.com/qemu-project/qemu/-/issues/737
> implements:
> AND WITH COMPLEMENT (NCRK, NCGRK)
> NAND (NNRK, NNGRK)
> NOT EXCLUSIVE OR (NXRK, NXGRK)
> NOR (NORK, NOGRK)
> OR WITH COMPLEMENT(OCRK, O
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
---
v2: also remove from docs/about/deprecated.rst
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c| 53 --
3 files changed, 61 deletions(-)
On Wed, Feb 16, 2022 at 11:59 AM Alistair Francis wrote:
>
> On Tue, Feb 15, 2022 at 9:39 PM Peter Maydell
> wrote:
> >
> > On Sat, 12 Feb 2022 at 00:07, Alistair Francis
> > wrote:
> > >
> > > From: Alistair Francis
> > >
> > > The following changes since commit
> > > 0a301624c2f4ced3331ffd5
On 04/02/2022 11:07, Jon Doron wrote:
> SynIc can be enabled regardless of the SControl mechanisim which can
> register a GSI for a given SintRoute.
>
> This behaviour can achived by setting enabling SIMP and then the guest
> will poll on the message slot.
>
> Once there is another message pen
On Tue, Feb 15, 2022 at 08:34:23PM +0100, Eugenio Pérez wrote:
> This iova tree function allows it to look for a hole in allocated
> regions and return a totally new translation for a given translated
> address.
>
> It's usage is mainly to allow devices to access qemu address space,
> remapping gu
On Fri, Feb 11, 2022 at 05:13:09PM +0100, Laurent Vivier wrote:
vhost_vdpa_host_notifiers_init() initializes queue notifiers
for queues "dev->vq_index" to queue "dev->vq_index + dev->nvqs",
whereas vhost_vdpa_host_notifiers_uninit() uninitializes the
same notifiers for queue "0" to queue "dev->nv
On Wed, Feb 16, 2022 at 2:23 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1]
> https://github.com/lowRISC/opentitan/bl
This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.
Signed-off-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 2 ++
hw/misc/trace-events | 4
2 files changed, 6 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 08f856
Only a limited set of bits are used for decoding the Start and End
addresses of the mapping window of a flash device.
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 1 +
hw/ssi/aspeed_smc.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/include/hw/s
The Arch LBR record MSRs and control MSRs will be migrated
to destination guest if the vcpus were running with Arch
LBR active.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target/i386/machine.c
On 2/16/22 09:03, Joel Stanley wrote:
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Could you please send a v2 with an update of docs/about/deprecated.rst ?
With that,
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Yang Weijiang
---
targe
Hi,
Here is a set of extensions for the Aspeed machines, the most
important ones being the removal of a deprecated machine and a simple
model for the Secure Boot Controller, both from Joel.
Thanks,
C.
Cédric Le Goater (2):
aspeed/smc: Add an address mask on segment registers
aspeed/sdmc: A
Am 16.02.22 um 10:17 schrieb David Hildenbrand:
On 15.02.22 21:27, David Miller wrote:
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile
On Tue, Feb 15, 2022 at 07:37:40PM +, Joao Martins wrote:
> On 2/15/22 09:53, Gerd Hoffmann wrote:
> > What is missing:
> >
> > * Some way for the firmware to get a phys-bits value it can actually
> >use. One possible way would be to have a paravirtual bit somewhere
> >telling whenev
There're some new features, including Arch LBR, depending
on XSAVES/XRSTORS support, the new instructions will
save/restore data based on feature bits enabled in XCR0 | XSS.
This patch adds the basic support for related CPUID enumeration
and meanwhile changes the name from FEAT_XSAVE_COMP_{LO|HI} t
From: Joel Stanley
This helps quieten booting the current Rainier kernel.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 9789a489047b..0e5e5c31d59c 100
If we do, we should probably change the
default value for this cap based on cpu model in
default_caps_with_cpu().
We allegedly still support POWER7 KVM in Linux. I've never tested it
and I don't know how much it's used at all. Probably should keep it
working here if possible. I'll look into defa
Excerpts from Fabiano Rosas's message of February 16, 2022 5:20 am:
> Daniel Henrique Barboza writes:
>
>> On 2/15/22 15:33, Cédric Le Goater wrote:
>>> On 2/15/22 04:16, Nicholas Piggin wrote:
Here is the rollup of patches in much better shape since the RFC.
I include the 2 first ones
On Wed, Feb 16, 2022 at 02:27:49PM +0800, Peter Xu wrote:
> The new patch layout:
>
> Patch 1-3: Three leftover patches from patchset "[PATCH v3 0/8] migration:
> Postcopy cleanup on ram disgard" that I picked up here too.
>
> https://lore.kernel.org/qemu-devel/20211224065000.97572-1-pet...@red
On 04/02/2022 11:07, Jon Doron wrote:
> Add all required definitions for hyperv synthetic debugger interface.
>
> Signed-off-by: Jon Doron
> ---
> include/hw/hyperv/hyperv-proto.h | 52
> target/i386/kvm/hyperv-proto.h | 37 +++
> 2 files
On Mon, Feb 14, 2022 at 08:34:15PM +0100, Eugenio Pérez wrote:
Simplifying memory management.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Stefano Garzarella
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index
On 04/02/2022 11:07, Jon Doron wrote:
> SynDbg commands can come from two different flows:
> 1. Hypercalls, in this mode the data being sent is fully
>encapsulated network packets.
> 2. SynDbg specific MSRs, in this mode only the data that needs to be
>transfered is passed.
>
> Signed-o
Michael Roth writes:
> On Mon, Feb 14, 2022 at 03:14:37PM +0100, Markus Armbruster wrote:
>> Cc: the qemu-ga maintainer
>>
>> John Snow writes:
>>
>> > [Moving our discussion upstream, because it stopped being brief and
>> > simple.]
>
> Hi John, Markus,
>
>>
>> Motivation: qemu-ga doesn't d
On 15.02.22 23:19, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:57:26PM +0100, Hanna Reitz wrote:
Add a parameter to optionally open a QMP connection when creating a
QemuStorageDaemon instance.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/iotests.py | 29 -
I forget that I already sent it in other series: [PATCH v3 02/19]
block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return value
"[PATCH v3 02/19] block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return
value" is a bit better as it adds a comment. And has Hanna's r-b
15.02.2022 20:53, Vladi
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
> Signed-off-by: David Miller
> ---
> tests/tcg/s390x/Makefile.target | 2 +-
> tests/tcg/s390x/mie3-
Architectural LBR (Arch LBR) is the enhancement for previous
non-Architectural LBR (Legacy LBR). This feature is introduced
in Intel Architecture Instruction Set Extensions and Future
Features Programming Reference[0]. The advantages of Arch LBR
can be referred to in native patch series[1].
Since
From: Joel Stanley
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device: 0x
Define Arch LBR bit in XSS and save/restore structure
for XSAVE area size calculation.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 6 +-
target/i386/cpu.h | 23 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cp
From: Joel Stanley
Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-j...@jms.id.au/
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +
inc
On 15.02.22 23:22, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:57:27PM +0100, Hanna Reitz wrote:
Test the following scenario:
1. Some block node (null-co) attached to a user (here: NBD server) that
performs I/O and keeps the node in an I/O thread
2. Repeatedly run blockdev-add/blockdev-del
> +
> +static uint16_t handle_recv_msg(HvSynDbg *syndbg, uint64_t outgpa,
> +uint32_t count, bool is_raw, uint32_t
> options,
> +uint64_t timeout, uint32_t *retrieved_count)
> +{
> +uint16_t ret;
> +uint8_t data_buf[TARGET_P
On Wed, Feb 16, 2022 at 08:08:46AM +, Joel Stanley wrote:
> On Wed, 16 Feb 2022 at 08:07, Cédric Le Goater wrote:
> >
> > On 2/16/22 09:03, Joel Stanley wrote:
> > > It was scheduled for removal in 7.0.
> > >
> > > Signed-off-by: Joel Stanley
> >
> > Could you please send a v2 with an update
On 2/16/22 07:56, Alexander Kanavin wrote:
Lack of AVX/AVX2 support in the i386 TCG has been a significant gap
for a long while; I've started work to close this gap.
This is of course nowhere near complete, or even buildable, I'm
just requesting initial feedback from the qemu gurus - am I on
the
On 16.02.22 10:28, Christian Borntraeger wrote:
>
>
> Am 16.02.22 um 10:17 schrieb David Hildenbrand:
>> On 15.02.22 21:27, David Miller wrote:
>>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
>>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
>>> tests/tcg/s390x/mie3-sel.c: SELECT instruct
From: Joel Stanley
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Message-Id: <20220216080947.65955-1-j...@jms.id.au>
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c| 53 ---
On Wed, Feb 16, 2022 at 06:39:47PM +1030, Joel Stanley wrote:
> It was scheduled for removal in 7.0.
>
> Signed-off-by: Joel Stanley
> ---
> v2: also remove from docs/about/deprecated.rst
>
> docs/about/deprecated.rst | 7 -
> docs/system/arm/aspeed.rst | 1 -
> hw/arm/aspeed.c
> -Original Message-
> From: John Johnson
> Sent: 16 February 2022 02:10
> To: Thanos Makatos
> Cc: qemu-devel@nongnu.org
> Subject: Re: [RFC v4 08/21] vfio-user: define socket receive functions
>
>
>
> > On Feb 15, 2022, at 6:50 AM, Thanos Makatos
> wrote:
> >
> >>>
> >
> > On seco
On Tue, 15 Feb 2022 at 09:35, Paolo Bonzini wrote:
>
> The following changes since commit 2d88a3a595f1094e3ecc6cd2fd1e804634c84b0f:
>
> Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for-upstream' into
> staging (2022-02-14 19:54:00 +)
>
> are available in the Git repository at:
>
On Montag, 14. Februar 2022 21:33:37 CET Will Cohen wrote:
> Hello all,
>
> I'm seeing on the updated release schedule that we're now looking at March
> 8 for soft feature freeze (
> https://wiki.qemu.org/Planning/7.0#Release_Schedule). Is there anything
> additional that should be prepared for th
On Tue, Feb 15, 2022 at 10:53:58AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > I don't know what behavior should be if firmware tries to program
> > PCI64 hole beyond supported phys-bits.
>
> Well, you are basically f*cked.
>
> Unfortunately there is no reliable way to figure what phys-bits actual
On 16/02/2022 10.17, David Hildenbrand wrote:
On 15.02.22 21:27, David Miller wrote:
...
diff --git a/tests/tcg/s390x/Makefile.target
b/tests/tcg/s390x/Makefile.target
index 1a7238b4eb..16b9d45307 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -1,6 +1,6 @@
On 16.02.22 10:43, Thomas Huth wrote:
> On 16/02/2022 10.17, David Hildenbrand wrote:
>> On 15.02.22 21:27, David Miller wrote:
> ...
>>> diff --git a/tests/tcg/s390x/Makefile.target
>>> b/tests/tcg/s390x/Makefile.target
>>> index 1a7238b4eb..16b9d45307 100644
>>> --- a/tests/tcg/s390x/Makefile.tar
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
> Signed-off-by: David Miller
> ---
> tests/tcg/s390x/Makefile.target | 2 +-
> tests/tcg/s390x/mie3-
Reviewed-by: David Gibson
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fcc83a7701..bbc75afbc0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/pp
There are still PMU exclusive bits to handle in fire_PMC_interrupt()
before implementing the EBB support. Let's finalize it now to avoid
dealing with PMU and EBB logic at the same time in the next patches.
fire_PMC_interrupt() will fire an Performance Monitor alert depending on
MMCR0_PMAE. If we a
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
exception and External EBB
On Wed, 16 Feb 2022 at 10:24, Richard Henderson
wrote:
> > There's an enormous amount of legacy SSE instructions to adjust
> > for VEX-128 and VEX-256 flavours, so I would want to know that this
> > way would be acceptable.
> >
> > Signed-off-by: Alexander Kanavin
> > ---
>
> Have a look at updati
This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing
meson.build accordingly will prevent problems --disable-tcg and
--disable-linux-user later on.
Suggested-by: Fabiano Rosas
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c | 5 ++---
target/ppc/machine.c
This patch adds the EBB exception support that are triggered by
Performance Monitor alerts. This happens when a Performance Monitor
alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that
will check for MMCR0_EBE, BESCR_PME a
Hi,
This new version adds a new patch (patch 2) that fixes --disable-tcg
--disable-linux-user compilation.
The series was based on upstream master.
Changes from v12:
- patch 2 (new):
* make power8-pmu.c compile only with CONFIG_TCG available
- patch 4 (former 3):
* added Cedric's r-b
- v11 l
On Tue, Feb 15, 2022 at 05:24:14PM -0600, Eric Blake wrote:
> Oh. The QMP command (which is immediately visible through
> nbd-server-add/block-storage-add to qemu and qemu-storage-daemon)
> gains "multi-conn":"on", but you may be right that qemu-nbd would want
> a command line option (either that,
On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote:
GCC 10.1 introduced the -moutline-atomics option on Aarch64.
This options is enabled by default, and triggers a link failure:
Undefined symbols for architecture arm64:
"___aarch64_cas1_acq_rel", referenced from:
_qmp_migrate_re
On 2/16/22 02:16, Nicholas Piggin wrote:
Excerpts from Cédric Le Goater's message of February 16, 2022 4:21 am:
On 2/15/22 04:16, Nicholas Piggin wrote:
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is s
Alistair,
This PULL seems not to include the fixup (which you had intended to
squash into it) for the regression introduced (i.e. the condition
being inverted):
https://patchwork.kernel.org/project/qemu-devel/patch/20220203153946.2676353-1-philipp.toms...@vrull.eu/
Without that change this will
Add all required definitions for hyperv synthetic debugger interface.
Signed-off-by: Jon Doron
---
include/hw/hyperv/hyperv-proto.h | 52
target/i386/kvm/hyperv-proto.h | 37 +++
2 files changed, 89 insertions(+)
diff --git a/include/hw/hyp
Signed-off-by: Jon Doron
---
hw/hyperv/Kconfig | 5 +
hw/hyperv/meson.build | 1 +
hw/hyperv/syndbg.c| 402 ++
3 files changed, 408 insertions(+)
create mode 100644 hw/hyperv/syndbg.c
diff --git a/hw/hyperv/Kconfig b/hw/hyperv/Kconfig
index 3f
SynIc can be enabled regardless of the SControl mechanisim which can
register a GSI for a given SintRoute.
This behaviour can achived by setting enabling SIMP and then the guest
will poll on the message slot.
Once there is another message pending the host will set the message slot
with the pendin
This patchset adds support for the synthetic debugging device.
HyperV supports a special transport layer for the kernel debugger when
running in HyperV.
This patchset add supports for this device so you could have a setup
fast windows kernel debugging.
At this point of time, DHCP is not implmene
This should account for AFAIKS all comments, except maybe some
about naming.
Changes since v1:
- Per-CPU spapr nested state moved to SpaprCpuState from PowerPCCPU.
- address_space_map ops are used, small rearrangement to make any
given access region store-only or load-only.
- Some style, naming,
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