On Thu, Feb 10, 2022 at 4:10 PM Nick Hudson wrote:
>
> In section 7.4.3 of the 82574 datasheet it states that
>
> "In systems that do not support MSI-X, reading the ICR
> register clears it's bits..."
>
> Some OSes rely on this.
>
> Signed-off-by: Nick Hudson
> ---
> hw/net/e1000e_core.
On Jan 26 18:11, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> With four new properties:
> - sriov_v{i,q}_flexible,
> - sriov_max_v{i,q}_per_vf,
> one can configure the number of available flexible resources, as well as
> the limits. The primary and secondary controller capability structures
>
On Jan 26 18:11, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> The n->reg_size parameter unnecessarily splits the BAR0 size calculation
> in two phases; removed to simplify the code.
>
> With all the calculations done in one place, it seems the pow2ceil,
> applied originally to reg_size, is unn
LGTM
Reviewed-by: Cameron Esfahani mailto:di...@apple.com>>
Cameron
> On Feb 9, 2022, at 4:41 AM, Alexander Graf wrote:
>
> We are parsing the syndrome field for sysregs in multiple places across
> the hvf code, but repeat shift/mask operations with hard coded constants
> every time. This is a
On Thu, Feb 10, 2022 at 8:24 PM Anup Patel wrote:
>
> On Thu, Feb 10, 2022 at 1:58 PM Atish Patra wrote:
> >
> > On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis
> > wrote:
> > >
> > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis
> > > wrote:
> > > >
> > > > On Sat, Feb 5, 2022 at 3:47 AM
On Mon, 7 Feb 2022 17:01:27 +0530
Ani Sinha wrote:
> This is a minor cleanup. Using macro definitions makes the code more
> readable. It is at once clear which tables use which starting base addresses.
> It also makes it easy to calculate the gaps between the addresses and modify
> them if neede
Several changes in this patch:
- Add support for virtio crypto asymmetric handling, include:
create/close session
encrypt/decrypt/sign/verify guest data
- Modify crypto backend to compat sym&asym operation.
- Introduce akcipher class without any implementation.
Then QEMU can provide
Update header from linux, support akcipher service.
Signed-off-by: lei he
Signed-off-by: zhenwei pi
---
.../standard-headers/linux/virtio_crypto.h| 82 ++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/include/standard-headers/linux/virtio_crypto.h
b/include
From: Lei He
Implement RSA algorithm by nettle hogweed, and apply it for
virtio-crypto akcipher backend.
1, The self-test framework of crypto layer works fine in guest kernel
2, Test with Linux guest(with asym support), the following script
test(note that pkey_XXX is supported only in a newer ve
v1 -> v2:
- Update virtio_crypto.h from v2 version of related kernel patch.
v1:
- Support akcipher for virtio-crypto.
- Introduce akcipher class.
- Introduce ASN1 decoder into QEMU.
- Implement RSA backend by nettle/hogweed.
Lei He (1):
crypto: Introduce RSA algorithm
Zhenwei Pi (2):
virtio-
Am 09.02.2022 um 11:15 hat Thomas Huth geschrieben:
> Instead of failing the iotests if GNU sed is not available (or skipping
> them completely in the check-block.sh script), it would be better to
> simply skip the bash-based tests, so that the python-based tests could
> still be run. Thus add the
On 10/02/2022 18:35, Stefan Hajnoczi wrote:
> On Thu, Feb 10, 2022 at 05:26:52PM +0100, Emanuele Giuseppe Esposito wrote:
>>
>>
>> On 10/02/2022 16:40, Stefan Hajnoczi wrote:
>>> On Tue, Feb 08, 2022 at 09:34:55AM -0500, Emanuele Giuseppe Esposito wrote:
Categorize the fields in struct Job
Am 09.02.2022 um 11:15 hat Thomas Huth geschrieben:
> If multiple tests run in parallel, they must use unique file
> names for the test output.
>
> Suggested-by: Hanna Reitz
> Signed-off-by: Thomas Huth
> ---
> tests/qemu-iotests/testrunner.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletio
+Thomas
On 11/2/22 00:19, Richard Henderson wrote:
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
Move user-mode specific prototypes from "exec/exec-all.h"
to "user/cpu-target.h".
Signed-off-by: Philippe Mathieu-Daudé
---
Why a new cpu-target.h, and what is it supposed to mean? What else i
On Thu, 2022-02-03 at 14:19 +, Stefan Hajnoczi wrote:
> Yep, I didn't comment on this because I don't have a good suggestion.
>
> In terms of semantics I think we should have:
>
> 1. A global default value that all new AioContext take. The QEMU main
>loop's qemu_aio_context will use this
On 11/2/22 00:25, Richard Henderson wrote:
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-icount.c | 1 +
accel/tcg/tcg-accel-ops-mttcg.c | 1 +
accel/tcg/tcg-accel-ops-rr.c | 1 +
accel/tcg/tcg-accel-ops.c | 1
On 11/2/22 00:14, Richard Henderson wrote:
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
To reduce the inclusion of "hw/core/cpu.h", extract
MMUAccessType to its own "exec/cpu-tlb.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
Not keen on the name, unless you plan to put something els
11.02.2022 12:29, Kevin Wolf wrote:
Am 09.02.2022 um 11:15 hat Thomas Huth geschrieben:
If multiple tests run in parallel, they must use unique file
names for the test output.
Suggested-by: Hanna Reitz
Signed-off-by: Thomas Huth
---
tests/qemu-iotests/testrunner.py | 2 +-
1 file changed,
On 9/2/22 13:41, Alexander Graf wrote:
We are parsing the syndrome field for sysregs in multiple places across
the hvf code, but repeat shift/mask operations with hard coded constants
every time. This is an error prone approach and makes it harder to reason
about the correctness of these operatio
On 11/2/22 04:30, Taylor Simpson wrote:
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 58a0d3870b..e3efbb2303 100644
--- a/ta
On Thu, Feb 10, 2022 at 07:39:01PM +, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > I wonder if we're thinking of this at the wrong level though. Does
> > it actually need to be QEMU providing this info to the guest owner ?
> >
> > Guest owners aren't go
The arch_sf_recip_common function was calling float32_getexp which
adjusts for denorm, but the we actually need the raw exponent bits.
This function is called from 3 instructions
sfrecipa
sffixupn
sffixupd
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
From: Zongyuan Li
When building with clang version 13.0.0 (eg. Fedora 13.0.0-3.fc35),
two unused variables introduced by macro GATHER_FUNCTION and
SCATTER_FUNCTION will cause building process failure due to
[-Werror -Wunused-variable].
Signed-off-by: Zongyuan Li
Resolves: https://gitlab.com/qem
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to
c4 inside a packet with reads from predicate registers, the predicate
reads should get the old values.
Test case added to tests/tcg/hexagon/preg_alias.c
Co-authored-by: Michael Lambert
Signed-off-by: Taylor Simpson
Messag
Instead of checking for nan arguments, use float??_unordered_quiet
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-4-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/op_helper.c | 6 +
On Thu, 10 Feb 2022, Philippe Mathieu-Daudé wrote:
> On 10/2/22 14:28, Ani Sinha wrote:
> > When adding E820_RESERVED entries we also accidentally allocate dynamic
> > entries. This is incorrect. We should simply return early with the count of
> > the number of reserved entries added.
> >
> > fi
From: Michael Lambert
Versions V3 and earlier should treat the "K_const" and "length" values
as unsigned.
Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug
Signed-off-by: Michael Lambert
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-2-tsimp...@quicinc.c
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Message-Id: <20220211033034.21107-1-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.
Tests to confirm floating point instructions are properly
setting exception bits in USR
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-8-tsimp...@quicinc.com>
Acked-by: Richard Henderson
---
tests/tcg/hexagon/usr.c | 339
1 file changed,
Add a test that sets USR multiple times in a packet
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-9-tsimp...@quicinc.com>
Acked-by: Richard Henderson
---
tests/tcg/hexagon/overflow.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
dif
Two tests added to tests/tcg/hexagon/hvx_misc.c
v21.uw = vadd(v11.uw, v10.uw):sat
v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-3-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/macros.h | 4 +-
te
Hexagon has ~200 instructions that set the saturate bit in USR, these
were broken into groups of similar instructions and one instruction
from each group is tested with at least one input that does not
saturate and at least one input that does saturate.
Signed-off-by: Taylor Simpson
Message-Id: <
Fix typo that checked for 32 bit nan instead of 64 bit
Test case added in tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-11-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/op_helper.c | 2 +-
tests/tcg/hexagon/usr.c| 4
2
The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208'
into staging (2022-02-08 11:40:08 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-he
Replace consecutive inline asm blocks with a single one with proper
outputs/inputs/clobbers rather than making assumptions about register
values being carried between separate blocks.
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-10-tsimp...@quicinc.com>
Reviewed-by: Richard Hend
Am 03.02.2022 um 15:19 hat Stefan Hajnoczi geschrieben:
> On Thu, Feb 03, 2022 at 10:56:49AM +, Daniel P. Berrangé wrote:
> > On Thu, Feb 03, 2022 at 10:53:07AM +, Stefan Hajnoczi wrote:
> > > On Wed, Feb 02, 2022 at 06:52:34PM +0100, Nicolas Saenz Julienne wrote:
> > > > The thread pool re
ull-target-arm-20220208'
into staging (2022-02-08 11:40:08 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20220211
for you to fetch changes up to effdede7a4b04cacea14618010ccc7775bb19196:
target/hexagon: remove unused variable (2022-02-11
On Wed, 9 Feb 2022 at 22:12, Richard Henderson
wrote:
>
> On 2/9/22 22:22, Alex Bennée wrote:
> > linux-user wants to trap all signals in case they are related to the
> > guest. This however results in less than helpful core dumps when the
> > error is internal to QEMU. We can detect when an asser
On Thu, 10 Feb 2022 at 11:48, Philippe Mathieu-Daudé wrote:
>
> Hi Alex,
>
> On 10/2/22 12:30, Alex Bennée wrote:
> > The previous numbers were a guess at best and rather arbitrary without
> > taking into account anything that might be loaded. Instead of using
> > guesses based on the state of reg
Am 08.02.2022 um 16:36 hat Emanuele Giuseppe Esposito geschrieben:
> Using bdrv_do_drained_begin_quiesce() in bdrv_child_cb_drained_begin()
> is not a good idea: the callback might be called when running
> a drain in a coroutine, and bdrv_drained_begin_poll() does not
> handle that case, resulting
On Wed, 9 Feb 2022 at 23:12, Philippe Mathieu-Daudé via
wrote:
>
> common-user/ has been added in commit bbf15aaf7c
> ("common-user: Move safe-syscall.* from linux-user").
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> scripts/coverity-scan/COMPONENTS.md | 2 +-
> 1 file changed, 1 insertion(
John Snow writes:
> On Thu, Feb 10, 2022 at 10:56 AM Markus Armbruster wrote:
>>
>> John Snow writes:
>>
>> > Just cleaning up some cobwebs.
>> >
>> > Signed-off-by: John Snow
>> > ---
>> > scripts/qapi/commands.py | 2 +-
>> > scripts/qapi/events.py | 6 +++---
>> > scripts/qapi/types.py
Jonah Palmer writes:
> From: Laurent Vivier
>
> This new command lists all the instances of VirtIODevices with
> their canonical QOM path and name.
>
> [Jonah: @virtio_list duplicates information that already exists in
> the QOM composition tree. However, extracting necessary information
> fro
Jonah Palmer writes:
> From: Laurent Vivier
>
> These new commands show the internal status of a VirtIODevice's
> VirtQueue and a vhost device's vhost_virtqueue (if active).
>
> Signed-off-by: Jonah Palmer
QAPI schema
Acked-by: Markus Armbruster
Jonah Palmer writes:
> From: Laurent Vivier
>
> This new command shows the status of a VirtIODevice, including
> its corresponding vhost device's status (if active).
>
> Next patch will improve output by decoding feature bits, including
> vhost device's feature bits (backend, protocol, acked, an
This version is mainly a reorganization of v5 patch ordering to make for
more sensible stepwise review and merging. I took the opportunity to add
a few more tests and introduce an overview document.
Changes since v5: Thanks to Michael and Igor for comments.
- Reorganize series to make it more sens
Jonah Palmer writes:
> From: Laurent Vivier
>
> This new command shows the information of a VirtQueue element.
>
> [Note: Up until v10 of this patch series, virtio.json had many (15+)
> enums defined (e.g. decoded device features, statuses, etc.). In v10
> most of these enums were removed and
From: Jonathan Cameron
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
From: Ben Widawsky
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of
From: Ben Widawsky
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit comm
From: Ben Widawsky
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignme
From: Ben Widawsky
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/cxl/cxl-mailbox-utils.c | 27 +++
From: Ben Widawsky
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extende
From: Ben Widawsky
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulate
From: Ben Widawsky
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
command
From: Ben Widawsky
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 44
Jonah Palmer writes:
> From: Laurent Vivier
>
> These new commands show the internal status of a VirtIODevice's
> VirtQueue and a vhost device's vhost_virtqueue (if active).
>
> Signed-off-by: Jonah Palmer
QAPI schema
Acked-by: Markus Armbruster
From: Ben Widawsky
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 23 +++
tests/qtest/meson.build | 4
2 files changed, 27 insertions(+)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cx
From: Ben Widawsky
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 11 +++
1 f
From: Ben Widawsky
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically c
From: Jonathan Cameron
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/core/machine.c
From: Ben Widawsky
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a no
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
Jonah Palmer writes:
> From: Laurent Vivier
>
> This new command shows the information of a VirtQueue element.
>
> [Note: Up until v10 of this patch series, virtio.json had many (15+)
> enums defined (e.g. decoded device features, statuses, etc.). In v10
> most of these enums were removed and
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 69 +
From: Ben Widawsky
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 126 +
1 file changed, 126 insertions(+)
diff --git a/tests/qtest/cxl-
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
---
hw/arm/Kconfig | 1 +
hw/pci-host/gpex-acpi.c
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mai
From: Jonathan Cameron
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable b
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cxl_type3.c | 24 +---
include/hw/cxl/cxl_devic
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tab
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_port.c | 25
From: Ben Widawsky
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield
Signed-of
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicat
Am 08.02.2022 um 16:36 hat Emanuele Giuseppe Esposito geschrieben:
> Doing the opposite can make ->detach() (more precisely
> bdrv_unapply_subtree_drain() in bdrv_child_cb_detach) undo the subtree_drain
> just performed to protect the removal of the child from the graph,
> thus making the fully-ena
From: Jonathan Cameron
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/pci_expander_bridge.c | 7 +++
include/hw/cxl/cxl_component.h | 2 ++
2 files changed, 9 insertion
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/h
From: Ben Widawsky
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/acpi/Kconfig |
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
Signed-off-
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then directly access the hostmem->mr to fullfil the actual
operation.
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| 0
tests/data/acpi/q35/DSDT.cxl| 0
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
3 files
From: Ben Widawsky
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 49 +
tests/qtest/meson.build | 1 +
2 files changed, 41 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
From: Ben Widawsky
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tes
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which is relevant to either
user
From: Jonathan Cameron
Inorder to implement memory interleaving we need a means to proxy
the calls. Adding mem_ops allows such proxying.
Note should have no impact on use cases not using _dispatch_read/write.
For now, only file backed hostmem is considered to seek feedback on
the approach before
From: Ben Widawsky
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 31 +++
1 file changed, 31 insertions(+)
diff
On 11/2/22 12:56, Peter Maydell wrote:
On Wed, 9 Feb 2022 at 23:12, Philippe Mathieu-Daudé via
wrote:
common-user/ has been added in commit bbf15aaf7c
("common-user: Move safe-syscall.* from linux-user").
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| Bin 0 -> 184 bytes
tests/data/acpi/q35/DSDT.cxl| Bin 0 -> 9627 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 fi
Jonah Palmer writes:
> From: Laurent Vivier
>
> Display feature names instead of bitmaps for host, guest, and
> backend for VirtIODevices.
>
> Display status names instead of bitmaps for VirtIODevices.
>
> Display feature names instead of bitmaps for backend, protocol,
> acked, and features (hde
Am 08.02.2022 um 16:36 hat Emanuele Giuseppe Esposito geschrieben:
> Doing the opposite can make adding the child node to a non-drained node,
> as apply_subtree_drain is only done in ->attach() and thus make
> assert_bdrv_graph_writable fail.
>
> This can happen for example during a transaction ro
On Wed, 9 Feb 2022 at 14:03, Vladimir Sementsov-Ogievskiy
wrote:
>
> The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
> 11:40:08 +)
>
> are available in
On Fri, 11 Feb 2022 at 12:38, Philippe Mathieu-Daudé wrote:
>
> On 11/2/22 12:56, Peter Maydell wrote:
> > On Wed, 9 Feb 2022 at 23:12, Philippe Mathieu-Daudé via
> > wrote:
> >>
> >> common-user/ has been added in commit bbf15aaf7c
> >> ("common-user: Move safe-syscall.* from linux-user").
> >>
> -Original Message-
> From: Qemu-devel bounces+thanos.makatos=nutanix@nongnu.org> On Behalf Of John
> Johnson
> Sent: 12 January 2022 00:44
> To: qemu-devel@nongnu.org
> Subject: [RFC v4 20/21] vfio-user: migration support
>
> Signed-off-by: John G Johnson
> Signed-off-by: Elena U
11.02.2022 15:52, Peter Maydell wrote:
On Wed, 9 Feb 2022 at 14:03, Vladimir Sementsov-Ogievskiy
wrote:
The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
11:4
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