This commit adds emulation of the magnetometer on the LSM303DLHC.
It allows the magnetometer's X, Y and Z outputs to be set via the
mag-x, mag-y and mag-z properties, as well as the 12-bit
temperature output via the temperature property. Sensor can be
enabled with 'CONFIG_LSM303DLHC_MAG=y'.
Signed
On Fri, 28 Jan 2022 at 18:31, Juan Quintela wrote:
>
> The following changes since commit b367db48126d4ee14579af6cf5cdbffeb9496627:
>
> Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into
> staging (2022-01-28 11:05:29 +)
>
> are available in the Git repository at:
>
On Thu, Jan 27, 2022 at 2:10 PM Peter Maydell
wrote:
> On Fri, 2 Nov 2018 at 17:24, Peter Maydell
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add a virtual Xilinx Versal board.
> >
> > This board is based on the Xilinx Versal SoC. The exact
> > details of what peripherals are attached to
From: "Edgar E. Iglesias"
Always call arm_load_kernel() regardless of kernel_filename being
set. This is needed because arm_load_kernel() sets up reset for
the CPUs.
Fixes: 6f16da53ff (hw/arm: versal: Add a virtual Xilinx Versal board)
Reported-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
This should be applied on top of Peter Maydell's
"arm: Fix handling of unrecognized functions in PSCI emulation"
patch series.
This fixes an issue reported by Peter Maydell. We should
always call arm_load_kernel() regardless of kernel_filename being
set. This is needed
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
v2:
Per Paolo's suggestion, move the help
On Thu, Jan 27, 2022 at 4:46 PM Peter Maydell
wrote:
> This series fixes our handling of PSCI calls where the function ID is
> not recognized. These are supposed to return an error value, but
> currently we instead emulate the SMC or HVC instruction to trap to the
> guest at EL3 or EL2. Particula
On Fri, 28 Jan 2022 at 23:04, Eric Blake wrote:
>
> The following changes since commit 7a1043cef91739ff4b59812d30f1ed2850d3d34e:
>
> Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream'
> into staging (2022-01-28 14:04:01 +)
>
> are available in the Git repository at:
>
>
The 602 was derived from the PowerPC 603, for the gaming market it
seems. It was hardly used and no firmware supporting the CPU could be
found. Drop support.
Cc: Fabiano Rosas
Cc: Víctor Colombo
Signed-off-by: Cédric Le Goater
---
v2: - Fixed PPC_602_SPEC compile issue (Victor)
- Dropped
On 1/27/22 21:11, Fabiano Rosas wrote:
Changes from v1:
- Restored the 'sc 1' support to avoid breaking the pegasos2 machine.
I tested this version in the G4 with the following OSes:
- Linux 5.15 (5.16 seems to be broken, even with master)
Have you tried pmac32 defconfig plus these configs
Cc'ing Alex/Darren.
On 29/1/22 14:34, Peter Maydell wrote:
Hi; the build-oss-fuzz gitlab CI job seems to intermittently
but quite commonly hit the 1 hour timeout mark and get killed.
Examples from the last couple of days:
https://gitlab.com/qemu-project/qemu/-/jobs/2030815488
https://gitlab.com
On 28/1/22 21:54, Eric Blake wrote:
On Wed, Jan 19, 2022 at 01:14:39PM +0100, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daude
From: Philippe Mathieu-Daudé
The doubled From: looks odd here. I'll double-check that git doesn't
mess up the actual commit once I apply the patch.
I p
+Alex
On 28/1/22 15:30, Paolo Bonzini wrote:
On 1/28/22 15:17, Peter Maydell wrote:
Hi; I've been looking into what is the right way to handle in Kconfig
an i2c device which is intended for the user to specify on the command
line with a -device option.
(It's the lsm303dlhc magnetometer, current
Cc'ing qemu-trivial@
On 22/1/22 01:31, Philippe Mathieu-Daudé wrote:
vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(),
"exec/memory.h" for address_space_read/write(),
"exec/address-spaces.h" for address_space_memory
and more importantly "cpu.h" for target_ulong.
vof.c doesn't need "ex
On 1/29/22 01:56, Philipp Tomsich wrote:
+struct RISCVCPUConfig cfg;
Coding style says use a typedef for the struct.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 1/29/22 01:56, Philipp Tomsich wrote:
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the av
On 1/29/22 01:56, Philipp Tomsich wrote:
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the s
On 1/29/22 01:56, Philipp Tomsich wrote:
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the
On 1/29/22 01:56, Philipp Tomsich wrote:
-if (!decode_insn16(ctx, opcode)) {
-gen_exception_illegal(ctx);
-}
+if (decode_insn16(ctx, opcode))
+return;
...
-if (!decode_insn32(ctx, opcode32)) {
-gen_exception
On 1/29/22 01:56, Philipp Tomsich wrote:
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented
athttps://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1
On 1/29/22 01:56, Philipp Tomsich wrote:
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich
---
Reviewed-by: Richard Henderson
r~
On 1/29/22 10:28, Warner Losh wrote:
+static int reset_signal_mask(target_ucontext_t *ucontext)
+{
+int i;
+sigset_t blocked;
+target_sigset_t target_set;
+TaskState *ts = (TaskState *)thread_cpu->opaque;
+
+for (i = 0; i < TARGET_NSIG_WORDS; i++)
+if (__get_user(targe
On 1/29/22 10:28, Warner Losh wrote:
+if (block_signals()) {
+return -TARGET_ERESTART;
+}
+
+k = &sigact_table[sig - 1];
+if (oact) {
+oact->_sa_handler = tswapal(k->_sa_handler);
+oact->sa_flags = tswap32(k->sa_flags);
+oact->sa_mask = k->sa_mask;
On 1/28/22 02:46, Peter Maydell wrote:
We want to allow the psci-conduit property to be set after realize,
because the parts of the code which are best placed to decide if it's
OK to enable QEMU's builtin PSCI emulation (the board code and the
arm_load_kernel() function are distant from the code
On Sun, Jan 30, 2022 at 2:19 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/29/22 10:28, Warner Losh wrote:
> > +if (block_signals()) {
> > +return -TARGET_ERESTART;
> > +}
> > +
> > +k = &sigact_table[sig - 1];
> > +if (oact) {
> > +oact->_sa_ha
On 1/28/22 02:46, Peter Maydell wrote:
The CPU object's start-powered-off property is currently only
settable before the CPU object is realized. For arm machines this is
awkward, because we would like to decide whether the CPU should be
powered-off based on how we are booting the guest code, whi
On 1/28/22 02:46, Peter Maydell wrote:
Currently we expect board code to set the psci-conduit property on
CPUs and ensure that secondary CPUs are created with the
start-powered-off property set to false, if the board wishes to use
QEMU's builtin PSCI emulation. This worked OK for the virt board
On 12/1/22 22:36, Bernhard Beschow wrote:
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 58 +++
hw/mips/gt64xxx_pci.c | 62
Hi Peter,
On Thu, Jan 27, 2022 at 4:46 PM Peter Maydell
wrote:
> Change the allwinner-h3 based board to use the new boot.c
> functionality to allow us to enable psci-conduit only if the guest is
> being booted in EL1 or EL2, so that if the user runs guest EL3
> firmware code our PSCI emulation
On 12/1/22 22:36, Bernhard Beschow wrote:
Passing own DeviceState rather than just the IRQs allows for resolving
global variables.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 6 +++---
hw/pci-host/sh_pci.c| 6 +++---
hw/pci-host/versatile.c | 6 +++---
hw/ppc/ppc440_p
On 12/1/22 22:36, Bernhard Beschow wrote:
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c| 22 +-
include/h
Hi David,
While I realize my response is quite late, I wanted to report this error I
found when running the acceptance
tests for the orangepi-pc machine using avocado:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado
--show=app,console run -t machine:orangepi-pc
tests/avocado/
On 14/1/22 14:36, Peter Maydell wrote:
On Wed, 12 Jan 2022 at 22:02, Bernhard Beschow wrote:
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c
From: "Edgar E. Iglesias"
This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.
I've only tested this on top of Peter's recent PSCI emulation fixes.
Cheers,
E
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP APU Control.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +
hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +
hw/misc/meson.build| 1 +
3 files c
From: "Edgar E. Iglesias"
Add unimplemented SERDES area.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
in
From: "Edgar E. Iglesias"
Connect the ZynqMP CRF - Clock Reset FPD device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16
2 files changed, 18 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/ar
From: "Edgar E. Iglesias"
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cp
From: "Edgar E. Iglesias"
Connect the ZynqMP APU Control device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c | 25 +++--
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/xlnx-zynqmp.
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-crf.h | 209 +++
hw/misc/xlnx-zynqmp-crf.c | 270 ++
hw/misc/meson
Hi Niek!
(+Mark FYI)
On 30/1/22 23:50, Niek Linnenbank wrote:
Hi David,
While I realize my response is quite late, I wanted to report this error
I found when running the acceptance
tests for the orangepi-pc machine using avocado:
Unfortunately I only run the full SD/MMC tests when I send a
On 31/1/22 00:12, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-crf.h | 209 +++
hw/misc/xlnx-zynqmp-crf.c | 27
On 31/1/22 00:12, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Add a model of the Xilinx ZynqMP APU Control.
Signed-off-by: Edgar E. Iglesias
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +
hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +
hw/misc/m
On 31/1/22 00:12, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Connect the ZynqMP CRF - Clock Reset FPD device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16
2 files changed, 18 insertions(+)
Reviewed
On 31/1/22 00:12, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Connect the ZynqMP APU Control device.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c | 25 +++--
2 files changed, 26 insertions(+), 3 deleti
On 31/1/22 00:12, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Add unimplemented SERDES area.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Math
In adding our first X-extension (i.e., vendor-defined) on RISC-V with
XVentanaCondOps, we need to add a few instructure improvements to make
it easier to add similar vendor-defined extensions in the future:
- refactor access to the cfg->ext_* fields by making a pointer to the
cfg structure (as
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and th
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to cop
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a gua
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tom
Signed-off-by: Philipp Tomsich
Suggested-by: Richard Henderson
---
Changes in v4:
- use a typedef into 'RISCVCPUConfig' (instead of the explicit
'struct RISCVCPUConfig') to comply with the coding standard
(as suggested in Richard's review of v3)
Changes in v3:
- (new patch) refactor 'struc
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Signed-off-by: Philipp Toms
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- add a MAINTAINERS entry for XVentanaCondOps
MAINTAINERS | 7 +++
Hello dear experts.
I would like to try vhost-user-blk, may I know what is the guide for this?
For now I do not know how to build and run it, and how to start one vhost
target emulator?
https://github.com/qemu/qemu/tree/master/contrib/vhost-user-blk
On Wed, Jan 12, 2022 at 6:33 PM Igor Mammedov wrote:
>
> Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> fields in headers of ACPI tables. While it doesn't have impact on
> default values since QEMU uses 6 and 8 characters long values
> respectively, it broke usecase where IDs
On Sat, Jan 29, 2022 at 10:57 AM Atish Kumar Patra wrote:
>
>
>
> On Sun, Jan 23, 2022 at 11:59 PM Richard Henderson
> wrote:
>>
>> On 1/21/22 7:07 AM, Atish Patra wrote:
>> > Add the definition for ratified privileged specification version v1.12
>> >
>> > Signed-off-by: Atish Patra
>> > ---
>>
On 1/28/22 02:46, Peter Maydell wrote:
Change the iMX-SoC based boards to use the new boot.c functionality
to allow us to enable psci-conduit only if the guest is being booted
in EL1 or EL2, so that if the user runs guest EL3 firmware code our
PSCI emulation doesn't get in its way.
To do this we
On 1/28/22 02:46, Peter Maydell wrote:
Change the Xilinx ZynqMP-based board xlnx-zcu102 to use the new
boot.c functionality to allow us to enable psci-conduit only if
the guest is being booted in EL1 or EL2, so that if the user runs
guest EL3 firmware code our PSCI emulation doesn't get in its
wa
On 1/28/22 02:46, Peter Maydell wrote:
Instead of setting the CPU psci-conduit and start-powered-off
properties in the virt board code, set the arm_boot_info psci_conduit
field so that the boot.c code can do it.
This will fix a corner case where we were incorrectly enabling PSCI
emulation when b
On 1/28/22 02:46, Peter Maydell wrote:
Change the highbank/midway boards to use the new boot.c functionality
to allow us to enable psci-conduit only if the guest is being booted
in EL1 or EL2, so that if the user runs guest EL3 firmware code our
PSCI emulation doesn't get in its way.
To do this
On 1/28/22 02:46, Peter Maydell wrote:
Instead of setting the CPU psci-conduit and start-powered-off
properties in the xlnx-versal-virt board code, set the arm_boot_info
psci_conduit field so that the boot.c code can do it.
This will fix a corner case where we were incorrectly enabling PSCI
emul
On Tue, 25 Jan 2022 11:59:38 +0100
Philippe Mathieu-Daudé via wrote:
> I'm seeing the same issue with these domains since mid december:
>
> ...
> - rev.ng
>
> ...
> https://lore.kernel.org/qemu-devel/20220105185720.0d4fc159@orange/
> ...
I've tried to look into this and it looks like our set u
On Sat, 29 Jan 2022 13:33:59 +0100
Christian Schoenebeck wrote:
> On Freitag, 28. Januar 2022 12:49:58 CET Christian Schoenebeck wrote:
> > On Mittwoch, 26. Januar 2022 18:11:36 CET Greg Kurz wrote:
> > > The template pointer in virtio_9p_create_local_test_dir() is leaked.
> > > Add the g_autofre
On 1/28/22 02:46, Peter Maydell wrote:
Now that we have arranged for all the affected board models
to not enable the PSCI emulation if they are running guest code
at EL3, we can revert commit 4825eaae4fdd56fba0f, thus
reinstating commit 9fcd15b9193e819b, without bringing back the
regressions that
On 29/1/22 14:34, Peter Maydell wrote:
Hi; the build-oss-fuzz gitlab CI job seems to intermittently
but quite commonly hit the 1 hour timeout mark and get killed.
Examples from the last couple of days:
https://gitlab.com/qemu-project/qemu/-/jobs/2030815488
https://gitlab.com/qemu-project/qemu/-/
On 1/30/22 20:38, Philippe Mathieu-Daudé wrote:
Cc'ing qemu-trivial@
It is queued in ppc-7.0. I should send a PR today or tomorrow.
Thanks,
C.
On 22/1/22 01:31, Philippe Mathieu-Daudé wrote:
vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(),
"exec/memory.h" for address_space_read
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