Hi,
I'm trying to compile qemu 6.2.0 using musl-cross.
I am getting the following errors on make:
/output/aarch64-linux-musl/include/asm/sigcontext.h:83:8: error: redefinition
of 'struct esr_context'
/output/aarch64-linux-musl/include/asm/sigcontext.h:116:8: error: redefinition
of 'struct extr
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> >Signed-off-by: Philippe Mathieu-Da
On Sun, 23 Jan 2022 at 08:58, Adam Baxter wrote:
> I'm trying to compile qemu 6.2.0 using musl-cross.
>
> I am getting the following errors on make:
>
> /output/aarch64-linux-musl/include/asm/sigcontext.h:83:8: error: redefinition
> of 'struct esr_context'
> /output/aarch64-linux-musl/include/asm
When called with WNOHANG and no child has exited, waitid returns with
info.si_pid set to zero and thus check for info.si_pid != 0 will cause
target siginfo structure to be uninitialized. Fixed by removing the check.
Signed-off-by: Serge Belyshev
Resolves: https://gitlab.com/qemu-project/qemu/-/i
Alpha uses different values of some TARGET_RLIMIT_* constants, which were
missing and caused bugs like #577, fixed thus. Also rearranged all three
(alpha, mips and sparc) that differ from everyone else for clarity.
Signed-off-by: Serge Belyshev
Resolves: https://gitlab.com/qemu-project/qemu/-/is
Hi All,
I had a question about the CXL HDM Decoder register programming.
Is there any part of Qemu, that automatically programs the enable bit of the
HDM decoder register in the Component registers of the CXL endpoint?
The CDR (component registers) are hosted inside the memory of the CXL endpoint
On Samstag, 22. Januar 2022 13:57:31 CET Volker Rümelin wrote:
> Replace open-coded buffer arithmetic with the new function
> audio_ring_posb(). That's the position in backward direction
> of a given point at a given distance.
>
> Signed-off-by: Volker Rümelin
> ---
First of all, getting rid of
On Samstag, 22. Januar 2022 13:57:36 CET Volker Rümelin wrote:
> The next patch reduces the effective qemu playback buffer size
> by timer-period. Increase the number of jack audio buffers by
> one to preserve the total effective buffer size. The size of one
> jack audio buffer is 512 samples. With
On Thu, 13 Jan 2022 03:52:46 +0300
Viktor Prutyanov wrote:
> Perform read access to Windows dump header fields via helper macros.
> This is preparation for the next 32-bit guest Windows dump support.
>
> Signed-off-by: Viktor Prutyanov
> ---
> dump/win_dump.c | 100
> ++
All, I believe we will have a followup meeting this coming Tuesday 25th
January, at 15:00 (presumably using the same link:
https://redhat.bluejeans.com/5402697718).
We (GreenSocs/Xilinx) would like to quickly show what now ‘works’, and to give
an update on the patches.
Cheers
Mark.
> On 17
On 1/10/22 3:18 AM, Warner Losh wrote:
Move the EXCP_ATOMIC case to match linux-user/arm/cpu_loop.c:cpu_loop
ordering.
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/10/22 3:18 AM, Warner Losh wrote:
Start to implement the force_sig_fault code. This currently just calls
queue_signal(). The bsd-user fork version of that will handle this the
synchronous nature of this call. Add signal-common.h to hold signal
helper functions like force_sig_fault.
Signed-o
On 1/10/22 3:18 AM, Warner Losh wrote:
First attempt at implementing cpu_loop_exit_sigsegv, mostly copied from
linux-user version of this function.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/signal.c | 15 ---
1 file changed, 12 ins
On 1/10/22 3:18 AM, Warner Losh wrote:
First attempt at implementing cpu_loop_exit_sigbus, mostly copied from
linux-user version of this function.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/signal.c | 12 +---
1 file changed, 9 insertio
On 1/10/22 3:18 AM, Warner Losh wrote:
Implement EXCP_DEBUG and EXCP_BKPT the same, as is done in
linux-user. The prior adjustment of register 15 isn't needed, so remove
that. Remove a redunant comment (that code in FreeBSD never handled
break points).
Signed-off-by: Warner Losh
---
bsd-user/a
On 1/10/22 3:18 AM, Warner Losh wrote:
The code has moved in FreeBSD since the emulator was started, update the
comment to reflect that change. Remove now-redundant comment saying the
same thing (but incorrectly).
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_cpu.h | 2 +-
1 file ch
On 22/1/22 19:24, Peter Maydell wrote:
In an SMP system it can be unclear which CPU is taking an exception;
add the CPU index (which is the same value used in the TCG 'Trace
%d:' logging) to the "Taking exception" log line to clarify it.
Signed-off-by: Peter Maydell
---
target/arm/internals.h
On 22/1/22 19:24, Peter Maydell wrote:
The ITS currently has no tracepoints; add a minimal set
that allows basic monitoring of guest register accesses and
reading of commands from the command queue.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 11 +++
hw/intc/trace-even
On 22/1/22 19:24, Peter Maydell wrote:
The list of #defines for the ITS command packet numbers is neither
in alphabetical nor numeric order. Sort it into numeric order.
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
On 22/1/22 19:24, Peter Maydell wrote:
The MemoryRegionOps gicv3_its_translation_ops currently provides only
a .write_with_attrs function, because the only register in this
region is the write-only GITS_TRANSLATER. However, if you don't
provide a read function and the guest tries reading from th
On 1/14/22 4:19 AM, Peter Maydell wrote:
On Sun, 9 Jan 2022 at 16:27, Warner Losh wrote:
Use force_sig_fault to implement unknown opcode. This just uninlines
that function, so simplify things by using it. Fold in EXCP_NOCP and
EXCP_INVSTATE, as is done in linux-user.
Signed-off-by: Warner Los
Hi Cédric,
> and the default ppce500 machine has enough devices for the purpose ?
We cannot test much without a predictable timer emulation on QEMU, sometimes we
have fairly random freezes, but otherwise the basics work ok. I will let you
know in case we find something more or less reproducible
On Fri, Jan 21, 2022 at 3:50 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch removes the left-over/unused `ibex_plic.h` file. Previously
> used by opentitan, which now follows the RISC-V standard and uses the
> SiFivePlicState.
>
> Fixes: 434e7e021 ("hw/intc: Remove the Ibex P
On Thu, Jan 20, 2022 at 7:57 PM Petr Tesarik wrote:
>
> The documentation for the generic loader says that "the maximum size of
> the data is 8 bytes". However, attempts to set data-len=8 trigger the
> following assertion failure:
>
> ../hw/core/generic-loader.c:59: generic_loader_reset: Assertion
From: Alistair Francis
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
This fixes: https://gitlab.com/qemu-project/qemu/-/issues/594
Alistair Francis (2):
accel: tcg: Al
From: Alistair Francis
If the atomic operation fails we want to generate a MMU_DATA_STORE
access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for
the guest.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/tra
From: Alistair Francis
When performing atomic operations TCG will do a read operation then a
write operation. This results in a MMU_DATA_LOAD fault if the address is
invalid.
For some platforms (such as RISC-V) we should produce a store fault if
an atomic operation fails. This patch adds a new M
On 1/10/22 3:19 AM, Warner Losh wrote:
Update for the richer set of data faults that are now possible. Copied
largely from linux-user/arm/cpu_loop.c
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_cpu.h | 44 ++
1 file changed, 34 insertions(+), 10 dele
On 1/10/22 3:19 AM, Warner Losh wrote:
Initialize the signal state for the emulator. Setup a set of sane
default signal handlers, mirroring the host's signals. For fatal signals
(those that exit by default), establish our own set of signal
handlers. Stub out the actual signal handler we use for t
On 1/10/22 3:19 AM, Warner Losh wrote:
Implement host_signal_pc, host_signal_set_pc and host_signal_write for
i386.
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/host/i386/host-signal.h | 37
1 file changed, 37 insertions(+)
create mode 1
On 1/10/22 3:19 AM, Warner Losh wrote:
Implement host_signal_pc, host_signal_set_pc and host_signal_write for
x86_64.
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/host/x86_64/host-signal.h | 37 ++
1 file changed, 37 insertions(+)
create mode
On 1/10/22 3:19 AM, Warner Losh wrote:
Start to add the host signal functionality to the build.
Signed-off-by: Warner Losh
---
bsd-user/meson.build | 1 +
bsd-user/signal.c| 1 +
meson.build | 1 +
3 files changed, 3 insertions(+)
Reviewed-by: Richard Henderson
r~
On 1/10/22 3:19 AM, Warner Losh wrote:
Add the bsd-user specific events and infrastructure. Only include the
linux-user trace events for linux-user, not bsd-user.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/signal.c | 1 +
bsd-user/trace-ev
On 1/10/22 3:19 AM, Warner Losh wrote:
+static inline void host_to_target_siginfo_noswap(target_siginfo_t *tinfo,
+const siginfo_t *info)
+{
+int sig, code;
+
+sig = host_to_target_signal(info->si_signo);
You now have a target signo, so...
+if (SIGILL == sig || SIGFPE == s
On 1/10/22 3:19 AM, Warner Losh wrote:
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 2 ++
bsd-user/signal.c | 12
2 files changed, 14 insertions(+)
Reviewed-by: Richard Henderson
r~
On 1/10/22 3:19 AM, Warner Losh wrote:
print_taken_signal() prints signals when we're tracing signals.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 10 +
bsd-user/strace.c | 97 +++
2 fi
On 1/10/22 3:19 AM, Warner Losh wrote:
Returns 1 for signals that cause core files.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/signal.c | 17 +
1 file changed, 17 insertions(+)
Reviewed-by: Richard Henderson
r~
On Sat, Jan 22, 2022 at 11:22:37AM +0800, Hyman Huang wrote:
>
>
> 在 2022/1/17 10:19, Peter Xu 写道:
> > On Wed, Jan 05, 2022 at 01:14:06AM +0800, huang...@chinatelecom.cn wrote:
> > > From: Hyman Huang(黄勇)
> > >
> > > +
> > > +static void vcpu_dirty_stat_collect(VcpuStat *stat,
> > > +
On Sat, Jan 22, 2022 at 11:54:07AM +0800, Hyman Huang wrote:
>
> > > +static void *dirtylimit_thread(void *opaque)
> > > +{
> > > +CPUState *cpu;
> > > +
> > > +rcu_register_thread();
> > > +
> > > +while (!qatomic_read(&dirtylimit_quit)) {
> > > +sleep(DIRTYLIMIT_CALC_TIME_MS
Hi Peter
I realise this might be a bit offtopic for this mailing list, but might help
others searching for the same error message
> I think this must be a musl problem. Quoting the full error
> message:
Turns out this is actually related to the kernel (headers?) version - fixed in
4.20
https:/
在 2022/1/17 15:32, Peter Xu 写道:
On Wed, Jan 05, 2022 at 01:14:08AM +0800, huang...@chinatelecom.cn wrote:
##
+# @DirtyLimitInfo:
+#
+# Dirty page rate limit information of virtual CPU.
+#
+# @cpu-index: index of virtual CPU.
+#
+# @limit-rate: upper limit of dirty page rate for virtual CPU.
On Fri, Jan 21, 2022 at 09:27:23PM +0100, Eugenio Pérez wrote:
> +int iova_tree_alloc(IOVATree *tree, DMAMap *map, hwaddr iova_begin,
> +hwaddr iova_last)
> +{
> +const DMAMapInternal *last, *i;
> +
> +assert(iova_begin < iova_last);
> +
> +/*
> + * Find a valid
On 2022/1/24 上午8:59, Alistair Francis wrote:
From: Alistair Francis
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
Hi Alistair,
As Richard said, we can address thi
On 2022/1/24 上午8:59, Alistair Francis wrote:
From: Alistair Francis
If the atomic operation fails we want to generate a MMU_DATA_STORE
access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for
the guest.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594
Signed-off-by: A
From: Frank Chang
In SPI-mode, unlike SD-mode, card status bits: ILLEGAL_COMMAND and
COM_CRC_ERROR have type C ("cleared by read") clear conditions.
Also, type B ("cleared on valid command") clear condition is not
supported in SPI-mode. As the "In idle state" bit in SPI-mode has type A
("accordin
On Tue, Jan 18, 2022 at 10:35 AM wrote:
> From: Frank Chang
>
> In SPI-mode, type B ("cleared on valid command") clear condition is not
> supported, and as the "In idle state" bit in SPI-mode has type A
> ("according to current state") clear condition, the CURRENT_STATE bits
> in an SPI-mode res
On 1/10/2022 7:01 PM, Gerd Hoffmann wrote:
Regarding pflash itself, the read-only KVM memslot is required for it.
Otherwise pflash cannot work as a "ROMD device" (= you can't flip it
back and forth between ROM mode and programming (MMIO) mode).
We don't need Read-only mode for TDVF so far. If f
When building with clang version 13.0.0 (eg. Fedora 13.0.0-3.fc35),
two unused variables introduced by macro GATHER_FUNCTION and
SCATTER_FUNCTION will cause building process failure due to
[-Werror -Wunused-variable].
Signed-off-by: Zongyuan Li
Resolves: https://gitlab.com/qemu-project/qemu/-/iss
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, leading to the occurence of
"code should not be reached" in a few places.
This patch makes rv128 react as rv64 for gdb, as previously.
Signed-off-by: Frédéric Pétrot
---
target/riscv/g
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