10.01.2022 21:09, John Snow wrote:
On Mon, Jan 10, 2022 at 12:57 PM Stefan Weil mailto:s...@weilnetz.de>> wrote:
Am 10.01.22 um 18:08 schrieb John Snow:
On Fri, Jan 7, 2022 at 10:32 AM Stefan Weil mailto:s...@weilnetz.de>> wrote:
Signed-off-by: Stefan Weil mailto:s...@weilne
Hello Troy,
On 1/12/22 09:09, Troy Lee wrote:
Accumulative mode will supply a initial state and append padding bit at
the end of hash stream. However, the crypto library will padding those
bit automatically, so ripped it off from iov array.
The aspeed ast2600 acculumative mode is described in
On 17.01.22 05:12, Raphael Norwitz wrote:
> Today if multiple FDs are sent from the VMM to the backend in a
> VHOST_USER_REM_MEM_REG message, one FD will be unmapped and the remaining
> FDs will be leaked. Therefore if multiple FDs are sent we report an
> error and fail the operation, closing all F
On 17.01.22 05:12, Raphael Norwitz wrote:
> Today if multiple FDs are sent from the VMM to the backend in a
> VHOST_USER_ADD_MEM_REG message, one FD will be mapped and the remaining
> FDs will be leaked. Therefore if multiple FDs are sent we report an
> error and fail the operation, closing all FDs
On 15.01.22 21:37, Laurent Vivier wrote:
> From: Philippe Mathieu-Daudé
>
> dma_memory_set() does a DMA barrier, set the address space with
> a constant value. The constant value filling code is not specific
> to DMA and can be used for AddressSpace. Extract it as a new
> helper: address_space_se
On 17.01.22 05:12, Raphael Norwitz wrote:
> When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to
> libvhost-user, no guardrails were added to protect against QEMU
> attempting to hot-add too many RAM slots to a VM with a libvhost-user
> based backed attached.
>
> This change adds th
On 17.01.22 05:12, Raphael Norwitz wrote:
> Today if QEMU (or any other VMM) has sent multiple copies of the same
> region to a libvhost-user based backend and then attempts to remove the
> region, only one instance of the region will be removed, leaving stale
> copies of the region in dev->regions
在 2022/1/17 下午3:18, Guo Ren 写道:
On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li wrote:
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU,
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bits check for inner PTE
- add reserved bits
12.01.2022 13:50, Stefan Hajnoczi wrote:
On Tue, Jan 11, 2022 at 07:32:52PM -0500, John Snow wrote:
On Tue, Jan 11, 2022 at 6:53 PM John Snow wrote:
On Thu, Dec 23, 2021 at 6:08 AM Vladimir Sementsov-Ogievskiy
wrote:
Add possibility to generate trace points for each qmp command.
We should
10.01.2022 19:22, Stefan Hajnoczi wrote:
On Thu, Dec 23, 2021 at 12:07:54PM +0100, Vladimir Sementsov-Ogievskiy wrote:
Add possibility to generate trace points for each qmp command.
We should generate both trace points and trace-events file, for further
trace point code generation.
Signed-off-
-static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)
+static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
+ bool acc_mode)
{
struct iovec iov[ASPEED_HACE_MAX_SG];
g_autofree uint8_t *digest_buf;
@@ -103,6 +1
12.01.2022 03:38, John Snow wrote:
On Thu, Dec 23, 2021 at 6:08 AM Vladimir Sementsov-Ogievskiy
wrote:
Add and option to generate trace points. We should generate both trace
points and trace-events files for further trace point code generation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Rev
On Wed, Jan 12, 2022 at 05:04:57PM +0530, Viresh Kumar wrote:
> Hello,
>
> This patchset adds vhost-user-gpio device's support in Qemu. The support for
> the
> same has already been added to virtio specification and Linux Kernel.
>
> A Rust based backend is also in progress and is tested against
On Wed, Jan 05, 2022 at 01:14:05AM +0800, huang...@chinatelecom.cn wrote:
> From: Hyman Huang(黄勇)
>
> v11
> - rebase on master
> - add a commit " refactor dirty page rate calculation" so that dirty page
> rate limit
> can reuse the calculation logic.
> - handle the cpu hotplug/unplug case in
On Sun, Jan 16, 2022 at 10:05:58PM +0100, Philippe Mathieu-Daudé wrote:
> On 14/1/22 19:07, Michael S. Tsirkin wrote:
> > On Thu, Jan 13, 2022 at 04:55:11PM +, Daniel P. Berrangé wrote:
> > > Traditionally the OVMF firmware has been loaded using the pflash
> > > mechanism. This is because it is
On Sat, Jan 15, 2022 at 09:37:23PM +0100, Laurent Vivier wrote:
> From: Philippe Mathieu-Daudé
>
> dma_memory_set() does a DMA barrier, set the address space with
> a constant value. The constant value filling code is not specific
> to DMA and can be used for AddressSpace. Extract it as a new
> h
On Wed, Jan 05, 2022 at 01:14:08AM +0800, huang...@chinatelecom.cn wrote:
> +uint32_t kvm_dirty_ring_size(void)
> +{
> +return kvm_state->kvm_dirty_ring_size;
> +}
You may need to touch up stub too to fix build on non-x86:
=
diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-st
14.01.2022 18:55, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Fri, Jan 14, 2022 at 12:22:13PM +0100, Markus Armbruster wrote:
Nikita Lapshin writes:
If this capability is enabled migration stream
will have RAM section only.
Signed-off-by: Nikita Lapshin
[...]
diff --git a/
Commit c8f49e6b938e ("target/ppc: remove 401/403 CPUs") left a few
things behind.
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 1 -
target/ppc/cpu-models.c | 1 -
target/ppc/machine.c | 23 ---
target/ppc/misc_helper.c | 9 -
target/ppc/trans
The 7448 CPU is an evolution of the PowerPC 7447A and the last of the
G4 family. Change its family to reflect correctly its features. This
fixes Linux boot.
Cc: Fabiano Rosas
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.c | 8
1 file changed, 4 insertions(+), 4 deletions(-
Am 17.01.2022 um 09:45 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 12.01.2022 13:50, Stefan Hajnoczi wrote:
> > On Tue, Jan 11, 2022 at 07:32:52PM -0500, John Snow wrote:
> > > On Tue, Jan 11, 2022 at 6:53 PM John Snow wrote:
> > > >
> > > > On Thu, Dec 23, 2021 at 6:08 AM Vladimir Sementsov-
On 10/01/2022 11.33, Liviu Ionescu wrote:
I now have successful builds on all platforms, including on macOS 11 with Apple
Silicon and macOS 10.13 with Intel, but I had to disable Cocoa support, and
enable SDL support.
The resulting binaries (qemu-system-arm/aarch64/riscv32/riscv64) start, but
On 1/17/22 06:52, David Gibson wrote:
On Fri, Jan 14, 2022 at 08:07:21AM +0100, Cédric le Goater wrote:
On 1/14/22 00:41, David Gibson wrote:
On Thu, Jan 13, 2022 at 06:51:56PM +, Dr. David Alan Gilbert wrote:
Hi,
Is there any easy way of getting a machine where the pbr403 vmstate
woul
* Cédric Le Goater (c...@kaod.org) wrote:
> On 1/17/22 06:52, David Gibson wrote:
> > On Fri, Jan 14, 2022 at 08:07:21AM +0100, Cédric le Goater wrote:
> > > On 1/14/22 00:41, David Gibson wrote:
> > > > On Thu, Jan 13, 2022 at 06:51:56PM +, Dr. David Alan Gilbert wrote:
> > > > > Hi,
> > > > >
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 13 Jan 2022 at 19:45, Dr. David Alan Gilbert (git)
> wrote:
> >
> > From: "Dr. David Alan Gilbert"
> >
> > The pbr403 subsection is part of the tlb6xx state, so I believe it's
> > name needs to be:
> >
> > .name = "cpu/tlb6xx/pbr403"
Am 10.01.2022 um 16:55 hat Peter Maydell geschrieben:
> Just saw this failure of iotests in a netbsd VM (the in-tree
> tests/vm stuff). Pretty sure it's an intermittent as the
> pulreq being tested has nothing io or block related.
>
>
> TEST iotest-qcow2: 036
> TEST iotest-qcow2: 037
>
On 12/22/21 20:40, Vladimir Sementsov-Ogievskiy wrote:
Add a convenient function similar with bdrv_block_status() to get
status of dirty bitmap.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/dirty-bitmap.h | 2 ++
include/qemu/hbitmap.h | 11 +++
block/dirty-b
On 15/01/2022 23.21, Paolo Bonzini wrote:
"meson test" can be asked to run tests verbosely; this makes it usable
also for qemu-iotests's own harness, and it lets "make check-block"
reuse mtest2make.py's infrastructure to find and build test dependencies.
Adjust check-block.sh to use the standard
"Michael S. Tsirkin" writes:
> On Wed, Jan 12, 2022 at 05:04:57PM +0530, Viresh Kumar wrote:
>> Hello,
>>
>> This patchset adds vhost-user-gpio device's support in Qemu. The support for
>> the
>> same has already been added to virtio specification and Linux Kernel.
>>
>> A Rust based backend
Viresh Kumar writes:
> On 14-01-22, 14:06, Alex Bennée wrote:
>>
>> Viresh Kumar writes:
>>
>> > This creates the QEMU side of the vhost-user-gpio device which connects
>> > to the remote daemon. It is based of vhost-user-i2c code.
>> >
>> > Signed-off-by: Viresh Kumar
>>
>> > +++ b/includ
On Sun, 16 Jan 2022, Philippe Mathieu-Daudé wrote:
On 16/1/22 14:20, BALATON Zoltan wrote:
This also allows removing two forward declarations
Signed-off-by: BALATON Zoltan
---
hw/usb/hcd-ohci.c | 204 +++---
1 file changed, 100 insertions(+), 104 dele
Hi; I see intermittent hangs in the qtest migration-test on my
32-bit arm setup (which is a chroot on a 64-bit arm box). Here's
a backtrace:
Process tree:
migration-test(13212)-+-qemu-system-aar(24798)
|-qemu-system-aar(24813)
`-qemu-system-aar(25455)
==
On 1/14/22 19:07, Daniel Henrique Barboza wrote:
'stack->stack_no' represents the order that a stack appears in its PEC.
Its primary use is in XSCOM address space calculation in
pnv_phb4_xscom_realize() when calculating the memory region offset.
This attribute is redundant with phb->phb_id, whic
On 1/14/22 14:22, Markus Armbruster wrote:
Nikita Lapshin writes:
If this capability is enabled migration stream
will have RAM section only.
Signed-off-by: Nikita Lapshin
[...]
diff --git a/qapi/migration.json b/qapi/migration.json
index d53956852c..626fc59d14 100644
--- a/qapi/migration.
On Thu, Jan 13, 2022 at 04:15:10PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 15, 2021 at 09:25:13PM +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> > Th
On Sat, 15 Jan 2022 at 17:39, Mark Cave-Ayland
wrote:
>
> The following changes since commit 1cd2ad11d37c48f284f557954e1df675b126264c:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
> (2022-01-14 15:56:30 +)
>
> are available in the Git repository at:
>
>
On 1/14/22 19:07, Daniel Henrique Barboza wrote:
pnv_pec_default_phb_realize() stopped using it after the previous patch and
no one else is using it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/
On 1/14/22 19:07, Daniel Henrique Barboza wrote:
This patch changes the design of the PEC device to create and realize PHB4s
instead of PecStacks. After all the recent changes, PHB4s now contain all
the information needed for their proper functioning, not relying on PecStack
in any capacity.
All
> On 17 Jan 2022, at 11:41, Thomas Huth wrote:
>
> On 10/01/2022 11.33, Liviu Ionescu wrote:
>> I now have successful builds on all platforms, including on macOS 11 with
>> Apple Silicon and macOS 10.13 with Intel, but I had to disable Cocoa
>> support, and enable SDL support.
>> The resulti
Peter Maydell writes:
> Hi; I see intermittent hangs in the qtest migration-test on my
> 32-bit arm setup (which is a chroot on a 64-bit arm box). Here's
> a backtrace:
>
> Process tree:
> migration-test(13212)-+-qemu-system-aar(24798)
> |-qemu-system-aar(24813)
>
On Mon, 17 Jan 2022 at 11:21, Liviu Ionescu wrote:
> I did not check the implementation details, but if Cocoa is
> mandatory when building on macOS, why is it even allowed to
> choose SDL during configure?
Because (1) the macOS host support in QEMU is not very well
maintained, so the default is "
14.01.2022 20:47, Hanna Reitz wrote:
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
This brings "incremental" mode to copy-before-write filter: user can
specify bitmap so that filter will copy only "dirty" areas.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json
On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
We have one SGX-EPC address/size/node per memory backend,
make it child of the backend in the QOM composition tree.
Cc: Yang Zhong
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/sgx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
On 1/16/22 13:23, Bernhard Beschow wrote:
The functions are only used within their respective source files, so no
need for exporting.
Signed-off-by: Bernhard Beschow
---
hw/intc/i8259_common.c| 6 +++---
hw/intc/ioapic_common.c | 2 +-
include/hw/i386/ioapic_internal.h
On Mon, Jan 17, 2022 at 09:34:30AM +0200, Dov Murik wrote:
> [+cc Tom, Brijesh, Ashish - see SEV-related changes in this series]
>
>
> On 13/01/2022 18:55, Daniel P. Berrangé wrote:
> > The AMD SEV build of EDK2 only emits a single file, intended to be
> >
> > mapped readonly. There is explicitl
On 12/7/21 19:42, Daniel P. Berrangé wrote:
Now onto the values being reported. AFAICT from the kernel
docs, for all the types of data it currently reports
(cumulative, instant, peak, none), there is only ever going
to be a single value. I assume the ability to report multiple
values is future pr
The commit 04ceb61a40 ("virtio: Fail if iommu_platform is requested, but
unsupported") claims to fail the device hotplug when iommu_platform
is requested, but not supported by the (vhost) device. On the first
glance the condition for detecting that situation looks perfect, but
because a certain pec
On 1/17/22 12:48, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
>> We have one SGX-EPC address/size/node per memory backend,
>> make it child of the backend in the QOM composition tree.
>>
>> Cc: Yang Zhong
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/i386/
17.01.2022 13:06, Nikta Lapshin wrote:
On 12/22/21 20:40, Vladimir Sementsov-Ogievskiy wrote:
Add a convenient function similar with bdrv_block_status() to get
status of dirty bitmap.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/dirty-bitmap.h | 2 ++
include/qemu/hbitmap.
Hi Peter,
Could you take this patch via your ARM tree?
Thanks!
On Thu, Nov 18, 2021 at 4:05 PM Philippe Mathieu-Daudé wrote:
>
> On 10/17/21 09:48, Benjamin Herrenschmidt wrote:
> > The framebuffer driver fails to initialize with recent Raspberry Pi
> > kernels, such as the ones shipped in the
On 1/10/22 18:50, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> configs/devices/arm-softmmu/default.mak | 1 +
> include/hw/arm/rp2040.h | 32 ++
> hw/arm/rp2040.c | 79 +
> hw/arm/Kconfig
On 1/10/22 18:51, Alex Bennée wrote:
> Currently we are only targeting the official RaspberryPi Pico although
> I suspect most RP2040 based boards will look broadly the same.
>
> Signed-off-by: Alex Bennée
> ---
> configs/devices/arm-softmmu/default.mak | 1 +
> hw/arm/raspi_pico.c
On 1/10/22 18:51, Alex Bennée wrote:
> All the memory aside from the external flash is a feature of the SoC
> itself. However the flash is part of the board and different RP2040
> boards can choose to wire up different amounts of it.
>
> For now add unimplemented devices for all the rp2040 periphe
Hello,
These are the last little tweaks on PHB4 to prepare ground for PHB5.
Thanks,
C.
Cédric Le Goater (3):
ppc/pnv: Move root port allocation under pnv_pec_default_phb_realize()
ppc/pnv: Add a 'rp_model' class attribute for the PHB4 PEC
ppc/pnv: Remove PHB4 version property
include/h
and grab the PHB version from the PEC class directly when needed.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4.c | 9 +
hw/pci-host/pnv_phb4_pec.c | 3 ---
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index
The root port device is currently created and attached to the PHB
early in pnv_phb4_realize(). Do it under pnv_pec_default_phb_realize()
after the PHB is fully realized. It's cleaner and avoids an extra
test on defaults_enabled().
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4.c |
On 1/10/22 18:51, Alex Bennée wrote:
> We do mention the limitation of single parenthood for
> memory_region_add_subregion but lets also make it clear how aliases
> help solve that conundrum.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/memory.rst | 14 +-
> 1 file changed, 9 in
PHB5 will introduce its own root port model. Prepare ground for it.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 1 +
hw/pci-host/pnv_phb4_pec.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-ho
On 12/22/21 20:40, Vladimir Sementsov-Ogievskiy wrote:
Add function to wait for all intersecting requests.
To be used in the further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/reqlist.h | 8
block/reqlist.c | 8
2 files changed, 16 inser
From: Longpeng
Hi guys,
This patchset tries to support the generic vDPA device, the previous
disscussion can be found here [1].
With the generic vDPA device, QEMU won't need to touch the device
types any more, such like vfio.
We can use the generic vDPA device as follow:
-device vhost-vdpa-d
On 1/17/22 09:20, David Hildenbrand wrote:
> On 17.01.22 05:12, Raphael Norwitz wrote:
>> When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to
>> libvhost-user, no guardrails were added to protect against QEMU
>> attempting to hot-add too many RAM slots to a VM with a libvhost-user
>
From: Longpeng
Update linux headers to 5.xxx(kernel part is not merged yet)
To support generic vdpa deivce, we need add the following ioctls:
- VHOST_VDPA_GET_CONFIG_SIZE: get the configuration size.
- VHOST_VDPA_GET_VQS_NUM: get the count of supported virtqueues.
Signed-off-by: Longpeng
---
From: Longpeng
Add the infrastructure of vdpa-dev (the generic vDPA device), we
can add a generic vDPA device as follow:
-device vhost-vdpa-device-pci,vdpa-dev=/dev/vhost-vdpa-X
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5
hw/virtio/meson.build| 2 ++
hw/virti
From: Longpeng
Implements the .instance_init and the .class_init interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev-pci.c | 52 ++-
hw/virtio/vdpa-dev.c | 81 +++-
include/hw/virtio/vdpa-dev.h | 5 +++
3 files changed, 134
From: Longpeng
Implements the .unrealize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index bd28cf7a15..e5691d02bb 100644
--- a/hw/virtio/vdpa
On 1/17/22 1:34 AM, Dov Murik wrote:
> [+cc Tom, Brijesh, Ashish - see SEV-related changes in this series]
>
>
> On 13/01/2022 18:55, Daniel P. Berrangé wrote:
>> The AMD SEV build of EDK2 only emits a single file, intended to be
>>
>> mapped readonly. There is explicitly no separate writable VAR
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 99722c88a1..65511243f9 1006
On 1/17/22 13:51, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller. Pass the previously
> returned value (the QEMUSGList residual size, which was rarely used)
> as an op
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> Sent: Thursday, January 6, 2022 7:34 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: m...@redhat.com; jasow...@redhat.com; sgarz...@redhat.com;
> coh...@redhat.com; pbonz...@redhat.c
From: Longpeng
Implements the .get_config and .set_config interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index e5691d02bb..cef0a58012 100644
--- a/hw/vir
From: Longpeng
Implements the .get_features interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index cef0a58012..7bf07fef9b 100644
--- a/hw/virtio/vdpa-dev.c
+++ b/h
於 2021年12月29日 週三 上午10:35寫道：
> From: Frank Chang
>
> In RVV v1.0 spec, several Zve* vector extensions for embedded processors
> are defined in Chapter 18.2:
>
> https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
>
> This patchset implements Z
From: Longpeng
Implements the .realize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 101 +++
include/hw/virtio/vdpa-dev.h | 8 +++
2 files changed, 109 insertions(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index b1037
> On 17 Jan 2022, at 13:35, Peter Maydell wrote:
>
> ... the macOS host support in QEMU is not very well
> maintained, so the default is "it doesn't change"
BTW, my main development platform is macOS, both Intel and Apple Silicon, so if
someone is willing to improve macOS host support in QEM
From: Philippe Mathieu-Daudé
Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
Do not discard it, return it to the caller. Pass the previously
returned value (the QEMUSGList residual size, which was rarely used)
as an optional argument.
With this new API, SCSIRequest::residual m
From: Longpeng
Add helpers to get the "Transitional PCI Device ID" and "class_id"
of the device specified by the "Virtio Device ID".
These helpers will be used to build the generic vDPA device later.
Signed-off-by: Longpeng
---
hw/virtio/virtio-pci.c | 77 +
As I was still reading claims on the net that 9p was not usable for more
complex use cases, I decided to write a complete HOWTO for installing and
configuring an entire guest OS (with Debian 11 "Bullseye" as example) on top
of 9p being guest's root fs:
https://wiki.qemu.org/Documentation/9p_roo
> On 17 Jan 2022, at 13:35, Peter Maydell wrote:
>
> (2) the "use SDL" option seems to have worked for at least
> some people in the past:
SDL worked nicely for me too in the past, qemu-system-gnuarmeclipse was
configured with SDL for all platforms and it worked unchanged in the last 4-5
yea
From: Longpeng
Implements the .set_status interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 100 ++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 7bf07fef9b..99722c88a1 100644
From: Anup Patel
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
Cédric Le Goater writes:
> The 7448 CPU is an evolution of the PowerPC 7447A and the last of the
> G4 family. Change its family to reflect correctly its features. This
> fixes Linux boot.
>
> Cc: Fabiano Rosas
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
> ---
> target/ppc/c
From: Anup Patel
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.h| 14 +-
target/
Cédric Le Goater writes:
> Commit c8f49e6b938e ("target/ppc: remove 401/403 CPUs") left a few
> things behind.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
From: Anup Patel
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.h
The exception caused by an SVC instruction may be taken to AArch32
Hyp mode for two reasons:
* HCR.TGE indicates that exceptions from EL0 should trap to EL2
* we were already in Hyp mode
The entrypoint in the vector table to be used differs in these two
cases: for an exception routed to Hyp mode
From: Anup Patel
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank
From: Anup Patel
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu_bits.h | 127 +
From: Anup Patel
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interup
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
From: Anup Patel
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
docs/system/riscv/virt.rst | 16 +
From: Anup Patel
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
--
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level gue
From: Anup Patel
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_bits.h | 3 +++
From: Anup Patel
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish r
From: Anup Patel
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
targ
On Sun, Jan 09, 2022 at 06:17:34PM -0800, Patrick Venture wrote:
> On Fri, Jan 7, 2022 at 7:04 PM Patrick Venture wrote:
>
> > From: Hao Wu
> >
> > SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
> > interface that reports AMD SoC's Ttcl (normalized temperature),
> > and resemble
From: Anup Patel
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Cha
From: Anup Patel
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subseque
On Mon, 17 Jan 2022 at 12:52, Liviu Ionescu wrote:
>
> Then perhaps it is a misunderstanding from my part, if I try to start the
> vexpress-a9 machine using the line copied from Thomas' presentation, the
> console shows, it prints "Guest has not initialized the display yet" using
> the PC-like
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