> On 12 Jan 2022, at 15:56, Peter Maydell wrote:
>
> Those are UEFI firmware images which are suitable for using with
> the arm/aarch64 "virt" board.
Then it would probably be useful to keep them.
For the xPack QEMU Arm package, I ended up with the following script:
```
cd .../share/qe
From: Leonardo Garcia
While working on this file, also removed and unused reference in the end of the
file. The reference in the text was removed by commit 9f992cca93d (spapr:
update spapr hotplug documentation), but the link in the end of the document
was not removed then.
Signed-off-by: Leo
On Wed, Jan 12, 2022 at 08:03:31AM -0500, Igor Mammedov wrote:
> Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> fields in headers of ACPI tables. While it doesn't have impact on
> default values since QEMU uses 6 and 8 characters long values
> respectively, it broke usecase whe
From: Thomas Huth
The handling for the XFS_IOC_DIOINFO ioctl is currently quite excessive:
This is not a "real" feature like the other features that we provide with
the "--enable-xxx" and "--disable-xxx" switches for the configure script,
since this does not influence lots of code (it's only abou
+Emilio
On 1/12/22 14:46, Philippe Mathieu-Daudé wrote:
> Anyway, with your/Akihiko/Christian help during review, this flag
> is not necessary anymore to build softmmu/tools (I still have to
> figure how to silent the "#pragma FENV_ACCESS" warning in tests),
> so let forget about this patch (excep
On Mon, Jan 10, 2022 at 06:28:53PM -0500, John Snow wrote:
> We have a replacement for async QMP, but it doesn't have feature parity
> yet. For now, then, port the old tool onto the new backend.
>
> Signed-off-by: John Snow
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> ---
> python/qemu/aqmp/le
On Mon, Jan 10, 2022 at 06:29:09PM -0500, John Snow wrote:
> Now that we are fully switched over to the new QMP library, move it back
> over the old namespace. This is being done primarily so that we may
> upload this package simply as "qemu.qmp" without introducing confusion
> over whether or not
On Wed, Jan 12, 2022 at 3:58 AM Atish Patra wrote:
>
> On Sun, Jan 9, 2022 at 11:51 PM Bin Meng wrote:
> >
> > On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote:
> > >
> > > From: Atish Patra
> > >
> > > mcycle/minstret are actually WARL registers and can be written with any
> > > given value.
Le 18/12/2021 à 12:19, Philippe Mathieu-Daudé a écrit :
This code is easier to review using the load/store API.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Fixed offset in megasas_setup_inquiry (rth)
---
hw/scsi/megasas.c | 17 +++--
1 file chang
On Mon, Jan 10, 2022 at 10:38:59AM +0100, Philippe Mathieu-Daudé wrote:
> Cc'ing Richard & Eric for dubious compiler warning.
>
> On 1/9/22 21:57, Philipp Tomsich wrote:
> > Compiling with gcc version 11.2.0 (Ubuntu 11.2.0-13ubuntu1) results in
> > a (spurious) warning:
> >
> > In function ‘dum
Le 18/12/2021 à 03:28, Richard Henderson a écrit :
On 12/17/21 3:37 PM, Philippe Mathieu-Daudé wrote:
ping?
On 11/6/21 11:56, Philippe Mathieu-Daudé wrote:
Add the vmstate for the ETRAX timers.
This is in theory a migration compatibility break
for the 'AXIS devboard 88' CRIS machine.
Signed-o
Le 11/01/2022 à 18:55, Philippe Mathieu-Daudé a écrit :
Fix typo in 'make check-help' output.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 4c564cf7899
Hello,
On Wed, 12 Jan 2022, John Paul Adrian Glaubitz wrote:
Hi Zoltan!
On 10/26/21 00:40, BALATON Zoltan wrote:
On Tue, 26 Oct 2021, John Paul Adrian Glaubitz wrote:
Hi Zoltan!
On 10/23/21 15:22, BALATON Zoltan wrote:
You either need to strip the kernel with "strip vmlinux" or use the imag
The following changes since commit b37778b840f6dc6d1bbaf0e8e0641b3d48ad77c5:
linux-user: Fix clang warning for nios2-linux-user code (2022-01-12 09:22:01
+)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 9d30
On 1/12/22 15:09, Philippe Mathieu-Daudé wrote:
> +Emilio
>
> On 1/12/22 14:46, Philippe Mathieu-Daudé wrote:
>> Anyway, with your/Akihiko/Christian help during review, this flag
>> is not necessary anymore to build softmmu/tools (I still have to
>> figure how to silent the "#pragma FENV_ACCESS" w
On Wed, 2022-01-12 at 11:23 +0100, Cornelia Huck wrote:
> On Wed, Jan 05 2022, Eric Farman wrote:
>
> > On Wed, 2021-12-22 at 11:55 +0100, Cornelia Huck wrote:
> > > Split out some more specialized devices etc., so that we can
> > > build
> > > smarter lists of people to be put on cc: in the futu
Le 11/01/2022 à 18:26, Peter Maydell a écrit :
Fix a comment in qdev-core.h where we incorrectly referred
to TYPE_IRQ_SPLIT when we meant TYPE_SPLIT_IRQ.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/qde
On Tue, Jan 11, 2022 at 09:17:43PM +0100, Philippe Mathieu-Daudé wrote:
> On 1/11/22 20:43, Nir Soffer wrote:
> > NBDRequestData struct has unused QSIMPLEQ_ENTRY filed. It seems that
s/filed/field/
> > this field exists since the first git commit and was never used.
If my git sleuthing is right,
On Wed, 12 Jan 2022, Igor Mammedov wrote:
> Expected changes caused by previous commit:
>
> nvdimm ssdt (q35/pc/virt):
> - * OEM Table ID "NVDIMM "
> + * OEM Table ID "NVDIMM"
>
> SLIC test FADT (tests/data/acpi/q35/FACP.slic):
> -[010h 0016 8] Oem Table
On Wed, 12 Jan 2022, Michael S. Tsirkin wrote:
> On Wed, Jan 12, 2022 at 08:03:31AM -0500, Igor Mammedov wrote:
> > Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> > fields in headers of ACPI tables. While it doesn't have impact on
> > default values since QEMU uses 6 and 8
Alistair,
Do you (and the other RISC-V custodians of target/riscv) have any opinion
on this?
We can go either way — and it boils down to a style and process question.
Thanks,
Philipp.
On Mon, 10 Jan 2022 at 12:30, Philippe Mathieu-Daudé
wrote:
> On 1/10/22 12:11, Philipp Tomsich wrote:
> > On
On Wed, 12 Jan 2022, Igor Mammedov wrote:
> Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> fields in headers of ACPI tables. While it doesn't have impact on
> default values since QEMU uses 6 and 8 characters long values
> respectively, it broke usecase where IDs are provid
On Wed, 2021-11-03 at 16:30 -0400, Michael S. Tsirkin wrote:
> On Wed, Nov 03, 2021 at 02:48:41PM +, Xueming(Steven) Li wrote:
> > On Tue, 2021-11-02 at 02:49 -0400, Michael S. Tsirkin wrote:
> > > On Tue, Nov 02, 2021 at 06:08:39AM +, Xueming(Steven) Li wrote:
> > > > On Mon, 2021-11-01 at
>>
>> I mean, that would be fundamentally broken, because the fsync() would
>> corrupt the file. So I assume in a sane environment, the dst could only
>> have stale clean pagecache pages. And we'd have to get rid of these to
>> re-read everything from file.
>
> In case of write back cache mode, we
Hi,
On Wed, Dec 16, 2020 at 05:06:51PM -0500, Darrin M. Gorski wrote:
> This patch adds a 'modemctl' option to "-chardev socket" to enable control
> of the socket via the guest serial port.
> The default state of the option is disabled.
>
> 1. disconnect a connected socket when DTR transitions to
On Tue, 2021-11-02 at 02:47 -0400, Michael S. Tsirkin wrote:
> On Tue, Nov 02, 2021 at 06:00:58AM +, Xueming(Steven) Li wrote:
> > On Mon, 2021-11-01 at 17:00 -0400, Michael S. Tsirkin wrote:
> > > On Mon, Nov 01, 2021 at 04:38:13PM +0800, Xueming Li wrote:
> > > > When vhost-user device cleanu
Thank you David for replying!
> > From: Pankaj Gupta >
> >
> > Enable live migration support for virtio-pmem device.
> > Tested this: with live migration on same host.
> >
> > Need suggestion on below points to support virtio-pmem live migration
> > between two separate host systems:
>
> I assume
On 12.01.22 14:17, Ilya Leoshkevich wrote:
> SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
> cout_s64() relies on o->out being the shift result, however,
> wout_r1_D32() clobbers it.
>
> Fix by using a temporary.
>
> Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE
On Wed, Jan 12, 2022 at 08:46:16PM +0530, Ani Sinha wrote:
>
>
> On Wed, 12 Jan 2022, Michael S. Tsirkin wrote:
>
> > On Wed, Jan 12, 2022 at 08:03:31AM -0500, Igor Mammedov wrote:
> > > Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> > > fields in headers of ACPI tables. Whi
> >> I mean, that would be fundamentally broken, because the fsync() would
> >> corrupt the file. So I assume in a sane environment, the dst could only
> >> have stale clean pagecache pages. And we'd have to get rid of these to
> >> re-read everything from file.
> >
> > In case of write back cache
>> If the sign is false, the shifted bits (mask) have to be 0.
>> If the sign bit is true, the shifted bits (mask) have to be set.
>
> IIUC this logic handles sign bit + "shift - 1" bits. So if the last
> shifted bit is different, the overflow is not detected.
Ah, right, because of the - 1ULL ...
On Wed, Jan 12, 2022 at 04:23:30PM +0300, Vladislav Yaroshchuk wrote:
> ср, 12 янв. 2022 г. в 11:22, Roman Bolshakov :
>
> > On Wed, Jan 12, 2022 at 10:50:04AM +0300, Roman Bolshakov wrote:
> > > On Wed, Jan 12, 2022 at 12:14:15AM +0300, Vladislav Yaroshchuk wrote:
> > > > v9 -> v10
> > > > - Dis
On Wed, Jan 12, 2022 at 01:45:05PM +0100, Cédric Le Goater wrote:
> Hello Gregory,
>
> On 1/12/22 11:57, Graeme Gregory wrote:
> > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
> > > This series of patch introduce a dummy implemenation of aspeed i3c
> > > model, and it provide just eno
> static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
> {
> if (dest == s->pc_tmp) {
> @@ -4113,9 +4099,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps
> *o)
>
> static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
> {
> +TCGv_i64 t;
> uint6
On Sat, 18 Dec 2021 at 02:28, Richard Henderson
wrote:
> What I don't understand is how these controls get applied to qemu_irq after
> vmload, here
> or in any other device. It seems like we should have some post_load hook
> that calls
> timer_update_irq, etc.
Very late answer, but: we don't n
On Tue, 11 Jan 2022 at 19:55, Laurent Vivier wrote:
>
> The following changes since commit 64c01c7da449bcafc614b27ecf1325bb08031c84:
>
> Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into
> staging (2022-01-11 11:39:31 +)
>
> are available in the Git repository at:
>
>
On 12.01.22 17:08, Pankaj Gupta wrote:
I mean, that would be fundamentally broken, because the fsync() would
corrupt the file. So I assume in a sane environment, the dst could only
have stale clean pagecache pages. And we'd have to get rid of these to
re-read everything from fil
After the recent restructuring, I'd like to volunteer to help
in some of the s390 I/O areas.
Built on "[PATCH RFC v2] MAINTAINERS: split out s390x sections"
Signed-off-by: Eric Farman
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d37b0ee
On Wed, 2022-01-12 at 16:45 +0100, David Hildenbrand wrote:
> > > If the sign is false, the shifted bits (mask) have to be 0.
> > > If the sign bit is true, the shifted bits (mask) have to be set.
> >
> > IIUC this logic handles sign bit + "shift - 1" bits. So if the last
> > shifted bit is differ
Anup Patel 於 2021年12月30日 週四 下午8:51寫道：
> From: Anup Patel
>
> The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> which allow indirect access to interrupt priority arrays and per-HART
> IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
>
> Signed-off-by: Anup P
> I mean, that would be fundamentally broken, because the fsync() would
> corrupt the file. So I assume in a sane environment, the dst could only
> have stale clean pagecache pages. And we'd have to get rid of these to
> re-read everything from file.
> >>>
> >>> In case of write
Anup Patel 於 2021年12月30日 週四 下午8:59寫道：
> From: Anup Patel
>
> We should use the AIA INTC compatible string in the CPU INTC
> DT nodes when the CPUs support AIA feature. This will allow
> Linux INTC driver to use AIA local interrupt CSRs.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> > I mean, that would be fundamentally broken, because the fsync() would
> > corrupt the file. So I assume in a sane environment, the dst could only
> > have stale clean pagecache pages. And we'd have to get rid of these to
> > re-read everything from file.
> > >>>
> > >>> In c
An overflow occurs for SLAG when at least one shifted bit is not equal
to sign bit. Therefore, we need to check that `shift + 1` bits are
neither all 0s nor all 1s. The current code checks only `shift` bits,
missing some overflows.
Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE")
SLDA operates on 64-bit values, so its sign bit index should be 63,
not 31.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Reported-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 2 +-
1 file changed, 1 inser
Add a test for each shift instruction in order to to prevent
regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/shift.c | 270
2 files changed, 271 insertions(+)
create mode 100644 tests/tcg/s390x/sh
SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
cout_s64() relies on o->out being the shift result, however,
wout_r1_D32() clobbers it.
Fix by using a temporary.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg
v3: https://lists.nongnu.org/archive/html/qemu-devel/2022-01/msg02680.html
v3 -> v4: Simplify cc_calc_sla().
Free temporaries.
v2: https://lists.nongnu.org/archive/html/qemu-devel/2022-01/msg02488.html
v2 -> v3: Unify CC_OP_SLA_32 and CC_OP_SLA_64.
Add underscores to test macro
On Wed, Jan 12, 2022 at 03:21:44PM +0300, Vladislav Yaroshchuk wrote:
> vmnet.framework dependency is added with 'vmnet' option
> to enable or disable it. Default value is 'auto'.
>
> vmnet features to be used are available since macOS 11.0,
> corresponding probe is created into meson.build.
>
>
According to PoP, both 32- and 64-bit shifts use lowest 6 address
bits. The current code special-cases 32-bit shifts to use only 5 bits,
which is not correct. For example, shifting by 32 bits currently
preserves the initial value, however, it's supposed zero it out
instead.
Fix by merging sh32 and
The following changes since commit 91f5f7a5df1fda8c34677a7c49ee8a4bb5b56a36:
Merge remote-tracking branch
'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging
(2022-01-12 11:51:47 +)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags
Prepare virtio_scsi_handle_cmd() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd more
specific. This way it won't trigger when dataplane has already been
started.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Message-id: 202112071323
Philippe Mathieu-Daudé writes:
> Fix typo in 'make check-help' output.
Queued to testing/next, thanks.
--
Alex Bennée
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For example,
The virtqueue host notifier API
virtio_queue_aio_set_host_notifier_handler() polls the virtqueue for new
buffers. AioContext previously required a bool progress return value
indicating whether an event was handled or not. This is no longer
necessary because the AioContext polling API has been split
On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
>
> [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> package. If anyone wants to publish additional Python packages from
> qemu.git, please contact him for PyPI access.]
>
> On Tue, Jan 11, 2022 at 03:42:23PM -0500, J
Am 02.09.2021 um 11:37 hat Vladimir Sementsov-Ogievskiy geschrieben:
> First, this permission never protected a node from being changed, as
> generic child-replacing functions don't check it.
>
> Second, it's a strange thing: it presents a permission of parent node
> to change its child. But gener
The difference between ->handle_output() and ->handle_aio_output() was
that ->handle_aio_output() returned a bool return value indicating
progress. This was needed by the old polling API but now that the bool
return value is gone, the two functions can be unified.
Signed-off-by: Stefan Hajnoczi
R
The return value of virtio_blk_handle_vq() is no longer used. Get rid of
it. This is a step towards unifying the dataplane and non-dataplane
virtqueue handler functions.
Prepare virtio_blk_handle_output() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd
Now that virtio-blk and virtio-scsi are ready, get rid of
the handle_aio_output() callback. It's no longer needed.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Message-id: 20211207132336.36627-7-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio.h
On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
> >
> > [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> > package. If anyone wants to publish additional Python packages from
> > qemu.git, please contact
On Wed, Jan 12, 2022 at 5:07 AM Daniel P. Berrangé wrote:
>
> On Tue, Jan 11, 2022 at 02:48:55PM -0500, John Snow wrote:
> > On Fri, Dec 17, 2021 at 8:46 AM Daniel P. Berrangé
> > wrote:
> >
> > > On Thu, Dec 16, 2021 at 06:35:23PM -0500, John Snow wrote:
> > > > On Thu, Dec 16, 2021 at 5:48 AM D
On 11/01/2022 19:10, Sebastian Hasler wrote:
With the current implementation, blocking flock can lead to
deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts
to perform a blocking flock request.
Signed-off-by: Sebastian Hasler
---
tools/virtiofsd/passthrough_ll.c | 6 ++
On Wed, Jan 12, 2022 at 8:52 AM Beraldo Leal wrote:
>
> On Mon, Jan 10, 2022 at 06:28:53PM -0500, John Snow wrote:
> > We have a replacement for async QMP, but it doesn't have feature parity
> > yet. For now, then, port the old tool onto the new backend.
> >
> > Signed-off-by: John Snow
> > Revie
On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé wrote:
>
> On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
> > >
> > > [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> > > package. If anyone wants
On Wed, Jan 12, 2022 at 12:47:01PM -0500, John Snow wrote:
> On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé
> wrote:
> >
> > On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > > On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi
> > > wrote:
> > > >
> > > > [Context: John created
On Wed, Jan 12, 2022 at 12:51 PM Daniel P. Berrangé wrote:
>
> On Wed, Jan 12, 2022 at 12:47:01PM -0500, John Snow wrote:
> > On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé
> > wrote:
> > >
> > > On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > > > On Wed, Jan 12, 2022 at 5:56
Unfortunately I ran out of cycles at the time. Adding test cases seems
like it was the roadblock - I don't think I ever figured out how to
implement the needed build tests for this additional feature in chardev.
I'm not that strong of a C developer, unfortunately.
I haven't looked at picking this
Hi Hanna, Kevin:
I think this series is pretty close, it's mostly reviewed by Vladimir
and Beraldo. Only patches 22 and 23 touch iotests, and quite
minimally. Everything appears to test fine on my end, but I don't
wanna sneak any changes past you without an ACK.
(OK, admittedly, patch 22 is a tou
Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
> On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
>> the assumption that we can't hit a hole if we do not diff against a snapshot
>> was wrong.
>>
>> We can see a hole in an image if we diff against base if there exists an
>> older snapshot
>> of t
On Wed, Jan 12, 2022 at 9:39 PM Peter Lieven wrote:
>
> Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
> > On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
> >> the assumption that we can't hit a hole if we do not diff against a
> >> snapshot was wrong.
> >>
> >> We can see a hole in an image if
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or
a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is
sent to the processor. This can be used for diagnostic purposes like obtaining
a stack trace/register dump or to enter KDB/KGDB in Linux.
Th
This patchset fixes some important bugs in the hppa artist graphics driver:
- Fix framebuffer access for Linux
- Mouse cursor fixes for HP-UX
New qemu features for hppa:
- Allow up to 16 emulated CPUs (instead of 8)
- Add support for an emulated TOC/NMI button
A new Seabios-hppa firmware:
- Updat
This brings the hppa_hardware.h file in sync with the copy in the
SeaBIOS-hppa sources.
In order to support up to 16 CPUs, it's required to move the HPA for
MEMORY_HPA out of the address space of the 16th CPU.
Signed-off-by: Helge Deller
---
hw/hppa/hppa_hardware.h | 5 +++--
1 file changed, 3
This patch fixes two problems which prevented Linux to access the
artist graphics framebuffer:
The check if the framebuffer or the color map should be accessed was
incomplete. By using the vram_read/write_bufidx() functions we now check
correctly if ARTIST_BUFFER_CMAP should be accessed.
The seco
This patch fix the behaviour and positioning of the X11 mouse cursor in HP-UX.
The current code missed to subtract the offset of the CURSOR_CTRL register from
the current mouse cursor position. The HP-UX graphics driver stores in this
register the offset of the mouse graphics compared to the curre
On Wed, 12 Jan 2022 at 11:27, Alex Bennée wrote:
>
> The following changes since commit bf99e0ec9a51976868d7a8334620716df15fe7fe:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2022-01-11 10:12:29 +)
>
> are available in the Git repository at:
>
> https:/
> Am 12.01.2022 um 22:06 schrieb Ilya Dryomov :
>
> On Wed, Jan 12, 2022 at 9:39 PM Peter Lieven wrote:
>>
>>> Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
>>> On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
the assumption that we can't hit a hole if we do not diff against a
sn
On Thu, Dec 16, 2021 at 5:41 AM Daniel P. Berrangé wrote:
>
> On Wed, Dec 15, 2021 at 04:06:10PM -0500, John Snow wrote:
> > (2) To ask for permission to become the maintainer of a
> > 'qemu-project/qemu.qmp' repository, where I would like to host this
> > subproject.
>
> I'd say we need 3 design
+Sven
On 12/1/22 22:07, Helge Deller wrote:
This patch fixes two problems which prevented Linux to access the
artist graphics framebuffer:
The check if the framebuffer or the color map should be accessed was
incomplete. By using the vram_read/write_bufidx() functions we now check
correctly if A
Hi,
first-time contributor here. Inspired by an article in LWN [1] I figured I'd
get my hands dirty with QEMU development. According to the article my goal is
to eliminate some "accidental complexity".
While studying the code I noticed some (accidental?) differences between piix3
and piix4 where
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 58 +++
hw/mips/gt64xxx_pci.c | 62 --
hw/mips/malta.c
Passing own DeviceState rather than just the IRQs allows for resolving
global variables.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 6 +++---
hw/pci-host/sh_pci.c| 6 +++---
hw/pci-host/versatile.c | 6 +++---
hw/ppc/ppc440_pcix.c| 6 +++---
hw/ppc/ppc4xx_pci.c | 6
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c| 22 +-
include/hw/southbridge/piix.h | 2 --
2 files changed,
On Wed, 12 Jan 2022 17:40:44 +0100
Eric Farman wrote:
> After the recent restructuring, I'd like to volunteer to help
> in some of the s390 I/O areas.
>
> Built on "[PATCH RFC v2] MAINTAINERS: split out s390x sections"
>
> Signed-off-by: Eric Farman
Acked-by: Halil Pasic
Thanks!
> ---
> M
From: Hao Wu
Reviewed-by: Doug Evanwqs
Signed-off-by: Hao Wu
Signed-off-by: Patrick Venture
---
tests/qtest/meson.build | 1 +
tests/qtest/tmp_sbtsi-test.c | 161 +++
2 files changed, 162 insertions(+)
create mode 100644 tests/qtest/tmp_sbtsi-test.c
di
v2:
* Split the commit into a separate patch for the qtest
* Moved the common registers into the new header
* Introduced a new header
Hao Wu (2):
hw/sensor: Add SB-TSI Temperature Sensor Interface
tests: add qtest for hw/sensor/sbtsi
hw/sensor/Kconfig| 4 +
hw/sensor/meson.b
From: Hao Wu
SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
interface that reports AMD SoC's Ttcl (normalized temperature),
and resembles a typical 8-pin remote temperature sensor's I2C interface
to BMC.
This patch implements a basic AMD SB-TSI sensor that is
compatible with the
Since 32-bit versions of Windows still exist, there is a need to take
live and crash dumps of such guests along with 64-bit guests. So, add
an ability for 'dump-guest-memory -w' to take dumps from 32-bit guest.
When running the command QEMU consumes 32-bit Complete Memory Dump
header passed by gues
Perform read access to Windows dump header fields via helper macros.
This is preparation for the next 32-bit guest Windows dump support.
Signed-off-by: Viktor Prutyanov
---
dump/win_dump.c | 100 +++-
1 file changed, 65 insertions(+), 35 deletions(-)
Context structure in 64-bit Windows differs from 32-bit one and it
should be reflected in its name.
Signed-off-by: Viktor Prutyanov
---
contrib/elf2dmp/main.c | 6 +++---
dump/win_dump.c | 14 +++---
include/qemu/win_dump_defs.h | 8
3 files changed, 14 inse
These structures are required to produce 32-bit guest Windows Complete
Memory Dump. Add 32-bit Windows dump header, CPU context and physical
memory descriptor structures along with corresponding definitions.
Signed-off-by: Viktor Prutyanov
---
include/qemu/win_dump_defs.h | 107 +
Before this patch, 'dump-guest-memory -w' was accepting only 64-bit
dump header provided by guest through vmcoreinfo and thus was unable
to produce 32-bit guest Windows dump. So, add 32-bit guest Windows
dumping support.
Signed-off-by: Viktor Prutyanov
---
dump/win_dump.c | 231 +
On Wed, Jan 12, 2022 at 10:56:07AM +, Peter Maydell wrote:
> We could have vmstate_register_with_alias_id() iterate through
> and assert presence of the right terminator (probably only if
> qtest enabled, or some other suitable condition). Then the
> existing tests that do the basic "check we c
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 12
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
3 files changed, 24 insertions(+)
diff --git a/target/riscv/c
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 6 +-
target/riscv/csr.c| 25 -
target/riscv/translate.c | 4
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 89 +++
tar
This patchset implements RISC-V Float-Point in Integer Registers
extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin
extension.
Specification:
https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf
The port is available here:
https://github.com/plctlab/plct-qemu/tr
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fc3ec5bca1..d5e772b2b8 100644
--- a/target/riscv/cpu.c
+++ b
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 285 +---
target/risc
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