Re: [PATCH v3 0/3] hw/net: Move MV88W8618 network device out of hw/arm/ directory

On 1/6/22 15:48, Peter Maydell wrote: > On Fri, 17 Dec 2021 at 23:30, Philippe Mathieu-Daudé wrote: >> >> This series simply extract the MV88W8618 device from the ARM >> machine in hw/arm/ and move it to hw/net/. >> >> Since v2: >> - declare MARVELL_88W8618 in hw/arm/Kconfig >> - use MARVELL_88W86

[PATCH v4 0/3] hw/net: Move MV88W8618 network device out of hw/arm/ directory

This series simply extract the MV88W8618 device from the ARM machine in hw/arm/ and move it to hw/net/. Since v3: - Rebased on latest main/master Since v2: - declare MARVELL_88W8618 in hw/arm/Kconfig - use MARVELL_88W8618 Kconfig (rth) Since v1: - update (c) notice Philippe Mathieu-Daudé (3):

[PATCH v4 1/3] hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/

The Marvell 88W8618 is a system-on-chip with an ARM core. We implement its audio codecs and network interface. Homogeneous SoC Kconfig are usually defined in the hw/$ARCH directory. Move it there. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud

Re: [PATCH] meson: reenable filemonitor-inotify compilation

On 1/7/22 14:35, Volker Rümelin wrote: Reenable util/filemonitor-inotify compilation. Compilation was disabled when commit a620fbe9ac ("configure: convert compiler tests to meson, part 5") moved CONFIG_INOTIFY1 from config-host.mak to config-host.h. This fixes the usb-mtp device and reenables te

[PATCH v4 2/3] hw/arm/musicpal: Fix coding style of code related to MV88W8618 device

We are going to move this code, so fix its style first to avoid: ERROR: spaces required around that '/' (ctx:VxV) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/musicpal.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/a

[PATCH v4 3/3] hw/net: Move MV88W8618 network device out of hw/arm/ directory

The Marvell 88W8618 network device is hidden in the Musicpal machine. Move it into a new unit file under the hw/net/ directory. Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/net/mv88w8618_eth.h | 12 + hw/arm/musicpal.c | 381 +---

Re: [PATCH] hw/i386: Add the possibility to disable the 'isapc' machine

On 1/7/22 17:07, Thomas Huth wrote: > We already have a CONFIG_ISAPC switch - but we're not using it yet. > Add some "#ifdefs" to make it possible to disable this machine now. > > Signed-off-by: Thomas Huth > --- > hw/i386/pc_piix.c| 5 - > tests/qtest/cdrom-test.c | 2 +- > 2 files

Re: [PATCH v3 3/5] hw/arm/virt: Honor highmem setting when computing the memory map

On Fri, 7 Jan 2022 at 18:18, Marc Zyngier wrote: > This is a chicken and egg problem: you need the IPA size to compute > the memory map, and you need the memory map to compute the IPA > size. Fun, isn't it? > > At the moment, virt_set_memmap() doesn't know about the IPA space, > generates a highes

[PATCH 00/37] target/ppc: PowerISA Vector/VSX instruction batch

From: Matheus Ferst This patch series implements 5 missing instructions from PowerISA v3.0 and 40 new instructions from PowerISA v3.1, moving 62 other instructions to decodetree along the way. Lucas Coutinho (2): target/ppc: Move vexts[bhw]2[wd] to decodetree target/ppc: Implement vextsd2q

[PATCH 04/37] target/ppc: vmulh* instructions use gvec

From: "Lucas Mateus Castro (alqotel)" Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to use gvec instructions Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 +- target/ppc/int_helper.c | 8 +- target/ppc/transl

[PATCH 01/37] target/ppc: Introduce TRANS*FLAGS macros

From: Luis Pires New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Signed-off-by: Luis Pires [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst --- target/ppc/translate.c

[PATCH 02/37] target/ppc: moved vector even and odd multiplication to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub, vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw, muleuw and vmulouw from legacy to decodetree. Implemented the instructions vmulesd, vmulosd, vmuleud, vmuloud. Signed-off-by: Lucas Mateus Castro

[PATCH 09/37] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 30 -- target/ppc/insn32.decode| 24 target/ppc/int_helper.c | 54 - target/ppc/translate/vmx-impl.c.inc | 91 - target

[PATCH 06/37] target/ppc: Implement vmsumudm instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl

[PATCH 03/37] target/ppc: Moved vector multiply high and low to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 target/ppc/insn32.decode| 6 ++

[PATCH 05/37] target/ppc: Implement vmsumcud instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 +++ target/ppc/translate/vmx-im

[PATCH 10/37] target/ppc: Move Vector Compare Not Equal or Zero to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 9 ++-- target/ppc/insn32.decode| 4 ++ target/ppc/int_helper.c | 50 + target/ppc/translate/vmx-impl.c.inc | 69 +++-- target/ppc/tra

[PATCH 08/37] target/ppc: Implement vextsd2q

From: Lucas Coutinho Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index

[PATCH 13/37] target/ppc: Implement Vector Compare Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/translate/vmx-impl.c.inc | 45 +

[PATCH 07/37] target/ppc: Move vexts[bhw]2[wd] to decodetree

From: Lucas Coutinho Move the following instructions to decodetree: vextsb2w: Vector Extend Sign Byte To Word vextsh2w: Vector Extend Sign Halfword To Word vextsb2d: Vector Extend Sign Byte To Doubleword vextsh2d: Vector Extend Sign Halfword To Doubleword vextsw2d: Vector Extend Sign Word To Doub

[PATCH 17/37] target/ppc: implement vcntmb[bhwd]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 923286e37f..a

[PATCH 15/37] target/ppc: implement vclrlb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 56 + 2 files changed, 58 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 57fd6407fa..f718f29

[PATCH 12/37] target/ppc: Implement Vector Compare Greater Than Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.in

[PATCH 11/37] target/ppc: Implement Vector Compare Equal Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpequq Vector Compare Equal Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 + 2 files changed, 44 insertions(+)

[PATCH 14/37] target/ppc: implement vstri[bh][lr]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 10 + target/ppc/int_helper.c | 32 + target/ppc/translate/vmx-impl.c.inc | 24 ++ 4 file

[PATCH 20/37] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 - 4 files

[PATCH 21/37] target/ppc: move xxperm/xxpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42 +++-- target/ppc/translate

[PATCH 26/37] target/ppc: Implement xxgenpcv[bhwd]m instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++ target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 84 + target/ppc/translate/vsx-impl.c.inc | 29 ++ 4 files changed, 127 inse

[PATCH 22/37] target/ppc: Move xxpermdi to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/target/ppc/insn3

[PATCH 16/37] target/ppc: implement vclrrb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 +++-- 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f718

[PATCH 24/37] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146 ++ 2 files changed, 168 i

[PATCH 28/37] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]

From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision

[PATCH 25/37] target/ppc: Implement xxeval

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 ++ target/ppc/int_helper.c | 42 ++ target/ppc/translate/vsx-impl.c.inc | 121 4 files changed, 172 inse

[PATCH 23/37] target/ppc: Implement xxpermx instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22 ++ 4 files changed, 51

[PATCH 19/37] target/ppc: Move vsel and vperm/vpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69 ++--- target/ppc/translate/vmx-ops.

[PATCH 30/37] target/ppc: Refactor VSX_SCALAR_CMP_DP

From: Victor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 33 +++-- 1 file changed, 15 in

[PATCH 29/37] target/ppc: Implement xvtlsbb instruction

From: Victor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 7 ++ target/ppc/translate/vsx-impl.c.inc | 37 + 2 files changed, 44 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/ins

[PATCH 18/37] target/ppc: implement vgnb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 target/ppc/translate/vmx-impl.c.inc | 44 + 2 files changed, 49 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a674e06727..15f4d

[PATCH 35/37] target/ppc: Refactor VSX_MAX_MINC helper

From: Victor Colombo Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for xs{max,min}cqp implementation. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/ta

[PATCH 31/37] target/ppc: Implement xscmp{eq,ge,gt}qp

From: Victor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 4 target/ppc/helper.h | 3 +++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 31 +

Re: [PATCH] configure: do not create roms/seabios/config.mak if SeaBIOS not present

On 1/7/22 3:47 AM, Paolo Bonzini wrote: If roms/seabios/Makefile is not present, the configure script is not creating the roms/seabios directory anymore (commit 5dce7b8d8c, "configure: remove DIRS", 2021-12-18); thus, creating roms/seabios/config.mak fails. The easiest thing to do is to not crea

[PATCH 27/37] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 ++-- target/ppc/helper.h | 16 - target/ppc/insn32.decode| 22 target/ppc/translate/vsx-impl.c.inc | 56 - target/p

[PATCH 32/37] target/ppc: Implement do_helper_XX3 and move xxperm* to use it

From: Víctor Colombo do_helper_XX3 is a wrapper for instructions that only call its helper. It will be used later to implement instructions like xscmp*dp. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/translate/vsx-impl.c.inc | 26 +- 1 file

[PATCH 37/37] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- xvcvspbf16 implementation is incorrectly setting both XX and FI bits in FPSCR, while the hardware sets only XX bit (as stated in the ISA). This happens because do_float_check_status calls float_inexact_excp, whi

Re: [PATCH v3 3/5] hw/arm/virt: Honor highmem setting when computing the memory map

On Fri, 07 Jan 2022 18:48:16 +, Peter Maydell wrote: > > On Fri, 7 Jan 2022 at 18:18, Marc Zyngier wrote: > > This is a chicken and egg problem: you need the IPA size to compute > > the memory map, and you need the memory map to compute the IPA > > size. Fun, isn't it? > > > > At the moment,

[PATCH 33/37] target/ppc: Move xscmp{eq,ge,gt,ne}dp to decodetree

From: Victor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 9 - target/ppc/helper.h | 8 target/ppc/insn32.decode| 4 target/ppc/translate/vsx-impl.c.inc | 8 target/ppc/tr

[PATCH 34/37] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3

From: Víctor Colombo Also, fixes these instructions not being capitalized. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 8 target/ppc/helper.h | 8 target/ppc/translate/vsx-impl.c.inc | 30

Re: [PATCH] softmmu/device_tree: Silence compiler warning with --enable-sanitizers

On 1/7/22 5:38 AM, Thomas Huth wrote: diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c index 3965c834ca..9e96f5ecd5 100644 --- a/softmmu/device_tree.c +++ b/softmmu/device_tree.c @@ -564,7 +564,7 @@ int qemu_fdt_add_path(void *fdt, const char *path) return -1; } -

[PATCH 36/37] target/ppc: Implement xs{max,min}cqp

From: Victor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 2 ++ 4 files changed, 9 insertions(+)

Re: [PATCH v3] hw/arm/virt: KVM: Enable PAuth when supported by the host

On 1/7/22 7:01 AM, Marc Zyngier wrote: @@ -1380,17 +1380,10 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } -/* - * KVM does not support modifications to this feature. - * We have not registered the cpu properties when KV

Re: [PULL v2 00/55] virtio,pci,pc: features,fixes,cleanups

On 1/7/22 3:03 AM, Michael S. Tsirkin wrote: Changes from v1: - mingw build fixes - added TPM patches which got acks meanwhile Big changes that were tagged originally but did not make the cut: - SRIOV/nvme (not sure they are my tree material anyway) - ACPI ERST (some coding style violations) Th

Re: [PATCH] docs: Add measurement calculation details to amd-memory-encryption.txt

On Thu, Dec 16, 2021 at 11:41:27PM +0200, Dov Murik wrote: > > > On 16/12/2021 18:09, Daniel P. Berrangé wrote: > > On Thu, Dec 16, 2021 at 12:38:34PM +0200, Dov Murik wrote: > >> > >> > >> On 14/12/2021 20:39, Daniel P. Berrangé wrote: > >>> Is there any practical guidance we can give apps on th

Re: [PATCH] target/arm/cpu64: Use 32-bit GDBstub when running in 32-bit KVM mode

On 1/7/22 7:54 AM, Ard Biesheuvel wrote: diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 15245a60a8c7..3dede9e2ec31 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -903,9 +903,15 @@ static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) return arm_feature(&cp

Re: [PATCH V7 00/29] Live Update

Hi Dave, It has been a long time since we chatted about this series. The vfio patches have been updated with feedback from Alex and are close to being final (I think). Could you take another look at the patches that you care about? To refresh your memory, you last reviewed V3 of the series,

Re: [PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx

On 1/7/22 3:27 AM, Weiwei Li wrote: @@ -342,6 +342,11 @@ static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; +/* hardwire mstatus.FS to zero when enable zfinx */ +if (ctx->ext_zfinx) { +return; +} + if (ctx->mstatus_fs != MSTATUS_FS) { This should also

Re: [PATCH v3 4/6] target/riscv: add support for zdinx

On 1/7/22 3:27 AM, Weiwei Li wrote: +#define REQUIRE_EVEN(ctx, reg) do { \ +if (ctx->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \ +(reg & 0x1)) { \ +return false; \ +} \ +} while (0) Parenthesis around reg. +REQUIRE_EVEN(ctx, a->rd); +REQUIRE_EVEN(ctx, a->rs1);

Re: [PATCH v2 17/18] ppc/pnv: Introduce user creatable pnv-phb4 devices

On 1/6/22 11:49, Cédric Le Goater wrote: On 1/5/22 22:23, Daniel Henrique Barboza wrote: This patch introduces pnv-phb4 user creatable devices that are created in a similar manner as pnv-phb3 devices, allowing the user to interact with the PHBs directly instead of creating PCI Express Control

Re: [PULL 00/19] target-arm queue

ository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220107 for you to fetch changes up to b8905cc2dde95ca6be5e56d77053b1ca0b8fc182: hw/arm: kudo add lm75s on bus 13 (2022-01-07 17:08:01 +)

[PATCH v5 00/24] linux-user: Clean up siginfo_t handling

Changes from v4: * Rebase on master. All patches are reviewed. r~ Richard Henderson (24): linux-user/alpha: Set TRAP_UNK for bugchk and unknown gentrap linux-user/alpha: Set FPE_FLTUNK for gentrap ROPRAND linux-user/alpha: Use force_sig_fault linux-user/cris: Use force_sig_fault li

[PATCH v5 06/24] linux-user/hppa: Use the proper si_code for PRIV_OPR, PRIV_REG, OVERFLOW

These si_codes have been properly set by the kernel since the beginning. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loo

[PATCH v5 02/24] linux-user/alpha: Set FPE_FLTUNK for gentrap ROPRAND

This si_code was changed in 4cc13e4f6d441, for linux 4.17. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 96466b23f9..

[PATCH v5 08/24] linux-user/hppa: Set FPE_CONDTRAP for COND

This si_code was changed in 75abf64287cab, for linux 4.17. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 1 + linux-user/hppa/cpu_loop.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_

[PATCH v5 03/24] linux-user/alpha: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 61 - 1 file changed, 19 insertions(+), 42 deletions(-) diff --git a/linux-u

[PATCH v5 01/24] linux-user/alpha: Set TRAP_UNK for bugchk and unknown gentrap

These si_codes were changed in 535906c684fca, for linux 4.17. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 1 + linux-user/alpha/cpu_loop.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/syscall_defs.h b/linux

[PATCH v5 07/24] linux-user: Remove TARGET_NSIGFPE

This define is unused, and we have no similar define for the other signal sub-codes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 1 - 1 file changed, 1 deletion(-) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index

[PATCH v5 09/24] linux-user/i386: Split out maybe_handle_vm86_trap

Reduce the number of ifdefs within cpu_loop(). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 31 +++ 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c

[PATCH v5 10/24] linux-user/i386: Use force_sig, force_sig_fault

Replace the local gen_signal with the generic functions that match how the kernel raises signals. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/i386/cpu_loop.c | 47 +++--- 1 file changed, 18 insert

[PATCH v5 05/24] linux-user/hppa: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP and missing si_code for SIGBUS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 18 +++--- 1 file changed, 3 inser

[PATCH v5 04/24] linux-user/cris: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/cris/cpu_loop.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git

[PATCH v5 12/24] linux-user/microblaze: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 61 +--- 1 file changed, 25 insertions(+), 3

[PATCH v5 11/24] linux-user/m68k: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 24 1 file changed, 4 insertions(+), 20 deletions(-)

[PATCH v5 17/24] target/mips: Extract trap code into env->error_code

Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c| 41 +-- target/mips/tcg/translate.c | 24 ++--- target/mips/tcg/micromips_tra

[PATCH v5 15/24] linux-user/mips: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP and SIGFPE; use force_sig (SI_KERNEL) for EXCP_DSPDIS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/mips/cpu_loop.c | 38 +

[PATCH v5 21/24] linux-user/s390x: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/s390x/cpu_loop.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/

[PATCH v5 19/24] linux-user/ppc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. The fault address for POWERPC_EXCP_ISI is nip exactly, not nip - 4. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 136 ++

[PATCH v5 13/24] linux-user/microblaze: Fix SIGFPE si_codes

Fix a typo for ESR_EC_DIVZERO, which is integral not floating-point. Fix the if ladder for decoding floating-point exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletion

[PATCH v5 14/24] linux-user/mips: Improve do_break

Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the return value to void. Use force_sig and force_sig_fault. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linu

[PATCH v5 24/24] linux-user/xtensa: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/xtensa/cpu_loop.c | 26 +- 1 file changed, 9 insertions(+), 17 deletions

[PATCH v5 16/24] target/mips: Extract break code into env->error_code

Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Reviewed-by: Philippe Mathieu-Daudé Si

ui/cocoa.m compile error

Hi, I'm building 6.2.0 on macOS, and on a recent macOS 11.6 with Apple Silicon the build passes, but on a slightly older macOS 10.13, which is my base platform for Intel macOS builds, compiling ui/cocoa.m fails: ``` ../../sources/qemu-6.2.0.git/ui/cocoa.m:1766:52: error: unknown type name 'NSP

[PATCH v5 18/24] linux-user/openrisc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-)

[PATCH v5 20/24] linux-user/riscv: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fix missing PC from EXCP_DEBUG by merging the case with EXCP_BREAKPOINT. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 31 +-- 1 f

[PATCH v5 22/24] linux-user/sh4: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/sh4/cpu_loop.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/linux-us

[PATCH v5 23/24] linux-user/sparc: Use force_sig_fault

Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --g

Re: ui/cocoa.m compile error

On Fri, 7 Jan 2022 at 21:56, Liviu Ionescu wrote: > I'm building 6.2.0 on macOS, and on a recent macOS 11.6 with > Apple Silicon the build passes, but on a slightly older macOS > 10.13, which is my base platform for Intel macOS builds, > compiling ui/cocoa.m fails QEMU's supported-hosts policy ht

[PATCH v3 2/8] target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs active

Remove the compile time definition and make the logging be controlled by the `-d mmu` option in the cmdline. Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Reviewed-by: David Gibson --- target/ppc/excp_helper.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git

[PATCH v3 3/8] target/ppc: powerpc_excp: Group unimplemented exceptions

Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Richard Henderson --- target/ppc/excp_helper.c | 77 +--- 1 file changed, 8 insertions(+), 69 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/e

[PATCH v3 7/8] target/ppc: Introduce a wrapper for powerpc_excp

Next patches will split powerpc_excp in multiple family specific handlers. This patch adds a wrapper to make the transition clearer. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/excp_helper.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git

[PATCH v3 0/8] target/ppc: powerpc_excp improvements (2/n)

Version 3: - patches 1,3,4,5,6,7: unchanged, reviewed; - patch 2: started using qemu_loglevel_mask(CPU_LOG_MMU) instead of qemu_log_enabled; I decided to not rename the function at this point because it is used for both 60x and 7x5 and these two will be split

[PATCH v3 4/8] target/ppc: Add HV support to ppc_interrupts_little_endian

The ppc_interrupts_little_endian function could be used for interrupts delivered in Hypervisor mode, so add support for powernv8 and powernv9 to it. Also drop the comment because it is inaccurate, all CPUs that can run little endian can have interrupts in little endian. The point is whether they c

[PATCH v3 8/8] target/ppc: Set the correct endianness for powernv memory dumps

We use the endianness of interrupts to determine which endianness to use for the guest kernel memory dump. For machines that support HILE (powernv8 and up) we have been always generating big endian dump files. This patch uses the HILE support recently added to ppc_interrupts_little_endian to fix t

[PATCH v3 1/8] target/ppc: powerpc_excp: Extract software TLB logging into a function

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Reviewed-by: Richard Henderson --- target/ppc/excp_helper.c | 63 +++- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a779dc936a.

[PATCH] tests/qtest: add qtests for npcm7xx sdhci

From: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Signed-off-by: Shengtan Mao --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_sdhci-test.c | 201 +++ 2 files changed, 202 insertions(+) create mode 100644 tests/qtest/npcm7xx_sdhci-te

[PATCH v3 5/8] target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian

Some CPUs set ILE via an MSR bit. We can make ppc_interrupts_little_endian handle that case as well. Now we have a centralized way of determining the endianness of interrupts. This change has no functional impact. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu.h | 4

[PATCH v3 6/8] target/ppc: Use ppc_interrupts_little_endian in powerpc_excp

The ppc_interrupts_little_endian function is now suitable for determining the endianness of interrupts for all CPUs. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/excp_helper.c | 29 + 1 file changed, 1 insertion(+), 28 deletions(-) diff --gi

Re: [PATCH v2] q800: fix segfault with invalid MacROM

On 07/01/2022 10:50, Laurent Vivier wrote: "qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault in q800_init(). This happens because the code doesn't check that rom_ptr() returned a non-NULL pointer . To avoid NULL pointer, don't allow 0 sized file and use bios_size with rom_ptr()

Re: [OpenBIOS] Re: [RFC PATCH 0/2] QEMU/openbios: PPC Software TLB support in the G4 family

On 07/01/2022 13:51, Cédric Le Goater wrote: Hello, a quick status on how QEMU has evolved regarding this topic. We have merged :     a09410ed1fb8 ("target/ppc: Remove the software TLB model of 7450 CPUs") and switched MMU model to POWERPC_MMU_32B in :     1da666cd8e79 ("target/ppc: Disable

Re: ui/cocoa.m compile error

> On 8 Jan 2022, at 00:16, Peter Maydell wrote: > > ... In this > specific case, NSPasteboardTypeOwner seems to be part of > an API introduced in 10.14 (Mojave). Thank you for the details, this explains the error. > So the upstream answer, I'm afraid, is that you should > upgrade to a newer

Re: [PATCH] softmmu/device_tree: Silence compiler warning with --enable-sanitizers

On Fri, Jan 7, 2022 at 11:41 PM Thomas Huth wrote: > > If I configure my build with --enable-sanitizers, my GCC (v8.5.0) > complains: > > .../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’: > .../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized > in this function [-

Re: [PULL v2 00/55] virtio,pci,pc: features,fixes,cleanups

On Fri, Jan 07, 2022 at 11:38:21AM -0800, Richard Henderson wrote: > On 1/7/22 3:03 AM, Michael S. Tsirkin wrote: > > Changes from v1: > > - mingw build fixes > > - added TPM patches which got acks meanwhile > > > > Big changes that were tagged originally but did not make the cut: > > - SRIOV/nvme

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